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* target-arm: Override do_interrupt for ARMv7-M profileAndreas Färber2013-03-121-5/+5
* cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber2013-03-121-4/+7
* cpu: Pass CPUState to cpu_interrupt()Andreas Färber2013-03-121-1/+1
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-1/+3
* ARM: KVM: Add support for KVM on ARM architectureChristoffer Dall2013-03-051-1/+1
* target-arm: Drop CPUARMState* argument from bank_number()Peter Maydell2013-03-051-7/+6
* target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson2013-02-231-5/+0
* target-arm: Move TCG initialization to ARMCPU initfnAndreas Färber2013-02-161-6/+0
* target-arm: Update ARMCPU to QOM realizefnAndreas Färber2013-02-161-4/+10
* target-arm: Rename CPU typesAndreas Färber2013-01-301-3/+8
* target-arm: Detect attempt to instantiate non-CPU type in cpu_init()Andreas Färber2013-01-271-2/+4
* cpu: Move cpu_index field to CPUStateAndreas Färber2013-01-151-1/+2
* target-arm: Fix SWI (SVC) instruction in M profile.Alex_Rozenman@mentor.com2013-01-111-1/+1
* Merge branch 'master' of git://git.qemu.org/qemu into qom-cpuAndreas Färber2012-12-231-4/+4
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| * softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
| * misc: move include files to include/qemu/Paolo Bonzini2012-12-191-2/+2
| * exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
* | cpu: Introduce CPUListState structAndreas Färber2012-12-191-7/+2
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* target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell2012-10-241-5/+0
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-14/+14
* target-arm: final conversion to AREG0 free modeBlue Swirl2012-09-151-4/+5
* target-arm: Fix potential buffer overflowStefan Weil2012-09-101-2/+2
* target-arm: Fix typos in commentsPeter Maydell2012-08-101-3/+3
* target-arm: Add support for long format translation table walksPeter Maydell2012-07-121-0/+182
* target-arm: Implement TTBCR changes for LPAEPeter Maydell2012-07-121-1/+14
* target-arm: Implement long-descriptor PAR formatPeter Maydell2012-07-121-10/+69
* target-arm: Use target_phys_addr_t in get_phys_addr()Peter Maydell2012-07-121-14/+15
* target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell2012-07-121-1/+76
* target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAEPeter Maydell2012-07-121-0/+5
* target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registersPeter Maydell2012-07-121-0/+16
* target-arm: Implement privileged-execute-never (PXN)Peter Maydell2012-07-121-12/+20
* target-arm: Fix some copy-and-paste errors in cp register namesPeter Maydell2012-07-121-3/+3
* target-arm: Fix typo that meant TTBR1 accesses went to TTBR0Peter Maydell2012-07-121-1/+1
* target-arm: Remove remaining old cp15 infrastructurePeter Maydell2012-06-201-39/+0
* target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2012-06-201-0/+13
* target-arm: Convert final ID registersPeter Maydell2012-06-201-48/+68
* target-arm: Convert MPIDRPeter Maydell2012-06-201-22/+28
* target-arm: Convert cp15 cache ID registersPeter Maydell2012-06-201-28/+33
* target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell2012-06-201-8/+54
* target-arm: Convert cp15 crn=1 registersPeter Maydell2012-06-201-75/+54
* target-arm: Convert cp15 crn=9 registersPeter Maydell2012-06-201-79/+25
* target-arm: Convert cp15 crn=6 registersPeter Maydell2012-06-201-53/+35
* target-arm: convert cp15 crn=7 registersPeter Maydell2012-06-201-11/+52
* target-arm: Convert cp15 VA-PA translation registersPeter Maydell2012-06-201-43/+65
* target-arm: Convert cp15 MMU TLB controlPeter Maydell2012-06-201-20/+43
* target-arm: Convert cp15 crn=15 registersPeter Maydell2012-06-201-115/+87
* target-arm: Convert cp15 crn=10 registersPeter Maydell2012-06-201-6/+5
* target-arm: Convert cp15 crn=13 registersPeter Maydell2012-06-201-30/+31
* target-arm: Convert cp15 crn=2 registersPeter Maydell2012-06-201-55/+33
* target-arm: Convert MMU fault status cp15 registersPeter Maydell2012-06-201-81/+107
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