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path: root/target-arm/cpu.h
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* target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2014-08-191-0/+21
* target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell2014-08-191-0/+21
* target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell2014-08-191-0/+61
* target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell2014-08-191-2/+10
* target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2014-08-041-1/+1
* target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2014-08-041-1/+1
* target-arm: Make far_el1 an arrayEdgar E. Iglesias2014-08-041-1/+1
* target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2014-06-191-0/+16
* target-arm: add support for v8 VMULL.P64 instructionPeter Maydell2014-06-091-0/+1
* target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel2014-06-091-0/+2
* target-arm: move arm_*_code to a separate filePaolo Bonzini2014-06-051-22/+0
* target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2014-05-271-1/+1
* target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2014-05-271-1/+1
* target-arm: Add a feature flag for EL3Edgar E. Iglesias2014-05-271-0/+1
* target-arm: Add a feature flag for EL2Edgar E. Iglesias2014-05-271-0/+1
* target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias2014-05-271-1/+3
* target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias2014-05-271-1/+1
* target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias2014-05-271-1/+1
* target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias2014-05-271-1/+1
* target-arm: Make esr_el1 an arrayEdgar E. Iglesias2014-05-271-1/+1
* target-arm: Make elr_el1 an arrayEdgar E. Iglesias2014-05-271-1/+1
* target-arm: Use a 1:1 mapping between EL and MMU indexEdgar E. Iglesias2014-05-271-4/+4
* target-arm: Implement CBAR for Cortex-A57Peter Maydell2014-04-171-0/+1
* target-arm: Implement AArch64 address translation operationsPeter Maydell2014-04-171-2/+1
* target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell2014-04-171-1/+1
* target-arm: Implement ARMv8 MVFR registersPeter Maydell2014-04-171-0/+1
* target-arm: Implement AArch64 SPSR_EL1Peter Maydell2014-04-171-1/+1
* target-arm: Implement SP_EL0, SP_EL1Peter Maydell2014-04-171-0/+2
* target-arm: Add AArch64 ELR_EL1 register.Peter Maydell2014-04-171-0/+2
* target-arm: Implement AArch64 views of fault status and data registersRob Herring2014-04-171-4/+3
* target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell2014-04-171-0/+2
* target-arm: A64: Implement DC ZVAPeter Maydell2014-04-171-1/+2
* target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell2014-04-171-1/+9
* target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell2014-04-171-0/+9
* target-arm: Define exception record for AArch64 exceptionsPeter Maydell2014-04-171-0/+15
* target-arm: Implement AArch64 DAIF system registerPeter Maydell2014-04-171-1/+1
* target-arm: Split out private-to-target functions into internals.hPeter Maydell2014-04-171-20/+0
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-3/+2
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-6/+0
* target-arm: Implements the ARM PMCCNTR registerAlistair Francis2014-03-101-0/+4
* target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton2014-02-261-0/+1
* target-arm: Add utility function for checking AA32/64 state of an ELPeter Maydell2014-02-261-0/+16
* target-arm: Implement AArch64 view of CPACRPeter Maydell2014-02-261-1/+1
* target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell2014-02-261-3/+9
* target-arm: Get MMU index information correct for A64 codePeter Maydell2014-02-261-3/+8
* target-arm: Implement AArch64 dummy breakpoint and watchpoint registersPeter Maydell2014-02-261-0/+4
* target-arm: Implement AArch64 generic timersPeter Maydell2014-02-261-3/+3
* target-arm: Implement AArch64 TTBR*Peter Maydell2014-02-261-4/+2
* target-arm: Implement AArch64 VBAR_EL1Peter Maydell2014-02-261-1/+1
* target-arm: Implement AArch64 TCR_EL1Peter Maydell2014-02-261-1/+1
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