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* target-arm: make MAIR0/1 bankedGreg Bellows2014-12-111-1/+20
* target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler2014-12-111-5/+31
* target-arm: make VBAR bankedGreg Bellows2014-12-111-1/+9
* target-arm: make PAR bankedFabian Aggeler2014-12-111-1/+9
* target-arm: make IFAR/DFAR bankedFabian Aggeler2014-12-111-1/+18
* target-arm: make DFSR bankedFabian Aggeler2014-12-111-1/+9
* target-arm: make IFSR bankedFabian Aggeler2014-12-111-1/+9
* target-arm: make DACR bankedFabian Aggeler2014-12-111-2/+11
* target-arm: make TTBCR bankedFabian Aggeler2014-12-111-3/+8
* target-arm: make TTBR0/1 bankedFabian Aggeler2014-12-111-2/+18
* target-arm: make CSSELR bankedFabian Aggeler2014-12-111-1/+9
* target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler2014-12-111-1/+9
* target-arm: add MVBAR supportFabian Aggeler2014-12-111-0/+1
* target-arm: add SDER definitionGreg Bellows2014-12-111-0/+1
* target-arm: add NSACR registerFabian Aggeler2014-12-111-0/+1
* target-arm: add secure state bit to CPREG hashPeter Maydell2014-12-111-5/+20
* target-arm: add CPREG secure state supportFabian Aggeler2014-12-111-2/+34
* target-arm: add non-secure Translation Block flagSergey Fedorov2014-12-111-0/+27
* target-arm: add banked register accessorsFabian Aggeler2014-12-111-0/+27
* target-arm: extend async excp maskingGreg Bellows2014-12-111-14/+52
* target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell2014-11-041-2/+2
* target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell2014-11-041-14/+2
* target-arm: make arm_current_el() return EL3Fabian Aggeler2014-10-241-9/+20
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-241-12/+15
* target-arm: add arm_is_secure() functionFabian Aggeler2014-10-241-0/+47
* target-arm: increase arrays of registers R13 & R14Fabian Aggeler2014-10-241-2/+2
* target-arm: add emulation of PSCI calls for system emulationRob Herring2014-10-241-0/+6
* target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias2014-09-291-3/+32
* target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias2014-09-291-0/+10
* target-arm: A64: Emulate the SMC insnEdgar E. Iglesias2014-09-291-0/+1
* target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias2014-09-291-0/+1
* target-arm: A64: Emulate the HVC insnEdgar E. Iglesias2014-09-291-0/+1
* target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias2014-09-291-0/+7
* target-arm: Break out exception masking to a separate funcEdgar E. Iglesias2014-09-291-0/+15
* target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias2014-09-291-0/+7
* target-arm: Add SCR_EL3Edgar E. Iglesias2014-09-291-1/+18
* target-arm: Add HCR_EL2Edgar E. Iglesias2014-09-291-0/+36
* target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell2014-09-291-0/+9
* target-arm: Implement setting guest breakpointsPeter Maydell2014-09-291-0/+1
* target-arm: Implement setting of watchpointsPeter Maydell2014-09-121-0/+2
* target-arm: Implement pmccntr_sync functionAlistair Francis2014-08-291-0/+11
* target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2014-08-291-2/+3
* target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2014-08-291-1/+1
* target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell2014-08-291-1/+8
* target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2014-08-191-0/+21
* target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell2014-08-191-0/+21
* target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell2014-08-191-0/+61
* target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell2014-08-191-2/+10
* target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2014-08-041-1/+1
* target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2014-08-041-1/+1
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