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path: root/target-arm/cpu.h
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* target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell2014-11-041-2/+2
* target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell2014-11-041-14/+2
* target-arm: make arm_current_el() return EL3Fabian Aggeler2014-10-241-9/+20
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-241-12/+15
* target-arm: add arm_is_secure() functionFabian Aggeler2014-10-241-0/+47
* target-arm: increase arrays of registers R13 & R14Fabian Aggeler2014-10-241-2/+2
* target-arm: add emulation of PSCI calls for system emulationRob Herring2014-10-241-0/+6
* target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias2014-09-291-3/+32
* target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias2014-09-291-0/+10
* target-arm: A64: Emulate the SMC insnEdgar E. Iglesias2014-09-291-0/+1
* target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias2014-09-291-0/+1
* target-arm: A64: Emulate the HVC insnEdgar E. Iglesias2014-09-291-0/+1
* target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias2014-09-291-0/+7
* target-arm: Break out exception masking to a separate funcEdgar E. Iglesias2014-09-291-0/+15
* target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias2014-09-291-0/+7
* target-arm: Add SCR_EL3Edgar E. Iglesias2014-09-291-1/+18
* target-arm: Add HCR_EL2Edgar E. Iglesias2014-09-291-0/+36
* target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell2014-09-291-0/+9
* target-arm: Implement setting guest breakpointsPeter Maydell2014-09-291-0/+1
* target-arm: Implement setting of watchpointsPeter Maydell2014-09-121-0/+2
* target-arm: Implement pmccntr_sync functionAlistair Francis2014-08-291-0/+11
* target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2014-08-291-2/+3
* target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2014-08-291-1/+1
* target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell2014-08-291-1/+8
* target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2014-08-191-0/+21
* target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell2014-08-191-0/+21
* target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell2014-08-191-0/+61
* target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell2014-08-191-2/+10
* target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2014-08-041-1/+1
* target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2014-08-041-1/+1
* target-arm: Make far_el1 an arrayEdgar E. Iglesias2014-08-041-1/+1
* target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2014-06-191-0/+16
* target-arm: add support for v8 VMULL.P64 instructionPeter Maydell2014-06-091-0/+1
* target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel2014-06-091-0/+2
* target-arm: move arm_*_code to a separate filePaolo Bonzini2014-06-051-22/+0
* target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2014-05-271-1/+1
* target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2014-05-271-1/+1
* target-arm: Add a feature flag for EL3Edgar E. Iglesias2014-05-271-0/+1
* target-arm: Add a feature flag for EL2Edgar E. Iglesias2014-05-271-0/+1
* target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias2014-05-271-1/+3
* target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias2014-05-271-1/+1
* target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias2014-05-271-1/+1
* target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias2014-05-271-1/+1
* target-arm: Make esr_el1 an arrayEdgar E. Iglesias2014-05-271-1/+1
* target-arm: Make elr_el1 an arrayEdgar E. Iglesias2014-05-271-1/+1
* target-arm: Use a 1:1 mapping between EL and MMU indexEdgar E. Iglesias2014-05-271-4/+4
* target-arm: Implement CBAR for Cortex-A57Peter Maydell2014-04-171-0/+1
* target-arm: Implement AArch64 address translation operationsPeter Maydell2014-04-171-2/+1
* target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell2014-04-171-1/+1
* target-arm: Implement ARMv8 MVFR registersPeter Maydell2014-04-171-0/+1
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