summaryrefslogtreecommitdiffstats
path: root/target-arm/cpu.c
Commit message (Expand)AuthorAgeFilesLines
* target-arm: Add CPU property to disable AArch64Greg Bellows2015-02-131-1/+4
* target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64Pranavkumar Sawargaonkar2015-02-051-0/+24
* target-arm: Change reset to highest available ELGreg Bellows2015-02-051-1/+8
* target-arm: add cpu feature EL3 to CPUs with Security ExtensionsFabian Aggeler2014-12-221-0/+4
* target-arm: Add ARMCPU secure propertyGreg Bellows2014-12-221-0/+23
* target-arm: Add feature unset functionGreg Bellows2014-12-221-0/+5
* target-arm: make IFAR/DFAR bankedFabian Aggeler2014-12-111-1/+1
* target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler2014-12-111-2/+6
* target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell2014-11-041-10/+39
* target-arm: Correct sense of the DCZID DZP bitPeter Maydell2014-10-241-2/+2
* target-arm: add emulation of PSCI calls for system emulationRob Herring2014-10-241-3/+7
* target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring2014-10-241-1/+1
* target-arm: add powered off cpu stateRob Herring2014-10-241-1/+7
* gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell2014-10-061-0/+1
* target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias2014-09-291-11/+36
* target-arm: Break out exception masking to a separate funcEdgar E. Iglesias2014-09-291-5/+2
* target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell2014-09-291-5/+0
* target-arm: Implement setting guest breakpointsPeter Maydell2014-09-291-0/+1
* target-arm: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-251-0/+34
* target-arm: Implement handling of fired watchpointsPeter Maydell2014-09-121-0/+1
* target-arm: Implement setting of watchpointsPeter Maydell2014-09-121-0/+2
* target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan2014-09-121-1/+1
* target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan2014-09-121-10/+22
* arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite2014-08-191-2/+2
* target-arm: Adjust debug ID registers per-CPUPeter Maydell2014-08-191-0/+3
* target-arm: Make far_el1 an arrayEdgar E. Iglesias2014-08-041-1/+1
* target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar2014-06-191-0/+1
* target-arm: VFPv4 implies half-precision extensionPeter Maydell2014-06-091-2/+1
* target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell2014-06-091-4/+4
* target-arm: Remove unnecessary setting of feature bitsPeter Maydell2014-06-091-2/+0
* target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell2014-06-091-3/+0
* target-arm: add support for v8 VMULL.P64 instructionPeter Maydell2014-06-091-0/+1
* target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel2014-06-091-0/+2
* target-arm: Fix segfault on startup when KVM enabledChristoffer Dall2014-05-271-1/+1
* kvm: reset state from the CPU's reset methodPaolo Bonzini2014-05-131-0/+7
* target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell2014-04-171-1/+1
* target-arm: Implement CBAR for Cortex-A57Peter Maydell2014-04-171-2/+6
* target-arm: Implement RVBAR registerPeter Maydell2014-04-171-0/+9
* target-arm: Implement ARMv8 MVFR registersPeter Maydell2014-04-171-0/+1
* target-arm: Implement AArch64 views of fault status and data registersRob Herring2014-04-171-1/+1
* target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell2014-04-171-0/+7
* target-arm: Split out private-to-target functions into internals.hPeter Maydell2014-04-171-0/+1
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-1/+1
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-1/+3
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-0/+7
* target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton2014-02-261-0/+1
* target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell2014-02-261-4/+4
* target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell2014-02-261-2/+2
* target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell2014-02-261-0/+2
OpenPOWER on IntegriCloud