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* tcg: Add type for vCPU pointersLluís Vilanova2019-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Acked-by: Richard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2019-11-291-4/+4
| | | | | | | | Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2019-11-291-0/+1
| | | | | | | | | | Split the bits that require it to exec/log.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-id: 1452174932-28657-8-git-send-email-den@openvz.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* alpha: Clean up includesPeter Maydell2019-11-291-0/+1
| | | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-12-git-send-email-peter.maydell@linaro.org
* target-alpha: fix uninitialized variablePaolo Bonzini2015-11-061-1/+1
| | | | | | | | | | | I am not sure why the compiler does not catch it. There is no semantic change since gen_excp returns EXIT_NORETURN, but the old code is wrong. Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-0/+5
| | | | | | | | Some targets already had this within their logic, but make sure it's present for all targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-37/+4
| | | | | | | | | | It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
| | | | | | | | | | The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-0/+3
| | | | | | | | Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-9/+4
| | | | | | | | | | | | Reduce the boilerplate required for each target. At the same time, move the test for breakpoint after calling tcg_gen_insn_start. Note that arm and aarch64 do not use cpu_breakpoint_test, but still move the inline test down after tcg_gen_insn_start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-2/+2
| | | | | | | | This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+2
| | | | | | | | | | While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
| | | | | | | | With an eye toward making it mandatory. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-1/+1
| | | | | | | | | | | | | | | | | | This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20150902' into stagingPeter Maydell2015-09-031-1/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | cmpbge emulation improvements # gpg: Signature made Wed 02 Sep 2015 20:25:10 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-axp-20150902: target-alpha: Special case cmpbge with zero target-alpha: Rewrite helper_cmpbge using bit tests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-alpha: Special case cmpbge with zeroRichard Henderson2015-08-181-1/+6
| | | | | | | | | | | | Knowing the comparator is zero leads to a simpler operation. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-2/+2
| | | | | | | | | | | | Replacing it with tcg_gen_extrl_i64_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-alpha: Inline hw_retRichard Henderson2015-08-181-5/+10
| | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-alpha: Inline call_palRichard Henderson2015-08-181-9/+24
| | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target-alpha: Use separate TCGv temporaries for the shadow registersRichard Henderson2015-08-181-53/+100
|/ | | | | | | | | | | | This avoids having to manually swap them around when swapping to and from PALmode. We simply encode the shadow registers into the translation. The VMStateDescription version changes, because the meaning of "shadow" changes in the save file when in PALmode. It would be possible to fix this, but I don't think it's worth the effort. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* target-alpha: Raise IOV from CVTQLRichard Henderson2015-05-181-29/+5
| | | | | | | | | Even if an exception isn't taken, the status flags need updating and the result should be written to the destination. Move the body of cvtql out of line, since we now always need a call. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Raise EXC_M_INV properly for fp inputsRichard Henderson2015-05-181-0/+7
| | | | | | | | Ignore DNZ if software completion isn't used. Raise INV for denormals in system mode so the OS completion handler sees them. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Disallow literal operand to 1C.30 to 1C.37Richard Henderson2015-05-181-2/+17
| | | | | | | | Before 64f45e49 we used to have literal checks for 4 of these 8 opcodes. Confirmed that real hardware doesn't allow them. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Implement WH64ENRichard Henderson2015-05-181-0/+4
| | | | | | | Backward compatible cache insn introduced for EV7. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Fix integer overflow checking insnsRichard Henderson2015-05-181-7/+53
| | | | | | | | | We need to write the result to the destination register before raising any exception. Thus inline the code for each insn, and check for any exception after we're done. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Raise IOV from CVTTQRichard Henderson2015-05-181-13/+4
| | | | | | | Floating-point overflow is a different bit from integer overflow. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Set fpcr_exc_status even for disabled exceptionsRichard Henderson2015-05-181-15/+13
| | | | | | | | The qualifiers can suppress the raising of exceptions, but real hardware still records that the exceptions occurred. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Tidy FPCR representationRichard Henderson2015-05-181-37/+8
| | | | | | | Store the fpcr as the hardware represents it. Convert the softfpu representation of exceptions into the fpcr representation. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Forget installed round mode after MT_FPCRRichard Henderson2015-05-181-0/+5
| | | | | | | | | When we use QUAL_RM_D, we copy fpcr_dyn_round to float_status. When we install a new FPCR value, we update fpcr_dyn_round. Reset the status of the cache so that we re-copy for the next fp insn that requires dynamic rounding. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Rename floating-point subroutinesRichard Henderson2015-05-181-34/+34
| | | | | | ... to match the instructions, which have no leading "f". Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-7/+7
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+1
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
| | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-4/+4
| | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
| | | | | Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-0/+1
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-3/+2
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Fix RDUSPRichard Henderson2014-05-021-1/+1
| | | | | | Commit 06ef8604e92964cbf30084b7d31091aa7cbbb62f contained a typo. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Remove cpu_unique, cpu_sysval, cpu_uspRichard Henderson2014-04-171-19/+18
| | | | | | | | | | | | | Technically, these variables could have been referenced both via offsets from env and as TCG registers, which would be illegal. Of course, that could only be done from PALcode, and ours doesn't do that. But honestly, these are used infrequently enough that they don't really need to be TCG registers. We wind up with exactly the same code if we follow the letter of the law and issue explicit ld/st. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Tidy alpha_translate_initRichard Henderson2014-04-171-35/+43
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Don't issue goto_tb under singlestepRichard Henderson2014-04-171-1/+2
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Use non-local temps for zero/sinkRichard Henderson2014-04-171-2/+2
| | | | | | These values are no longer live across branches. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Use extract to get insn fieldsRichard Henderson2014-04-171-27/+22
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Convert mfpr/mtpr to source/sinkRichard Henderson2014-04-171-33/+19
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Convert gen_cpys et al to source/sinkRichard Henderson2014-04-171-76/+24
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Convert gen_fcvtlq/ql to source/sinkRichard Henderson2014-04-171-50/+28
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Convert gen_fcmov to source/sinkRichard Henderson2014-04-171-30/+14
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Convert gen_bcond to source/sinkRichard Henderson2014-04-171-18/+6
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
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