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* dataplane: replace hostmem with memory_region_findPaolo Bonzini2013-12-203-192/+71
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* dataplane: change vring API to use VirtQueueElementPaolo Bonzini2013-12-202-72/+69
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* vring: factor common code for error exitsPaolo Bonzini2013-12-202-13/+22
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* vring: create a common function to parse descriptorsPaolo Bonzini2013-12-201-62/+51
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* spapr: limit numa memory regions by ram sizePaul Mackerras2013-12-201-4/+16
| | | | | | | | | This makes sure that all NUMA memory blocks reside within RAM or have zero length. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr: make sure RMA is in first mode of first memory nodeAlexey Kardashevskiy2013-12-201-6/+11
| | | | | | | | | | | | | | | The SPAPR specification says that the RMA starts at the LPAR's logical address 0 and is the first logical memory block reported in the LPAR’s device tree. So SLOF only maps the first block and that block needs to span the full RMA. This makes sure that the RMA area is where SLOF expects it. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* device_tree: s/qemu_devtree/qemu_fdt globallyPeter Crosthwaite2013-12-2010-213/+214
| | | | | | | | | The qemu_devtree API is a wrapper around the fdt_ set of APIs. Rename accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [agraf: also convert hw/arm/virt.c] Signed-off-by: Alexander Graf <agraf@suse.de>
* roms: Flush icache when writing roms to guest memoryAlexander Graf2013-12-201-0/+7
| | | | | | | | | | | | | | | | | | We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr: tie spapr-nvram to -pflashPaolo Bonzini2013-12-201-11/+3
| | | | | | | | | | | | | | | | spapr-nvram's drive property is currently connected to a non-existent "-machine nvram=<drivename>" option. Instead, tie it to -pflash like other non-volatile RAM devices. This provides the following possibilities for adding a backend for the sPAPR non-volatile RAM: * -pflash filename * -drive if=pflash,file=filename,format=raw,... * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Use default pci bus name for grackle and heathrowAlexander Graf2013-12-202-3/+3
| | | | | | | | | | | | | There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr-rtas: add ibm, (get|set)-system-parameterAlexey Kardashevskiy2013-12-201-0/+47
| | | | | | | | | | | | | | This adds very basic handlers for ibm,get-system-parameter and ibm,set-system-parameter RTAS calls. The only parameter handled at the moment is "platform-processor-diagnostics-run-mode" which is always disabled and does not support changing. This is expected to make "ppc64_cpu --run-mode=1" happy. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: s/papameter/parameter/g] Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr-rtas: replace return code constants with macrosAlexey Kardashevskiy2013-12-206-67/+67
| | | | | Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* hw/arm: add cubieboard supportliguang2013-12-172-1/+70
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-6-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: add allwinner a10 SoC supportliguang2013-12-172-0/+104
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc: add allwinner A10 interrupt controllerliguang2013-12-172-0/+201
| | | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/timer: add allwinner a10 timerliguang2013-12-172-0/+256
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-3-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/digic: add NOR ROM supportAntony Pavlov2013-12-171-0/+78
| | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-6-git-send-email-antonynpavlov@gmail.com [PMM: don't try to load ROM blob if qtest_enabled()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/digic: add UART supportAntony Pavlov2013-12-173-0/+212
| | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-5-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/digic: add timer supportAntony Pavlov2013-12-173-0/+192
| | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-4-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/digic: prepare DIGIC-based boards supportAntony Pavlov2013-12-172-0/+85
| | | | | | | | | Also this patch adds initial support for Canon PowerShot A1100 IS compact camera. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-3-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: add very initial support for Canon DIGIC SoCAntony Pavlov2013-12-172-0/+72
| | | | | | | | | | | | | | | | | | | DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/boot: Add boot support for AArch64 processorMian M. Hamayun2013-12-171-5/+38
| | | | | | | | | | | | | | | | | | This commit adds support for booting a single AArch64 CPU by setting appropriate registers. The bootloader includes placeholders for Board-ID that are used to implement uniform indexing across different bootloaders. Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-7-git-send-email-peter.maydell@linaro.org [PMM: * updated to use ARMInsnFixup style bootloader fragments * dropped virt.c additions * use runtime checks for "is this an AArch64 core" rather than ifdefs * drop some unnecessary setting of registers in reset hook ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
* hw/arm/boot: Allow easier swapping in of different loader codePeter Maydell2013-12-171-45/+107
| | | | | | | | | | | | | | | | For AArch64 we will obviously require a different set of primary and secondary boot loader code fragments. However currently we hardcode the offsets into the loader code where we must write the entrypoint and other data into arm_load_kernel(). This makes it hard to substitute a different loader fragment, so switch to a more flexible scheme where instead of a raw array of instructions we use an array of (instruction, fixup-type) pairs that indicate which words need special action or data written into them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-6-git-send-email-peter.maydell@linaro.org Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* arm/highbank.c: Fix MPCore periphbase namePeter Crosthwaite2013-12-171-7/+8
| | | | | | | | | | | GIC_BASE_ADDR is not the base address of the GIC. Its clear from the code that this is the base address of the MPCore. Rename to MPCORE_PERIPHBASE accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 90798bd3507205c16238b8b19a1a58c5437cf7ca.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/xilinx_zynq: Implement CBAR initialisationPeter Crosthwaite2013-12-171-1/+8
| | | | | | | | | | | | Fix the CBAR initialisation by using the newly defined static property. Zynq will now correctly init the CBAR to the SCU base address. Needed to boot Linux on the xilinx_zynq machine model. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8db7d57ebe5418fed397fcc86ea719f98446c178.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()Peter Crosthwaite2013-12-171-3/+9
| | | | | | | | | | To allow the machine model to set device properties before CPU realization. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: e57658b4506b26ab6b6fadbe6d7827f669f51895.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/highbank: Fix CBAR initialisationPeter Crosthwaite2013-12-171-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the CBAR initialisation by using the newly defined static property. CBAR is now set before realization, so the intended value is now actually used. So I have kind of tested this. I booted an ARM kernel on Highbank with the stock Highbank DTB. It doesn't boot (and I will be doing something wrong), but before this patch I got this: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198() CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.13.0-rc1-next-20131126-dirty #2 [<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14) [<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90) [<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84) [<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24) [<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198) [<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c) [<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c) [<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c) [<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c) [<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398) [<c03899ec>] (start_kernel) from [<00008074>] (0x8074) ---[ end trace 3406ff24bd97382f ]--- Which disappears with this patch. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: fedec366aaa512d75093635f523d1dbcb3358361.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/highbank: Use object_new() rather than cpu_arm_init()Peter Crosthwaite2013-12-171-3/+9
| | | | | | | | | | To allow the machine model to set device properties before CPU realization. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8c671e500390c8be0cc363e887e32867d1d1b0d2.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Fix NOR flash device ID readingRoy Franz2013-12-172-23/+88
| | | | | | | | | | | | | | | | | | | | | | Fix NOR flash manufacturer and device ID reading. This now properly takes into account device widths and device max widths as required. The reading of these IDs uses the same max_width dependent addressing as CFI queries. The old code remains for chips that don't specify a device width, as the new code relies on a device width being set in order to properly operate. The existing code seems very broken. Only ident0 and ident1 are used in the new code, as other fields relate to the lock state of blocks in flash. The VExpress flash configuration has been updated to match the new code, as the existing definition was 'wrong' in order to return the expected results with the broken device ID code. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-8-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Fix CFI query responses for NOR flashRoy Franz2013-12-171-11/+94
| | | | | | | | | | | | | | | | | | | | | This change fixes the CFI query responses to handle NOR device widths that are different from the bank width. Support is also added for multi-width devices in a x8 configuration. This is typically x8/x16 devices, but the CFI specification mentions x8/x32 devices so those should be supported as well if they exist. The query response data is now replicated per-device in the bank, and is adjusted for x16 or x32 parts configured in x8 mode. The existing code is left in place for boards that have not been updated to specify an explicit device_width. The VExpress board has been updated in an earlier patch in this series so this is the only board currently affected. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-7-git-send-email-roy.franz@linaro.org [PMM: fixed a few formatting nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Add max device width parameter for NOR devicesRoy Franz2013-12-171-0/+25
| | | | | | | | | | | | | | | | For handling CFI and device ID reads, we need to not only know the width that a NOR flash device is configured for, but also its maximum width. The maximum width addressing mode is used for multi-width parts no matter which width they are configured for. The most common case is x16 parts that also support x8 mode. When configured for x8 operation these devices respond to CFI and device ID requests differently than native x8 NOR parts. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-6-git-send-email-roy.franz@linaro.org [PMM: Added comment explaining the semantics of width vs device-width vs max-device-width] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Set proper device-width for vexpress flashRoy Franz2013-12-171-10/+34
| | | | | | | | | | | | Create vexpress specific pflash registration function which properly configures the device-width of 16 bits (2 bytes) for the NOR flash on the vexpress platform. This change is required for buffered flash writes to work properly. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-5-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* return status for each NOR flash deviceRoy Franz2013-12-171-2/+13
| | | | | | | | | | | Now that we know how wide each flash device that makes up the bank is, return status for each device in the bank. Leave existing code that treats 32 bit wide banks as composed of two 16 bit devices as otherwise we may break configurations that do not set the device_width propery. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-4-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Add device-width property to pflash_cfi01Roy Franz2013-12-171-0/+11
| | | | | | | | | | | | | | | | | | | The width of the devices that make up the flash interface is required to mask certain commands, in particular the write length for buffered writes. This length will be presented to each device on the interface by the program writing the flash, and the flash emulation code needs to be able to determine the length of the write as recieved by each flash device. The device-width defaults to the bank width which should maintain existing behavior for platforms that don't need this change. This change is required to support buffered writes on the vexpress platform that has a 32 bit flash interface with 2 16 bit devices on it. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-3-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* rename pflash_t member width to bank_widthRoy Franz2013-12-171-8/+9
| | | | | | | | | | Rename the 'width' member of the pflash_t structure in preparation for adding a bank_width member. Signed-off-by: Roy Franz <roy.franz@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386279359-32286-2-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* spice: stop server for qxl hard resetGerd Hoffmann2013-12-161-0/+10
| | | | | | | | | Hard reset can happen at any time. We should be able to put qxl into a known-good state no matter what. Stop spice server thread for reset so it can't be confused by fetching stale commands lingering around in the rings while we reset is ongoing. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* Merge remote-tracking branch 'bonzini/virtio' into stagingAnthony Liguori2013-12-1317-320/+387
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # By Andreas Färber (18) and Paolo Bonzini (12) # Via Paolo Bonzini * bonzini/virtio: (30 commits) virtio: Convert exit to unrealize virtio: Complete converting VirtioDevice to QOM realize virtio-scsi: Convert to QOM realize virtio-rng: Convert to QOM realize virtio-balloon: Convert to QOM realize virtio-net: Convert to QOM realize virtio-serial: Convert to QOM realize virtio-blk: Convert to QOM realize virtio-9p: Convert to QOM realize virtio: Start converting VirtioDevice to QOM realize virtio-scsi: QOM realize preparations virtio-rng: QOM realize preparations virtio-balloon: QOM realize preparations virtio-net: QOM realize preparations virtio-serial: QOM realize preparations virtio-blk: QOM realize preparations virtio-9p: QOM realize preparations virtio-blk-dataplane: Improve error reporting virtio-pci: add device_unplugged callback virtio-rng: switch exit callback to VirtioDeviceClass ...
| * virtio: Convert exit to unrealizeAndreas Färber2013-12-098-38/+49
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio: Complete converting VirtioDevice to QOM realizeAndreas Färber2013-12-092-8/+1
| | | | | | | | | | | | | | Drop VirtioDeviceClass::init. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-scsi: Convert to QOM realizeAndreas Färber2013-12-092-33/+32
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-rng: Convert to QOM realizeAndreas Färber2013-12-091-13/+11
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-balloon: Convert to QOM realizeAndreas Färber2013-12-091-5/+6
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-net: Convert to QOM realizeAndreas Färber2013-12-091-4/+4
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-serial: Convert to QOM realizeAndreas Färber2013-12-091-8/+8
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-blk: Convert to QOM realizeAndreas Färber2013-12-091-12/+12
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-9p: Convert to QOM realizeAndreas Färber2013-12-091-21/+20
| | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio: Start converting VirtioDevice to QOM realizeAndreas Färber2013-12-091-15/+27
| | | | | | | | | | | | | | | | | | | | Temporarily allow either VirtioDeviceClass::init or VirtioDeviceClass::realize. Introduce VirtioDeviceClass::unrealize for symmetry. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-scsi: QOM realize preparationsAndreas Färber2013-12-091-7/+7
| | | | | | | | | | | | | | | | | | | | Rename qdev -> dev since that's what realize's argument is called by convention. No need to keep more "qdev" around than necessary. Avoid duplicate VIRTIO_DEVICE() cast. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-rng: QOM realize preparationsAndreas Färber2013-12-091-5/+5
| | | | | | | | | | | | | | | | Rename qdev -> dev because that's what realize's argument is called by convention. No need to keep more "qdev" around than necessary. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * virtio-balloon: QOM realize preparationsAndreas Färber2013-12-091-6/+6
| | | | | | | | | | | | | | | | | | | | Rename qdev -> dev since that's what realize's argument is called by convention. No need to keep more "qdev" around than necessary. Avoid duplicate VIRTIO_DEVICE() cast. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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