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* hw: include hw header files with full pathsPaolo Bonzini2013-03-011-5/+5
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-12/+12
* sh7750: Remove redundant 'struct' from MemoryRegionOpsStefan Weil2012-03-071-1/+1
* sh_serial: convert to memory APIBenoît Canet2011-11-241-13/+15
* sh_intc: convert interrupt controller to memory APIBenoît Canet2011-11-241-1/+1
* sh_timer: convert to memory APIBenoît Canet2011-11-241-2/+2
* sh7750: convert cache and tlb to memory APIBenoît Canet2011-11-241-21/+22
* sh7750: convert memory controller/ioport to memory APIBenoît Canet2011-11-241-27/+45
* Use glib memory allocation and free functionsAnthony Liguori2011-08-201-1/+1
* Remove exec-all.h include directivesBlue Swirl2011-06-261-1/+0
* sh4: implement missing mmaped TLB read functionsAurelien Jarno2011-01-261-6/+9
* sh4: implement missing mmaped TLB write functionsAurelien Jarno2011-01-261-3/+2
* target-sh4: implement writes to mmaped ITLBAurelien Jarno2011-01-091-0/+2
* Add endianness as io mem parameterAlexander Graf2010-12-111-2/+4
* Replace assert(0) with abort() or cpu_abort()Blue Swirl2010-03-181-15/+15
* sh7750: handle MMUCR TI bitAurelien Jarno2010-02-091-2/+5
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-011-12/+12
* Get rid of _t suffixmalc2009-10-011-12/+12
* static and inline should came before the type of the functionsJuan Quintela2009-09-251-1/+1
* Make CPURead/WriteFunc structure 'const'Blue Swirl2009-08-251-4/+4
* Remove io_index argument from cpu_register_io_memory()Avi Kivity2009-06-161-4/+2
* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
* SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 an...aurel322009-02-071-10/+42
* Remove unnecessary trailing newlinesblueswir12008-12-131-1/+0
* SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog2008-12-071-0/+6
* SH: improve the way sh7750 registers io memory (Takashi YOSHII).balrog2008-12-071-8/+6
* SH: r2d pci support (Takashi YOSHII).balrog2008-12-071-0/+17
* sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).balrog2008-12-071-1/+39
* Change MMIO callbacks to use offsets, not absolute addresses.pbrook2008-12-011-1/+2
* SH4: Switch serial emulation to qemu_irqaurel322008-11-211-8/+8
* SH4: Use qemu_irq in timer emulation.aurel322008-11-211-6/+6
* sh4: CPU versioning.aurel322008-09-021-26/+17
* [sh4] MMU bug fixaurel322008-08-221-0/+4
* [sh4] memory mapped TLB entriesaurel322008-08-221-0/+110
* Fix a bunch of type mismatch-related warnings (Jan Kiszka).balrog2008-07-161-2/+2
* SH4 serial controler improvementsaurel322008-05-091-2/+12
* SH4 MMU improvementsaurel322008-05-091-0/+3
* Adds interrupt support to the sh specific timer code (Magnus Damm).balrog2007-12-121-3/+9
* SH4: system emulator interrupt update, by Magnus Damm.ths2007-12-021-0/+2
* Break up vl.h.pbrook2007-11-171-1/+3
* removed invalid use of _INTC_ARRAYbellard2007-11-111-2/+2
* sh775x interrupt controller by Magnus Damm.balrog2007-10-041-45/+178
* Add FRQCR read support, by Magnus Damm.ths2007-09-291-0/+2
* Add INTC controller prototype, by Magnus Damm.ths2007-09-291-0/+51
* Stand-alone SCI/SCIF emulation code, by Magnus Damm.ths2007-09-291-341/+4
* Stand-alone TMU emulation code, by Magnus Damm.ths2007-09-291-96/+6
* find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths2007-09-161-2/+2
* Rearrange char event handlers to fix CHR_EVENT_RESET.pbrook2007-01-271-6/+4
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