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* Merge remote-tracking branch 'afaerber-or/prep-up' into stagingAnthony Liguori2013-01-302-1/+682
|\ | | | | | | | | | | | | | | | | # By Andreas Färber # Via Andreas Färber * afaerber-or/prep-up: prep: Move PReP machine to hw/ppc/ prep_pci: Convert to QOM realizefn prep_pci: Create PCIBus and PCIDevice in-place
| * prep: Move PReP machine to hw/ppc/Andreas Färber2013-01-302-1/+682
| | | | | | | | Signed-off-by: Andreas Färber <andreas.faerber@web.de>
* | fw_cfg: Remove FW_CFG_MAX_CPUS from fw_cfg_init()Eduardo Habkost2013-01-272-0/+2
|/ | | | | | | | PC will not use max_cpus for that field, so move it outside the common code so it can use a different value on PC. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* PPC: e500: Select MPIC v4.2 on ppce500 platformScott Wood2013-01-254-3/+9
| | | | | | | | | | | The compatible string is changed to fsl,mpic on all e500 platforms, to advertise the existence of BRR1. This matches what the device tree will have on real hardware. With MPIC v4.2 max_cpu can be increased from 15 to 32. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: fix mpic_iack addressScott Wood2013-01-251-1/+1
| | | | | | | | MPIC+0xa0 is IACK for the current CPU. MPIC+0x200a0 is IACK for CPU 0. This fix allows EPR to work with an SMP target. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* cuda: Move ADB bus into CUDA stateAndreas Färber2013-01-253-4/+12
| | | | | | | | Replace the global adb_bus with a CUDA-internal one, accessed using regular qdev child bus accessor. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* adb: QOM'ify ADB devicesAndreas Färber2013-01-252-4/+8
| | | | | | | | | | | | | They were not qdev'ified before. Derive ADBDevice from DeviceState and convert reset callbacks to DeviceClass::reset, ADBDevice::opaque pointer to ADBDevice subtypes for mouse and keyboard and adb_{kbd,mouse}_init() to regular qdev functions. Fixing Coding Style issues and splitting keyboard and mouse off into their own files is left for a later point in time. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* cuda: QOM'ify CUDAAndreas Färber2013-01-253-23/+84
| | | | | | | | It was not qdev'ified before. Turn it into a SysBusDevice and embed it in MacIO. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* ide/macio: QOM'ify MacIO IDEAndreas Färber2013-01-253-30/+59
| | | | | | | | It was not qdev'ified before. Turn it into a SysBusDevice. Embed them into the MacIO devices. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* mac_nvram: QOM'ify MacIO NVRAMAndreas Färber2013-01-253-14/+25
| | | | | | | | | | | | | It was not qdev'ified before. Turn it into a SysBusDevice and initialize it via static properties. Prepare Old World specific MacIO state and embed the NVRAM state there. Drop macio_nvram_setup_bar() in favor of sysbus_mmio_map() or direct use of Memory API. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* mac_nvram: Clean up public APIAndreas Färber2013-01-251-2/+2
| | | | | | | | | | The state data field is accessed in uint8_t quantities, so switch from uint32_t argument and return value to uint8_t. Fix debug format specifiers while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* macio: Split MacIO in twoAndreas Färber2013-01-253-6/+12
| | | | | | | | Let the machines create two different types. This prepares to move knowledge about sub-devices from the machines into the devices. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Move Mac machines to hw/ppc/Andreas Färber2013-01-254-4/+891
| | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> [agraf: squash in MAINTAINERS fix] Signed-off-by: Alexander Graf <agraf@suse.de>
* sysbus: Drop sysbus_from_qdev() cast macroAndreas Färber2013-01-211-2/+2
| | | | | | | | | | | Replace by SYS_BUS_DEVICE() QOM cast macro using a scripted conversion. Avoids the old macro creeping into new code. Resolve a Coding Style warning in openpic code. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Anthony Liguori <anthony@codemonkey.ws> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* PPC: e500: Change in-memory order of load blobsAlexander Graf2013-01-181-1/+6
| | | | | | | | | | | | | | | | | Today, we load <kernel> <initrd> <dtb> into memory in that order. However, Linux has a bug where it can only handle the dtb if it's within the first 64MB of where <kernel> starts. So instead, let's change the order to <kernel> <dtb> <initrd> making Linux happy. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: E500: Calculate loading blob offsets properlyAlexander Graf2013-01-181-4/+8
| | | | | | | | | | | | | | | We have 3 blobs we need to load when booting the system: - kernel - initrd - dtb We place them in physical memory in that order. At least we should. This patch fixes the location calculation up to take any module into account, fixing the dtb offset along the way. Reported-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* Make default boot order machine specificAvik Sil2013-01-152-0/+2
| | | | | | | | | | | | | | This patch makes default boot order machine specific instead of set globally. The default boot order can be set per machine in QEMUMachine boot_order. This also allows a machine to receive a NULL boot order when -boot isn't used and take an appropriate action accordingly. This helps machine boots from the devices as set in guest's non-volatile memory location in case no boot order is provided by the user. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avik Sil <aviksil@linux.vnet.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* cpu: Move cpu_index field to CPUStateAndreas Färber2013-01-151-6/+11
| | | | | | | | | | | | | Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
* PPC: Bring EPR support closer to realityAlexander Graf2013-01-071-2/+2
| | | | | | | | | | | | | | We already used to support the external proxy facility of FSL MPICs, but only implemented it halfway correctly. This patch adds support for * dynamic enablement of the EPR facility * interrupt acknowledgement only when the interrupt is delivered This way the implementation now is closer to real hardware. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: KVM: set has-idle in guest device treeStuart Yoder2013-01-071-0/+4
| | | | | | | | | | | On e500mc, the platform doesn't provide a way for the CPU to go idle. To still not uselessly burn CPU time, expose an idle hypercall to the guest if kvm supports it. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> [agraf: adjust for current code base, add patch description, fix non-kvm case] Signed-off-by: Alexander Graf <agraf@suse.de>
* Merge branch 'master' of git://git.qemu.org/qemu into qom-cpuAndreas Färber2012-12-234-11/+12
|\ | | | | | | | | | | Adapt header include paths. Signed-off-by: Andreas Färber <afaerber@suse.de>
| * softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-193-6/+6
| | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * misc: move include files to include/qemu/Paolo Bonzini2012-12-191-2/+2
| | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
| | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * net: reorganize headersPaolo Bonzini2012-12-191-1/+1
| | | | | | | | | | | | | | | | | | Move public headers to include/net, and leave private headers in net/. Put the virtio headers in include/net/tap.h, removing the multiple copies that existed. Leave include/net/tap.h as the interface for NICs, and net/tap_int.h as the interface for OS-specific parts of the tap backend. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * janitor: do not rely on indirect inclusions of or from qemu-char.hPaolo Bonzini2012-12-191-0/+1
| | | | | | | | | | | | | | | | | | Various header files rely on qemu-char.h including qemu-config.h or main-loop.h, but they really do not need qemu-char.h at all (particularly interesting is the case of the block layer!). Clean this up, and also add missing inclusions of qemu-char.h itself. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * Merge commit '1dd3a74d2ee2d873cde0b390b536e45420b3fe05' into HEADPaolo Bonzini2012-12-172-2/+2
| |\ | | | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| | * pci: update all users to look in pci/Michael S. Tsirkin2012-12-171-1/+1
| | | | | | | | | | | | | | | | | | update all users so we can remove the makefile hack. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| | * pci: move pci core code to hw/pciMichael S. Tsirkin2012-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | Move files and modify makefiles to pick them at the new location. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | | ppc_booke: Pass PowerPCCPU to ppc_booke_timers_init()Andreas Färber2012-12-191-1/+1
|/ / | | | | | | | | | | Cleans up after passing PowerPCCPU to timer callbacks. Signed-off-by: Andreas Färber <afaerber@suse.de>
* | PPC: e500: pci: Export slot2irq calculationAlexander Graf2012-12-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | We need the calculation method to get from a PCI slot ID to its respective interrupt line twice. Once in the internal map function and once when assembling the device tree. So let's extract the calculation to a separate function that can be called by both users. Signed-off-by: Alexander Graf <agraf@suse.de>
* | PPC: E500plat: Make a lot of PCI slots availableAlexander Graf2012-12-141-2/+3
| | | | | | | | | | | | | | | | | | | | The ppce500 machine doesn't have to stick to hardware limitations, as it's defined as being fully device tree based. Thus we can change the initial PCI slot ID to 0x1 which gives us a whopping 31 PCI devices we can support with this machine now! Signed-off-by: Alexander Graf <agraf@suse.de>
* | PPC: E500: Move PCI slot information into paramsAlexander Graf2012-12-144-1/+9
| | | | | | | | | | | | | | | | We have a params struct that allows us to expose differences between e500 machine models. Include PCI slot information there, so we can have different machines with different PCI slot topology. Signed-off-by: Alexander Graf <agraf@suse.de>
* | PPC: E500: Generate dt pci irq map dynamicallyAlexander Graf2012-12-141-20/+31
| | | | | | | | | | | | | | | | Today we're hardcoding the PCI interrupt map in the e500 machine file. Instead, let's write it dynamically so that different machine types can have different slot properties. Signed-off-by: Alexander Graf <agraf@suse.de>
* | PPC: e500: Add MSI supportAlexander Graf2012-12-141-0/+23
| | | | | | | | | | | | | | Now that our interrupt controller supports MSIs, let's expose that feature to the guest through the device tree! Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: convert to qdevAlexander Graf2012-12-141-5/+19
| | | | | | | | | | | | | | | | | | | | | | This patch converts the OpenPIC device to qdev. Along the way it renames the "openpic" target to "raven" and the "mpic" target to "fsl_mpic_20", to better reflect the actual models they implement. This way we have a generic OpenPIC device now that can handle different flavors of the OpenPIC specification. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: remove irq_outAlexander Graf2012-12-141-1/+1
| | | | | | | | | | | | | | | | The current openpic emulation contains half-ready code for bypass mode. Remove it, so that when someone wants to finish it they can start from a clean state. Signed-off-by: Alexander Graf <agraf@suse.de>
* | mpic: Unify numbering schemeAlexander Graf2012-12-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | MPIC interrupt numbers in Linux (device tree) and in QEMU are different, because QEMU takes the sparseness of the IRQ number space into account. Remove that cleverness and instead assume a flat number space. This makes the code easier to understand, because we are actually aligned with Linux on the view of our worlds. Signed-off-by: Alexander Graf <agraf@suse.de>
* | Adding BAR0 for e500 PCI controllerBharat Bhushan2012-12-142-9/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with an address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> [agraf: fix double variable assignment w/o read] Signed-off-by: Alexander Graf <agraf@suse.de>
* | e500: Adding CCSR memory regionBharat Bhushan2012-12-141-23/+40
| | | | | | | | | | | | | | | | | | | | | | | | All devices are also placed under CCSR memory region. The CCSR memory region is exported to pci device. The MSI interrupt generation is the main reason to export the CCSR region to PCI device. This put the requirement to move mpic under CCSR region, but logically all devices should be under CCSR. So this patch places all emulated devices under ccsr region. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | pseries: Implement PAPR NVRAMDavid Gibson2012-12-141-1/+1
|/ | | | | | | | | | | | | | The PAPR specification requires a certain amount of NVRAM, accessed via RTAS, which we don't currently implement in qemu. This patch addresses this deficiency, implementing the NVRAM as a VIO device, with some glue to instantiate it automatically based on a machine option. The machine option specifies a drive id, which is used to back the NVRAM, making it persistent. If nothing is specified, the driver instead simply allocates space for the NVRAM, which will not be persistent Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: Map PIO space into core memory regionAlexander Graf2012-10-291-2/+1
| | | | | | | | On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is accessible via MMIO. Do this mapping explicitly by mapping the PIO space of our PCI bus into a memory region that lives in memory space. Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Implement qemu initiated shutdowns using EPOW eventsDavid Gibson2012-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | At present, using 'system_powerdown' from the monitor or otherwise instructing qemu to (cleanly) shut down a pseries guest will not work, because we did not have a method of signalling the shutdown request to the guest. PAPR does include a usable mechanism for this, though it is rather more involved than the equivalent on x86. This involves sending an EPOW (Environmental and POwer Warning) event through the PAPR event and error logging mechanism, which also has a number of other functions. This patch implements just enough of the event/error logging functionality to be able to send a shutdown event to the guest. At least with modern guest kernels and a userspace that is up and running, this means that system_powerdown from the qemu monitor should now work correctly on pseries guests. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* e500: Fix serial initializationBharat Bhushan2012-10-291-1/+1
| | | | | | | | it was wrongly using serial_hds[0] instead of serial_hds[1] Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-7/+7
| | | | | | | | | | | | | | | target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* serial: split serial.cGerd Hoffmann2012-10-221-1/+1
| | | | | | | | | | Split serial.c into serial.c, serial.h and serial-isa.c. While being at creating a serial.h header file move the serial prototypes from pc.h to the new serial.h. The latter leads to s/pc.h/serial.h/ in tons of boards which just want the serial bits from pc.h Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* create struct for machine initialization argumentsEduardo Habkost2012-10-202-12/+14
| | | | | | | | | | | | | | | | | This should help us to: - More easily add or remove machine initialization arguments without having to change every single machine init function; - More easily make mechanical changes involving the machine init functions in the future; - Let machine initialization forward the init arguments to other functions more easily. This change was half-mechanical process: first the struct was added with the local ram_size, boot_device, kernel_*, initrd_*, and cpu_model local variable initialization to all functions. Then the compiler helped me locate the local variables that are unused, so they could be removed. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* PPC: e500: Only expose even TLB sizes in initial TLBAlexander Graf2012-10-051-0/+4
| | | | | | | | | | | | | | | | When booting our e500 machine, we automatically generate a big TLB entry in TLB1 that covers all of the code we need to run in there until the guest can handle its TLB on its own. However, e500v2 can only handle MAS1.0 sizes. However, we keep our TLB information in MAS2.0 layout, which means we have twice as many TLB sizes to choose from. That also means we can run into a situation where we try to add a TLB size that could not fit into the MAS1.0 size bits. Fix it by making sure we always have the lower bit set to 0. That way we are always guaranteed to have MAS1.0 compatible TLB size information. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: calculate initrd_base like dt_baseScott Wood2012-10-051-1/+2
| | | | | | | | While investigating dtb pad issues, I noticed that initrd_base wasn't taking loadaddr into account the way dt_base was. This seems wrong. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: increase DTC_LOAD_PADScott Wood2012-10-051-1/+1
| | | | | | | | | | | | | | An allowance of 5 MiB for BSS is not enough for Linux kernels with certain debug options enabled (not sure exactly which one caused it, but I'd guess lockdep). The kernel I ran into this with had a BSS of around 6.4 MB. Unfortunately, uImage does not give us enough information to determine the actual BSS size. Increase the allowance to 18 MiB to give us plenty of room. Eventually this should be more intelligent, possibly packing initrd+dtb at the end of guest RAM. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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