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* hw/pci: Introduce pci_requester_id()Pavel Fedin2015-10-191-1/+1
| | | | | | | | | | | | | | | | For GICv3 ITS implementation we are going to use requester IDs in KVM IRQ routing code. This patch introduces reusable convenient way to obtain this ID from the device pointer. The new function is now used in some places, where the same calculation was used. MemTxAttrs.stream_id also renamed to requester_id in order to better reflect semantics of the field. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <5814bcb03a297f198e796b13ed9c35059c52f89b.1444916432.git.p.fedin@samsung.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* xen: don't allow guest to control MSI mask registerJan Beulich2015-06-021-4/+0
| | | | | | | | | | | It's being used by the hypervisor. For now simply mimic a device not capable of masking, and fully emulate any accesses a guest may issue nevertheless as simple reads/writes without side effects. This is XSA-129. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
* Add stream ID to MSI writePavel Fedin2015-05-311-1/+9
| | | | | | | | | | | | | | | | | GICv3 ITS distinguishes between devices by using hardwired device IDs passed on the bus. This patch implements passing these IDs in qemu. SMMU is also known to use stream IDs, therefore this addition can also be useful for implementing platforms with SMMU. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Changes from v1: - Added bus number to the stream ID - Added stream ID not only to MSI-X, but also to plain MSI. Some common code was made into msi_send_message() function. Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* Convert (ffs(val) - 1) to ctz32(val)Stefan Hajnoczi2015-04-281-6/+6
| | | | | | | | | | | | | | | | | | | This commit was generated mechanically by coccinelle from the following semantic patch: @@ expression val; @@ - (ffs(val) - 1) + ctz32(val) The call sites have been audited to ensure the ffs(0) - 1 == -1 case never occurs (due to input validation, asserts, etc). Therefore we don't need to worry about the fact that ctz32(0) == 32. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-5-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* Switch non-CPU callers from ld/st*_phys to address_space_ld/st*Peter Maydell2015-04-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch all the uses of ld/st*_phys to address_space_ld/st*, except for those cases where the address space is the CPU's (ie cs->as). This was done with the following script which generates a Coccinelle patch. A few over-80-columns lines in the result were rewrapped by hand where Coccinelle failed to do the wrapping automatically, as well as one location where it didn't put a line-continuation '\' when wrapping lines on a change made to a match inside a macro definition. ===begin=== #!/bin/sh -e # Usage: # ./ldst-phys.spatch.sh > ldst-phys.spatch # spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch # patch -p1 < out.patch for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do cat <<EOF @ cpu_matches_ld_${FN} @ expression E1,E2; identifier as; @@ ld${FN}_phys(E1->as,E2) @ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @ expression E1,E2; @@ -ld${FN}_phys(E1,E2) +address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL) EOF done for FN in b w_le w_be l_le l_be q_le q_be w l q; do cat <<EOF @ cpu_matches_st_${FN} @ expression E1,E2,E3; identifier as; @@ st${FN}_phys(E1->as,E2,E3) @ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @ expression E1,E2,E3; @@ -st${FN}_phys(E1,E2,E3) +address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL) EOF done ===endit=== Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
* pci: Use bus master address space for delivering MSI/MSI-X messagesJan Kiszka2014-08-141-1/+1
| | | | | | | | | | | | | The spec says (and real HW confirms this) that, if the bus master bit is 0, the device will not generate any PCI accesses. MSI and MSI-X messages fall among these, so we should use the corresponding address space to deliver them. This will prevent delivery if bus master support is disabled. Cc: qemu-stable@nongnu.org Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias2014-02-111-1/+1
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* misc: move include files to include/qemu/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pci: fix path for local includesMichael S. Tsirkin2012-12-171-1/+1
| | | | | | | | | Include dependencies from pci core using the correct path. This is required now that it's in the separate directory. Need to check whether they can be minimized, for now, keep the code as is. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* pci: move pci core code to hw/pciMichael S. Tsirkin2012-12-171-0/+395
Move files and modify makefiles to pick them at the new location. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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