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* hw: include hw header files with full pathsPaolo Bonzini2013-03-011-7/+7
| | | | | | | | | | | | | | | | | Done with this script: cd hw for i in `find . -name '*.h' | sed 's/^..//'`; do echo '\,^#.*include.*["<]'$i'[">], s,'$i',hw/&,' done | sed -i -f - `find . -type f` This is so that paths remain valid as files are moved. Instead, files in hw/dataplane are referenced with the relative path. We know they are not going to move to include/, and they are the only include files that are in subdirectories _and_ move. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* openpic: add basic support for MPIC v4.2Scott Wood2013-01-251-112/+226
| | | | | | | | | | | | | | | | | | | | | | Besides the new value in the version register, this provides: - ILR support, which includes: - IDR becoming a pure CPU bitmap, allowing 32 CPUs - machine check output support (though other parts of QEMU need to be fixed for it to do something other than immediately reboot the guest) - dummy error interrupt support (EISR0/EIMR0 read as zero) - actually all FSL MPICs get all summary registers returning zero for now, which includes EISR0/EIMR0 Various refactoring is done to support these changes and to ease new functionality (e.g. a more flexible way of declaring regions). Just as the code was already not a full implementation of MPIC v2.0, this is not a full implementation of MPIC v4.2 -- e.g. it still has only one bank of MSIs. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* openpic: fix timer address decodingScott Wood2013-01-251-3/+7
| | | | | | | | | | The timer memory range begins at 0x10f0, so that address 0x1120 shows up as 0x30, 0x1130 shows up as 0x40, etc. However, the address decoding (other than TFRR) is not adjusted for this, causing the wrong registers to be accessed. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* openpic: fix remaining issues from idr-to-destmask conversionScott Wood2013-01-251-6/+7
| | | | | | | | | | | | | | | openpic_update_irq() was checking idr rather than destmask, treating it as if it were a simple bitmap of cpus. Changed to use destmask. IPI delivery was removing bits directly from .idr, without calling write_IRQreg_idr so that the change could be conveyed to destmask. Changed to use destmask directly. Save/restore destmask when serializing, as due to the IPI change it cannot be reproduced from idr. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Move Mac machines to hw/ppc/Andreas Färber2013-01-251-1/+1
| | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> [agraf: squash in MAINTAINERS fix] Signed-off-by: Alexander Graf <agraf@suse.de>
* sysbus: Drop sysbus_from_qdev() cast macroAndreas Färber2013-01-211-1/+1
| | | | | | | | | | | Replace by SYS_BUS_DEVICE() QOM cast macro using a scripted conversion. Avoids the old macro creeping into new code. Resolve a Coding Style warning in openpic code. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Anthony Liguori <anthony@codemonkey.ws> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* openpic: export e500 epr enable into a ppc.c functionAlexander Graf2013-01-181-6/+5
| | | | | | | | Enabling and disabling the EPR capability (mpic_proxy) is a system wide operation. As such, it belongs into the ppc.c file, since that's where PPC specific machine wide logic happens. Signed-off-by: Alexander Graf <agraf@suse.de>
* openpic: set mixed mode as supportedAlexander Graf2013-01-181-0/+1
| | | | | | | | The Raven MPIC implementation supports the "Mixed" mode to work with an i8259. While we don't implement mixed mode, we should mark it as a supported mode in the mode bitmap. Signed-off-by: Alexander Graf <agraf@suse.de>
* openpic: unify gcr mode mask updatesAlexander Graf2013-01-181-12/+13
| | | | | | | The mode mask already masks out bits we don't care about, so the actual handling code can stay intact regardless. Signed-off-by: Alexander Graf <agraf@suse.de>
* openpic: move gcr write into a functionAlexander Graf2013-01-181-17/+22
| | | | | | | The GCR register contains too much functionality to be covered inside of the register switch statement. Move it out into a separate function. Signed-off-by: Alexander Graf <agraf@suse.de>
* cpu: Move cpu_index field to CPUStateAndreas Färber2013-01-151-1/+4
| | | | | | | | | | | | | Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
* Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agrafBlue Swirl2013-01-121-392/+640
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (31 commits) PPC: linux-user: Calculate context pointer explicitly target-ppc: Error out for -cpu host on unknown PVR target-ppc: Slim conversion of model definitions to QOM subclasses PPC: Bring EPR support closer to reality PPC: KVM: set has-idle in guest device tree kvm: Update kernel headers openpic: fix CTPR and de-assertion of interrupts openpic: move IACK to its own function openpic: IRQ_check: search the queue a word at a time openpic: fix sense and priority bits openpic: add some bounds checking for IRQ numbers openpic: use standard bitmap operations Revert "openpic: Accelerate pending irq search" openpic: always call IRQ_check from IRQ_get_next openpic/fsl: critical interrupts ignore mask before v4.1 openpic: make ctpr signed openpic: rework critical interrupt support openpic: make register names correspond better with hw docs ppc/booke: fix crit/mcheck/debug exceptions openpic: lower interrupt when reading the MSI register ...
| * PPC: Bring EPR support closer to realityAlexander Graf2013-01-071-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We already used to support the external proxy facility of FSL MPICs, but only implemented it halfway correctly. This patch adds support for * dynamic enablement of the EPR facility * interrupt acknowledgement only when the interrupt is delivered This way the implementation now is closer to real hardware. Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: fix CTPR and de-assertion of interruptsScott Wood2013-01-071-58/+123
| | | | | | | | | | | | | | | | | | | | | | | | Properly implement level-triggered interrupts by withdrawing an interrupt from the raised queue if the interrupt source de-asserts. Also withdraw from the raised queue if the interrupt becomes masked. When CTPR is written, check whether we need to raise or lower the interrupt output. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: move IACK to its own functionScott Wood2013-01-071-42/+53
| | | | | | | | | | | | | | | | Besides making the code cleaner, we will need a separate way to access IACK in order to implement EPR (external proxy) interrupt delivery. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: IRQ_check: search the queue a word at a timeScott Wood2013-01-071-12/+16
| | | | | | | | | | | | | | | | | | | | | | Search the queue more efficiently by first looking for a non-zero word, and then using the common bit-searching function to find the bit within the word. It would be even nicer if bitops_ffsl() could be hooked up to the compiler intrinsic so that bit-searching instructions could be used, but that's another matter. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: fix sense and priority bitsScott Wood2013-01-071-6/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the sense and priority bits were masked off when writing to IVPR, and all interrupts were treated as edge-triggered (despite the existence of code for handling level-triggered interrupts). Polarity is implemented only as storage. We don't simulate the bad effects that you'd get on real hardware if you set this incorrectly, but at least the guest sees the right thing when it reads back the register. Sense now controls level/edge on FSL external interrupts (and all interrupts on non-FSL MPIC). FSL internal interrupts do not have a sense bit (reads as zero), but are level. FSL timers and IPIs do not have sense or polarity bits (read as zero), and are edge-triggered. To accommodate FSL internal interrupts, QEMU's internal notion of whether an interrupt is level-triggered is separated from the IVPR bit. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: add some bounds checking for IRQ numbersScott Wood2013-01-071-0/+11
| | | | | | | | | | | | | | | | | | | | | | The two checks with abort() guard against potential QEMU-internal problems, but the EOI check stops the guest from causing updates to queue position -1 and other havoc if it writes EOI with no interrupt in service. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: remove hunk in code that didn't get applied yet] Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: use standard bitmap operationsScott Wood2013-01-071-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Besides the private implementation being redundant, namespace collisions prevented the use of other things in bitops.h. Serialization does get a bit more awkward, unfortunately, since the standard bitmap operations are "unsigned long" rather than "uint32_t", though in exchange we will get faster queue lookups on 64-bit hosts once we search a word at a time. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * Revert "openpic: Accelerate pending irq search"Scott Wood2013-01-071-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a9bd83f4c65de0058659ede009fa1a241f379edd. This counting approach is not robust against setting a bit that was already set, or clearing a bit that was already clear. Perhaps that is considered a bug, but besides the lack of any documentation for that restriction, it's a pretty unpleasant way for the problem to manifest itself. It could be made more robust by testing the current value of the bit before changing the count, but a later patch speeds up IRQ_check in all cases, not just when there's nothing pending. Hopefully that should be adequate to address performance concerns. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: always call IRQ_check from IRQ_get_nextScott Wood2013-01-071-7/+3
| | | | | | | | | | | | | | | | | | | | | | Previously the code relied on the queue's "next" field getting set to -1 sometime between an update to the bitmap, and the next call to IRQ_get_next. Sometimes this happened after the update. Sometimes it happened before the check. Sometimes it didn't happen at all. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic/fsl: critical interrupts ignore mask before v4.1Scott Wood2013-01-071-1/+4
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: make bool :1] Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: make ctpr signedScott Wood2013-01-071-3/+3
| | | | | | | | | | | | | | | | Other priorities are signed, so avoid comparisons between signed and unsigned. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: rework critical interrupt supportScott Wood2013-01-071-34/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Critical interrupts on FSL MPIC are not supposed to pay attention to priority, IACK, EOI, etc. On the currently modeled version it's not supposed to pay attention to the mask bit either. Also reorganize to make it easier to implement newer FSL MPIC models, which encode interrupt level information differently and support mcheck as well as crit, and to reduce problems for later patches in this set. Still missing is the ability to lower the CINT signal to the core, as IACK/EOI is not used. This will come with general IRQ-source-driven lowering in the next patch. New state is added which is not serialized, but instead is recomputed in openpic_load() by calling the appropriate write_IRQreg function. This should have the side effect of causing the IRQ outputs to be raised appropriately on load, which was missing. The serialization format is altered by swapping ivpr and idr (we'd like IDR to be restored before we run the IVPR logic), and moving interrupts to the end (so that other state has been restored by the time we run the IDR/IVPR logic. Serialization for this driver is not yet in a state where backwards compatibility is reasonable (assuming it works at all), and the current serialization format was not built for extensibility. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: fix for current code state] Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: make register names correspond better with hw docsScott Wood2013-01-071-178/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The base openpic specification doesn't provide abbreviated register names, so it's somewhat understandable that the QEMU code made up its own, except that most of the names that QEMU used didn't correspond to the terminology used by any implementation I could find. In some cases, like PCTP, the phrase "processor current task priority" could be found in the openpic spec when describing the concept, but the register itself was labelled "current task priority register" and every implementation seems to use either CTPR or the full phrase. In other cases, individual implementations disagree on what to call the register. The implementations I have documentation for are Freescale, Raven (MCP750), and IBM. The Raven docs tend to not use abbreviations at all. The IBM MPIC isn't implemented in QEMU. Thus, where there's disagreement I chose to use the Freescale abbreviations. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: rebase on current state of the code] Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: lower interrupt when reading the MSI registerScott Wood2013-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | This will stop things from breaking once it's properly treated as a level-triggered interrupt. Note that it's the MPIC's MSI cascade interrupts that are level-triggered; the individual MSIs are edge-triggered. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: fix debug printsScott Wood2013-01-071-17/+27
| | | | | | | | | | | | | | | | | | | | Fix various format errors when debug prints are enabled. Also cause error checking to happen even when debug prints are not enabled, and consistently use 0x for hex output. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: adjust for more recent code base, prettify DPRINTF macro] Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: fix coding style issuesAlexander Graf2013-01-071-45/+55
| | | | | | | | | | | | | | | | | | This patch fixes the following coding style violations: - structs have to be typedef and be CamelCase - if()s are always surrounded by curly braces Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: don't crash on a register access without a CPU contextScott Wood2013-01-071-1/+15
| | | | | | | | | | | | | | | | | | | | If we access a register via the QEMU memory inspection commands (e.g. "xp") rather than from guest code, we won't have a CPU context. Gracefully fail to access the register in that case, rather than crashing. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: s/opp->nb_irqs -1/opp->nb_cpus - 1/Scott Wood2013-01-071-2/+2
| | | | | | | | | | | | | | | | | | "opp->nb_irqs-1" would have been a minor coding style error, but putting in one space but not the other makes it look confusingly like a numeric literal "-1". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: BRR1 is not a CPU-specific register.Scott Wood2013-01-071-3/+2
| | | | | | | | | | | | | | | | | | | | | | It's in the address range that normally contains a magic redirection to the CPU-specific region of the curretn CPU, but it isn't actually a per-CPU register. On real hardware BRR1 shows up only at 0x40000, not at 0x60000 or other non-magic per-CPU areas. Plus, this makes it possible to read the register on the QEMU command line with "xp". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: support large vectors on FSL mpicScott Wood2013-01-071-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | Previously only the spurious vector was sized appropriately to the openpic model. Also, instances of "IPVP_VECTOR(opp->spve)" were replace with just "opp->spve", as opp->spve is already just a vector and not an IVPR. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: remove pcsr (CPU sensitivity register)Scott Wood2013-01-071-4/+0
| | | | | | | | | | | | | | | | | | I could not find this register in any spec (FSL, IBM, or OpenPIC) and the code doesn't do anything with it but initialize, save, or restore it. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * openpic: symbolicize some magic numbersScott Wood2013-01-071-22/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deefine symbolic names for some register bits, and use some that have already been defined. Also convert some register values from hex to decimal when it improves readability. IPVP_PRIORITY_MASK is corrected from (0x1F << 16) to (0xF << 16), in conjunction with making wider use of the symbolic name. I looked at Freescale and IBM MPIC docs and at the base OpenPIC spec, and all three had priority as 4 bits rather than 5. Plus, the magic nubmer that is being replaced with symbolic values treated the field as 4 bits wide. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | Make all static TypeInfos constAndreas Färber2013-01-101-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | Since 39bffca2030950ef6efe57c2fac8327a45ae1015 (qdev: register all types natively through QEMU Object Model), TypeInfo as used in the common, non-iterative pattern is no longer amended with information and should therefore be const. Fix the documented QOM examples: sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h Since frequently the wrong examples are being copied by contributors of new devices, fix all types in the tree: sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c This also avoids to piggy-back these changes onto real functional changes or other refactorings. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Merge commit '1dd3a74d2ee2d873cde0b390b536e45420b3fe05' into HEADPaolo Bonzini2012-12-171-2/+2
|\ | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * pci: update all users to look in pci/Michael S. Tsirkin2012-12-171-1/+1
| | | | | | | | | | | | update all users so we can remove the makefile hack. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | openpic: Accelerate pending irq searchAlexander Graf2012-12-141-0/+11
| | | | | | | | | | | | | | | | | | | | | | When we're done with one interrupt, we need to search for the next pending interrupt in the queue. This search has grown quite big now that we have more than 256 possible irq lines. So let's memorize how many interrupts we have pending in our bitmaps, so that we can always bail out in the usual case - the one where we're all done. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: fix minor coding style issuesAlexander Graf2012-12-141-6/+6
| | | | | | | | | | | | | | This patch removes all remaining occurences of spaces before function parameter indicating parenthesis. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: add Shared MSI supportAlexander Graf2012-12-141-20/+130
| | | | | | | | | | | | | | The OpenPIC allows MSI access through shared MSI registers. Implement them for the MPC8544 MPIC, so we can support MSIs. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: make brr1 model specificAlexander Graf2012-12-141-1/+4
| | | | | | | | | | | | | | Now that we can properly distinguish between openpic model differences, let's move brr1 out of the raven code path. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: convert to qdevAlexander Graf2012-12-141-142/+136
| | | | | | | | | | | | | | | | | | | | | | This patch converts the OpenPIC device to qdev. Along the way it renames the "openpic" target to "raven" and the "mpic" target to "fsl_mpic_20", to better reflect the actual models they implement. This way we have a generic OpenPIC device now that can handle different flavors of the OpenPIC specification. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: remove irq_outAlexander Graf2012-12-141-6/+2
| | | | | | | | | | | | | | | | The current openpic emulation contains half-ready code for bypass mode. Remove it, so that when someone wants to finish it they can start from a clean state. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: rename openpic_t to OpenPICStateAlexander Graf2012-12-141-34/+34
| | | | | | | | | | | | | | Rename the openpic_t struct to OpenPICState, so it adheres better to the current coding style rules. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: convert simple reg operations to builtin bitopsAlexander Graf2012-12-141-31/+36
| | | | | | | | | | | | | | | | | | | | The openpic code has its own bitmap code to access bits inside of a bitmap. However, that is overkill when we simply want to check for a bit inside of a uint32_t. So instead, let's use normal bit masks and C builtin shifts and ands. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: remove unused type variableAlexander Graf2012-12-141-25/+2
| | | | | | | | | | | | | | The openpic source irqs are carrying around a type indicator that is never accessed by anything. Remove it. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: unify memory api subregionsAlexander Graf2012-12-141-52/+56
| | | | | | | | | | | | | | | | The only difference between the "openpic" and "mpic" memory api subregion descriptors is the endianness. Unify them as openpic accessors with explicit endianness markers in their names. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: combine openpic and mpic reset functionsAlexander Graf2012-12-141-61/+42
| | | | | | | | | | | | | | The openpic and mpic reset handlers are almost identical. Combine them and extract the differences into state variables. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: merge mpic and openpic timer handlingAlexander Graf2012-12-141-100/+31
| | | | | | | | | | | | | | The openpic and mpic timer handling code is basically the same. Merge them. Signed-off-by: Alexander Graf <agraf@suse.de>
* | openpic: combine mpic and openpic irq raise functionsAlexander Graf2012-12-141-18/+16
| | | | | | | | | | | | | | | | | | The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical, just that the MPIC one can also raise critical interrupts. Combine those two and check for critical raise capability during runtime. Signed-off-by: Alexander Graf <agraf@suse.de>
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