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* Add instruction counter.pbrook2008-06-291-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
* Optimize MIPS timer read/write functionsaurel322008-04-111-31/+25
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4190 c046a42c-6fe2-441c-8c8c-71466251a162
* Break up vl.h.pbrook2007-11-171-1/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
* Timer start/stop implementation, by Aurelien Jarno.ths2007-09-251-5/+24
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162
* Partial support for 34K multithreading, not functional yet.ths2007-09-061-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
* Choose number of TLBs at runtime, by Herve Poussineau.ths2007-04-171-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
* Unify IRQ handling.pbrook2007-04-071-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix disabling of the Cause register for R2.ths2007-04-051-11/+11
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2612 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix BD flag handling, cause register contents, implement some more bitsths2007-03-181-0/+7
| | | | | | | for R2 interrupt handling. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
* Reworking MIPS interrupt handling, by Aurelien Jarno.ths2007-01-241-4/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
* Move the MIPS CPU timer in a seperate file, by Alec Voropay.ths2006-12-061-0/+85
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2225 c046a42c-6fe2-441c-8c8c-71466251a162
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