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* Compile some MIPS devices only onceBlue Swirl2010-03-271-1/+1
| | | | | | Move CPU specific declarations to a separate file. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* mips: add header to mips_int.c and mips_timer.cAurelien Jarno2010-03-141-0/+22
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Unexport ticks_per_sec variable. Create get_ticks_per_sec() functionJuan Quintela2009-09-111-5/+5
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Convert references to logfile/loglevel to use qemu_log*() macrosaliguori2009-01-151-3/+1
| | | | | | | | | | | | This is a large patch that changes all occurrences of logfile/loglevel global variables to use the new qemu_log*() macros. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
* target-mips: CP0 Random register improvementsaurel322009-01-081-3/+8
| | | | | | | | | | | - Use a LFSR to generate the random value - Make sure to not return the same value twice Based on a patch by Hervé Poussineau. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6233 c046a42c-6fe2-441c-8c8c-71466251a162
* MIPS: remove empty cpu_mips_irqctrl_init()aurel322008-09-141-4/+0
| | | | | | | | | cpu_mips_irqctrl_init() function in hw/mips_timer.c is empty. Attached patch removes it, and its callers. (Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5214 c046a42c-6fe2-441c-8c8c-71466251a162
* Add instruction counter.pbrook2008-06-291-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
* Optimize MIPS timer read/write functionsaurel322008-04-111-31/+25
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4190 c046a42c-6fe2-441c-8c8c-71466251a162
* Break up vl.h.pbrook2007-11-171-1/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
* Timer start/stop implementation, by Aurelien Jarno.ths2007-09-251-5/+24
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162
* Partial support for 34K multithreading, not functional yet.ths2007-09-061-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
* Choose number of TLBs at runtime, by Herve Poussineau.ths2007-04-171-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
* Unify IRQ handling.pbrook2007-04-071-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix disabling of the Cause register for R2.ths2007-04-051-11/+11
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2612 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix BD flag handling, cause register contents, implement some more bitsths2007-03-181-0/+7
| | | | | | | for R2 interrupt handling. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
* Reworking MIPS interrupt handling, by Aurelien Jarno.ths2007-01-241-4/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
* Move the MIPS CPU timer in a seperate file, by Alec Voropay.ths2006-12-061-0/+85
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2225 c046a42c-6fe2-441c-8c8c-71466251a162
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