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* Make all static TypeInfos constAndreas Färber2013-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Since 39bffca2030950ef6efe57c2fac8327a45ae1015 (qdev: register all types natively through QEMU Object Model), TypeInfo as used in the common, non-iterative pattern is no longer amended with information and should therefore be const. Fix the documented QOM examples: sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h Since frequently the wrong examples are being copied by contributors of new devices, fix all types in the tree: sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c This also avoids to piggy-back these changes onto real functional changes or other refactorings. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-3/+3
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* exec: refactor cpu_restore_stateBlue Swirl2012-12-161-3/+1
| | | | | | | | Refactor common code around calls to cpu_restore_state(). tb_find_pc() has now no external users, make it static. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvmvapic: Fix TB invalidation after instruction patchingJan Kiszka2012-11-101-4/+16
| | | | | | | | | | | | | | | Since 0b57e287, cpu_memory_rw_debug already triggers a TB invalidation. As it doesn't (and cannot) set is_cpu_write_access=1 but "consumes" the currently executed TB, the tb_invalidate_phys_page_range call from patch_instruction didn't work anymore. Fix this by open-coding the required bits to restore the CPU state from the current TB position before patching and resume execution on the patched instruction afterward. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* cpus: Pass CPUState to run_on_cpu()Andreas Färber2012-10-311-2/+4
| | | | | | | | CPUArchState is no longer needed. Move the declaration to include/qemu/cpu.h and add documentation. Signed-off-by: Andreas Färber <afaerber@suse.de>
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-9/+9
| | | | | | | | | | | | | | | target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* i386 hw/: Don't use CPUStateAndreas Färber2012-03-141-11/+11
| | | | | | | | | | Scripted conversion: for file in hw/apic.h hw/kvm/apic.c hw/kvmvapic.c hw/pc.c hw/vmport.c hw/xen_machine_pv.c; do sed -i "s/CPUState/CPUX86State/g" $file done Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* kvmvapic: align start address as well as sizeAvi Kivity2012-03-141-1/+3
| | | | | | | | | | | | | | | The kvmvapic code remaps a section of ROM as RAM to allow the guest to maintain state there. It is careful to align the section size to a page boundary, to avoid creating subpages, but neglects to do the same for the start address. These leads to an assert later on when the memory core tries to create a page which is half RAM and half ROM. Fix by aligning the start address to a page boundary. This can be triggered by running qemu-system-x86_64 -enable-kvm -vga none. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvmvapic: Introduce TPR access optimization for Windows guestsJan Kiszka2012-02-181-0/+805
This enables acceleration for MMIO-based TPR registers accesses of 32-bit Windows guest systems. It is mostly useful with KVM enabled, either on older Intel CPUs (without flexpriority feature, can also be manually disabled for testing) or any current AMD processor. The approach introduced here is derived from the original version of qemu-kvm. It was refactored, documented, and extended by support for user space APIC emulation, both with and without KVM acceleration. The VMState format was kept compatible, so was the ABI to the option ROM that implements the guest-side para-virtualized driver service. This enables seamless migration from qemu-kvm to upstream or, one day, between KVM and TCG mode. The basic concept goes like this: - VAPIC PV interface consisting of I/O port 0x7e and (for KVM in-kernel irqchip) a vmcall hypercall is registered - VAPIC option ROM is loaded into guest - option ROM activates TPR MMIO access reporting via port 0x7e - TPR accesses are trapped and patched in the guest to call into option ROM instead, VAPIC support is enabled - option ROM TPR helpers track state in memory and invoke hypercall to poll for pending IRQs if required Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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