hqemu - HQEMU

	Commit message (Collapse)	Author	Age	Files	Lines
*	cadence_ttc: Fix 'clear on read' behavior	Soren Brinkmann	2012-10-12	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \|	A missing call to qemu_set_irq() when reading the IRQ register required SW to write to the IRQ register to acknowledge an interrupt. With this patch the behavior is fixed: - Reading the interrupt register clears it and updates the timers interrupt status - Writes to the interrupt register are ignored Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
*	cadence_ttc: changed master clock frequency	Peter A. G. Crosthwaite	2012-06-19	1	-1/+1
\| \| \| \| \| \| \| \|	Change the timer clock frequency to 133MHz which is correct. the old 2.5MHz value was for the pre-silicon emulation platform. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
*	cadence_ttc: initial version of device model	Peter A. G. Crosthwaite	2012-03-07	1	-0/+489
	Implemented cadence Triple Timer Counter (TCC) Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: John Linn <john.linn@xilinx.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>