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* acpi: arm: add fw_cfg device node to dsdtGabriel L. Somlo2019-11-291-0/+15
| | | | | | | | | | | | | | | | Add a fw_cfg device node to the ACPI DSDT. This is mostly informational, as the authoritative fw_cfg MMIO region(s) are listed in the Device Tree. However, since we are building ACPI tables, we might as well be thorough while at it... Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Marc Marí <markmb@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1455906029-25565-5-git-send-email-somlo@cmu.edu Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* arm: boot: Support big-endian elfsPeter Crosthwaite2019-11-291-10/+83
| | | | | | | | | | | | | | | Support ARM big-endian ELF files in system-mode emulation. When loading an elf, determine the endianness mode expected by the elf, and set the relevant CPU state accordingly. With this, big-endian modes are now fully supported via system-mode LE, so there is no need to restrict the elf loading to the TARGET endianness so the ifdeffery on TARGET_WORDS_BIGENDIAN goes away. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fix typo in comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* loader: Add data swap option to load-elfPeter Crosthwaite2019-11-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Some CPUs are of an opposite data-endianness to other components in the system. Sometimes elfs have the data sections layed out with this CPU data-endianness accounting for when loaded via the CPU, so byte swaps (relative to other system components) will occur. The leading example, is ARM's BE32 mode, which is is basically LE with address manipulation on half-word and byte accesses to access the hw/byte reversed address. This means that word data is invariant across LE and BE32. This also means that instructions are still LE. The expectation is that the elf will be loaded via the CPU in this endianness scheme, which means the data in the elf is reversed at compile time. As QEMU loads via the system memory directly, rather than the CPU, we need a mechanism to reverse elf data endianness to implement this possibility. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is providedPeter Maydell2019-11-291-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | If the user passes us an EL3 boot rom, then it is going to want to implement the PSCI interface itself. In this case, disable QEMU's internal PSCI implementation so it does not get in the way, and instead start all CPUs in an SMP configuration at once (the boot rom will catch them all and pen up the secondaries until needed). The boot rom code is also responsible for editing the device tree to include any necessary information about its own PSCI implementation before eventually passing it to a NonSecure guest. (This "start all CPUs at once" approach is what both ARM Trusted Firmware and UEFI expect, since it is what the ARM Foundation Model does; the other approach would be to provide some emulated hardware for "start the secondaries" but this is simplest.) This is a compatibility break, but I don't believe that anybody was using a secure boot ROM with an SMP configuration. Such a setup would be somewhat broken since there was nothing preventing nonsecure guest code from calling the QEMU PSCI function to start up a secondary core in a way that completely bypassed the secure world. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-id: 1456853976-7592-1-git-send-email-peter.maydell@linaro.org
* hw/arm/virt: Make first flash device Secure-only if booting securePeter Maydell2019-11-291-14/+49
| | | | | | | | | | | | | | If the virt board is started with the 'secure' property set to request a Secure setup, then make the first flash device be visible only to the Secure world. This is a breaking change, but I don't expect it to be noticed by anybody, because running TZ-aware guests isn't common and those guests are generally going to be booting from the flash and implicitly expecting their Non-secure guests to not touch it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-5-git-send-email-peter.maydell@linaro.org
* hw/arm/virt: Load bios image to MemoryRegion, not physaddrPeter Maydell2019-11-291-19/+20
| | | | | | | | | | | If we're loading a BIOS image into the first flash device, load it into the flash's memory region specifically, not into the physical address where the flash resides. This will make a difference when the flash might be in the Secure address space rather than the Nonsecure one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-4-git-send-email-peter.maydell@linaro.org
* hw/arm/virt: Provide a secure-only RAM if booting in Secure modePeter Maydell2019-11-291-0/+23
| | | | | | | | | If we're booting in Secure mode, provide a secure-only RAM (just 16MB) so that secure firmware has somewhere to run from that won't be accessible to the Non-secure guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-2-git-send-email-peter.maydell@linaro.org
* virt: Lift the maximum RAM limit from 30GB to 255GBPeter Maydell2019-11-291-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The virt board restricts guests to only 30GB of RAM. This is a hangover from the vexpress-a15 board, and there's no inherent reason for it. 30GB is smaller than you might reasonably want to provision a VM for on a beefy server machine. Raise the limit to 255GB. We choose 255GB because the available space we currently have below the 1TB boundary is up to the 512GB mark, but we don't want to paint ourselves into a corner by assigning it all to RAM. So we make half of it available for RAM, with the 256GB..512GB range available for future non-RAM expansion purposes. If we need to provide more RAM to VMs in the future then we need to: * allocate a second bank of RAM starting at 2TB and working up * fix the DT and ACPI table generation code in QEMU to correctly report two split lumps of RAM to the guest * fix KVM in the host kernel to allow guests with >40 bit address spaces The last of these is obviously the trickiest, but it seems reasonable to assume that anybody configuring a VM with a quarter of a terabyte of RAM will be doing it on a host with more than a terabyte of physical address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1456402182-11651-1-git-send-email-peter.maydell@linaro.org
* raspi: fix SD card with recent sdhci changesAndrew Baumann2019-11-293-0/+30
| | | | | | | | | | Recent changes to sdhci broke SD on raspi. This change mirrors the logic to create the SD card device at the board level. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456351128-5560-1-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bios-linker-loader: document+validate inputMichael S. Tsirkin2019-11-291-1/+2
| | | | | | | | | | | | | | | | | While guest/host ABI is documented in hw/acpi/bios-linker-loader.c, the API was left undocumented. This adds documentation for all API functions. Additionally, input is validated to make sure all pointers fall within range of provided files. To allow this validation for checksum commands, bios_linker_loader_add_checksum is changed to accept GArray * in place of void *. Reported-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/arm/sysbus-fdt: remove qemu_fdt_setprop returned value checkEric Auger2019-11-291-14/+5
| | | | | | | | | qemu_fdt_setprop asserts in case of error hence no need to check the returned value. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/arm/sysbus-fdt: enable amd-xgbe dynamic instantiationEric Auger2019-11-291-6/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the instantiation of the vfio-amd-xgbe device from the QEMU command line (-device vfio-amd-xgbe,host="<device>"). The guest is exposed with a device tree node that combines the description of both XGBE and PHY (representation supported from 4.2 onwards kernel): Documentation/devicetree/bindings/net/amd-xgbe.txt. There are 5 register regions, 6 interrupts including 4 optional edge-sensitive per-channel interrupts. Some property values are inherited from host device tree. Host device tree must feature a combined XGBE/PHY representation (>= 4.2 host kernel). 2 clock nodes (dma and ptp) also are created. It is checked those clocks are fixed on host side. AMD XGBE node creation function has a dependency on vfio Linux header and more generally node creation function for VFIO platform devices only make sense with CONFIG_LINUX so let's protect this code with #ifdef CONFIG_LINUX. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/arm/sysbus-fdt: helpers for clock node generationEric Auger2019-11-291-0/+120
| | | | | | | | | | | | | | | | | | Some passthrough'ed devices depend on clock nodes. Those need to be generated in the guest device tree. This patch introduces some helpers to build a clock node from information retrieved in the host device tree. - copy_properties_from_host copies properties from a host device tree node to a guest device tree node - fdt_build_clock_node builds a guest clock node and checks the host fellow clock is a fixed one. fdt_build_clock_node will become static as soon as it gets used. A dummy pre-declaration is needed for compilation of this patch. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* device_tree: qemu_fdt_getprop_cell converted to use the error APIEric Auger2019-11-292-4/+8
| | | | | | | | | | | | | | This patch aligns the prototype with qemu_fdt_getprop. The caller can choose whether the function self-asserts on error (passing &error_fatal as Error ** argument, corresponding to the legacy behavior), or behaves differently such as simply output a message. In this later case the caller can use the new lenp parameter to interpret the error if any. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* sdhci_sysbus: Create SD card device in users, not the device itselfPeter Maydell2019-11-293-1/+45
| | | | | | | | | | | | Move the creation of the SD card device from the sdhci_sysbus device itself into the boards that create these devices. This allows us to remove the cannot_instantiate_with_device_add notation because we no longer call drive_get_next in the device model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1455646193-13238-7-git-send-email-peter.maydell@linaro.org
* all: Clean up includesPeter Maydell2019-11-293-0/+3
| | | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com>
* bcm2835_property: implement "get board revision" queryStephen Warren2019-11-293-0/+6
| | | | | | | | | | | | | | | | Return a valid value from the BCM2835 property mailbox query "get board revision". This query is used by U-Boot. Implementing it fixes the first obvious difference between qemu and real HW. The value returned is currently hard-coded to match the RPi2 I own. Other values are legal, e.g. different board manufacturer field values are likely to exist in the wild. Cc: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1454993910-24077-1-git-send-email-swarren@wwwdotorg.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: fix max-cpus checkAndrew Jones2019-11-291-5/+5
| | | | | | | | | | | | | | | | mach-virt doesn't yet support hotplug, but command lines specifying -smp <num>,maxcpus=<bigger-num> don't fail. Of course specifying bigger-num as something bigger than the machine supports, e.g. > 8 on a gicv2 machine, should fail though. This fix also makes mach- virt's max-cpus check truly consistent with the one in vl.c:main, as the one there was already correctly checking max-cpus instead of smp-cpus. Reported-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1454511578-24863-1-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Use error_fatal to simplify obvious fatal errors (again)Markus Armbruster2019-11-294-24/+4
| | | | | | | | | Done with the Coccinelle semantic patch from commit 007b065, plus manual clean up of dead variables. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1452783732-6581-1-git-send-email-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
* acpi: expose oem_id and oem_table_id in build_rsdt()Laszlo Ersek2019-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | Since build_rsdt() is implemented as common utility code (in "hw/acpi/aml-build.c"), it should expose -- and forward -- the oem_id and oem_table_id parameters between board code and the generic build_header() function. Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:ACPI/SMBIOS) Cc: Igor Mammedov <imammedo@redhat.com> (supporter:ACPI/SMBIOS) Cc: Shannon Zhao <zhaoshenglong@huawei.com> (maintainer:ARM ACPI Subsystem) Cc: Paolo Bonzini <pbonzini@redhat.com> (maintainer:X86) Cc: Richard W.M. Jones <rjones@redhat.com> Cc: Aleksei Kovura <alex3kov@zoho.com> Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Steven Newbury <steve@snewbury.org.uk> RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1248758 LP: https://bugs.launchpad.net/qemu/+bug/1533848 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
* acpi: take oem_id in build_header(), optionallyLaszlo Ersek2019-11-291-6/+6
| | | | | | | | | | | | | | | | | | | | | | This patch is the continuation of commit 8870ca0e94f2 ("acpi: support specified oem table id for build_header"). It will allow us to control the OEM ID field too in the SDT header. Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:ACPI/SMBIOS) Cc: Igor Mammedov <imammedo@redhat.com> (supporter:ACPI/SMBIOS) Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com> (maintainer:NVDIMM) Cc: Shannon Zhao <zhaoshenglong@huawei.com> (maintainer:ARM ACPI Subsystem) Cc: Paolo Bonzini <pbonzini@redhat.com> (maintainer:X86) Cc: Richard W.M. Jones <rjones@redhat.com> Cc: Aleksei Kovura <alex3kov@zoho.com> Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Steven Newbury <steve@snewbury.org.uk> RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1248758 LP: https://bugs.launchpad.net/qemu/+bug/1533848 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
* raspi: add raspberry pi 2 machineAndrew Baumann2019-11-292-1/+153
| | | | | | Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/boot: move highbank secure board setup code to common routineAndrew Baumann2019-11-292-35/+53
| | | | | | | | | | | The new version is slightly different, to support Rasbperry Pi (in particular, Pi1's arm11 core which doesn't support v7 instructions such as MOVW). Tested-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bcm2836: add bcm2836 SoC deviceAndrew Baumann2019-11-292-1/+166
| | | | | | | | This is the SoC for Raspberry Pi 2. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bcm2835_peripherals: add rollup device for bcm2835 peripheralsAndrew Baumann2019-11-292-0/+205
| | | | | | | | | | This device maintains all the non-CPU peripherals on bcm2835 (Pi1) which are also present on bcm2836 (Pi2). It also implements the private address spaces used for DMA and mailboxes. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: virt-acpi: each MADT.GICC entry as enabled unconditionallyIgor Mammedov2019-11-291-23/+3
| | | | | | | | | | | | | | | | | | | | in current impl. condition build_madt() { ... if (test_bit(i, cpuinfo->found_cpus)) is always true since loop handles only present CPUs in range [0..smp_cpus). But to fill usless cpuinfo->found_cpus we do unnecessary scan over QOM tree to find the same CPUs. So mark GICC as present always and drop not needed code that fills cpuinfo->found_cpus. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1454323689-248759-1-git-send-email-imammedo@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux bootsEdgar E. Iglesias2019-11-291-0/+2
| | | | | | | | | When booting Linux on AArch64 enabled cores, setup EL1 and EL2 to use AArch64. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* virt-acpi-build: add always-on property for timerAndrew Jones2019-11-291-1/+1
| | | | | | | | | | | | | | | | | | This patch is the ACPI equivalent of "hw/arm/virt: Add always-on property to the virt board timer". The timer is always on, and thus setting this informs Linux that it may switch off the periodic timer. Switching off the periodic timer substantially reduces the number of interrupts the host needs to inject. Testing note: AArch64 guests (the only ones currently booting with ACPI) do not actually need this patch to determine it can turn the periodic timer off. I therefore used a hacked guest kernel to ensure this patch works as the equivalent DT patch does. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1453380893-26174-1-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Add always-on property to the virt board timerChristoffer Dall2019-11-291-0/+1
| | | | | | | | | | | | The virt board has an arch timer, which is always on. Emit the "always-on" property to indicate to Linux that it can switch off the periodic timer and reduces the amount of interrupts injected into a guest. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1453204158-11412-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: add secure memory region and UARTPeter Maydell2019-11-291-7/+48
| | | | | | | | | | | Add a secure memory region to the virt board, which is the same as the nonsecure memory region except that it also has a secure-only UART in it. This is only created if the board is started with the '-machine secure=on' property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* hw/arm/virt: Wire up memory region to CPUs explicitlyPeter Maydell2019-11-291-0/+3
| | | | | | | | | | | Wire up the system memory region to the CPUs explicitly by setting the QOM property. This doesn't change anything over letting it default, but will be needed for adding a secure memory region later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* xlnx-ep108: Connect the SPI FlashAlistair Francis2019-11-291-0/+16
| | | | | | | | | | Connect the sst25wf080 SPI flash to the EP108 board. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xlnx-zynqmp: Connect the SPI devicesAlistair Francis2019-11-291-0/+31
| | | | | | | | | | | | | Connect the Xilinx SPI devices to the ZynqMP model. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [ PC changes * Use QOM alias for bus connectivity on SoC level ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free the g_strdup_printf() string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* ssi: Move ssi.h into a separate directoryAlistair Francis2019-11-297-7/+7
| | | | | | | | | | | | Move the ssi.h include file into the ssi directory. While touching the code also fix the typdef lines as checkpatch complains. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: Clean up includesPeter Maydell2019-11-2942-1/+42
| | | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1449505425-32022-4-git-send-email-peter.maydell@linaro.org
* ARM: virt: Don't generate RTC ACPI device when using UEFIShannon Zhao2019-11-291-19/+5
| | | | | | | | | | | | | | | When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. While UEFI can use libfdt to disable the RTC device node in the DTB that it passes to the OS, it cannot modify AML. Therefore, we won't generate the RTC ACPI device at all when using UEFI. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1452867091-4023-1-git-send-email-shannon.zhao@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xlnx-zynqmp: Add support for high DDR memory regionsAlistair Francis2019-11-292-19/+58
| | | | | | | | | | | | | | | | | | | | | | The Xilinx ZynqMP SoC and EP108 board supports three memory regions: - A 2GB region starting at 0 - A 32GB region starting at 32GB - A 256GB region starting at 768GB This patch adds support for the first two memory regions, which is automatically created based on the size specified by the QEMU memory command line argument. On hardware the physical memory region is one continuous region, it is then mapped into the three different regions by the DDRC. As we don't model the DDRC this is done at startup by QEMU. The board creates the memory region and then passes that memory region to the SoC. The SoC then maps the memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* error: Strip trailing '\n' from error string arguments (again)Markus Armbruster2019-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6daf194d, be62a2eb and 312fd5f got rid of a bunch, but they keep coming back. Tracked down with the Coccinelle semantic patch from commit 312fd5f. Cc: Fam Zheng <famz@redhat.com> Cc: Peter Crosthwaite <crosthwaitepeter@gmail.com> Cc: Bharata B Rao <bharata@linux.vnet.ibm.com> Cc: Dominik Dingel <dingel@linux.vnet.ibm.com> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: Jason J. Herne <jjherne@linux.vnet.ibm.com> Cc: Stefan Berger <stefanb@linux.vnet.ibm.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Cc: Changchun Ouyang <changchun.ouyang@intel.com> Cc: zhanghailiang <zhang.zhanghailiang@huawei.com> Cc: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Markus Armbruster <armbru@pond.sub.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Acked-by: Fam Zheng <famz@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <1450452927-8346-17-git-send-email-armbru@redhat.com>
* error: Use error_reportf_err() where it makes obvious senseMarkus Armbruster2019-11-292-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Done with this Coccinelle semantic patch @@ expression FMT, E, S; expression list ARGS; @@ - error_report(FMT, ARGS, error_get_pretty(E)); + error_reportf_err(E, FMT/*@@@*/, ARGS); ( - error_free(E); | exit(S); | abort(); ) followed by a replace of '%s"/*@@@*/' by '"' and some line rewrapping, because I can't figure out how to make Coccinelle transform strings. We now use the error whole instead of just its message obtained with error_get_pretty(). This avoids suppressing its hint (see commit 50b7b00), but I can't see how the errors touched in this commit could come with hints. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1450452927-8346-12-git-send-email-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
* error: Use error_report_err() where appropriate (again)Markus Armbruster2019-11-294-4/+4
| | | | | | | | | | | | | Same Coccinelle semantic patch as in commit 565f65d. We now use the original error whole instead of just its message obtained with error_get_pretty(). This avoids suppressing its hint (see commit 50b7b00), but I don't think the errors touched in this commit can come with hints. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <1450452927-8346-3-git-send-email-armbru@redhat.com>
* hw/arm/virt: Fix property "gic-version" error handlingMarkus Armbruster2019-11-291-3/+2
| | | | | | | | | | | | virt_set_gic_version() calls exit(1) when passed an invalid property value. Property setters are not supposed to do that. Screwed up in commit b92ad39. Harmless, because the property belongs to a machine. Set an error object instead. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* hw: Don't use hw_error() for machine initialization errorsMarkus Armbruster2019-11-291-2/+4
| | | | | | | | | | | | | | | | | | Printing CPU registers is not helpful during machine initialization. Moreover, these are straightforward configuration or "can get resources" errors, so dumping core isn't appropriate either. Replace hw_error() by error_report(); exit(1). Matches how we report these errors in other machine initializations. Cc: Richard Henderson <rth@twiddle.net> Cc: qemu-arm@nongnu.org Cc: qemu-ppc@nongnu.org Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Signed-off-by: Markus Armbruster <armbru@pond.sub.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <1450370121-5768-2-git-send-email-armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* hw: Inline the qdev_prop_set_drive_nofail() wrapperMarkus Armbruster2019-11-291-2/+2
| | | | | | Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1449764955-10741-3-git-send-email-armbru@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* Use error_fatal to simplify obvious fatal errorsMarkus Armbruster2019-11-297-83/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Done with this Coccinelle semantic patch: @@ type T; identifier FUN, RET; expression list ARGS; expression ERR, EC; @@ ( - T RET = FUN(ARGS, &ERR); + T RET = FUN(ARGS, &error_fatal); | - RET = FUN(ARGS, &ERR); + RET = FUN(ARGS, &error_fatal); | - FUN(ARGS, &ERR); + FUN(ARGS, &error_fatal); ) - if (ERR != NULL) { - error_report_err(ERR); - exit(EC); - } This is actually a more elegant version of my initial semantic patch by courtesy of Eduardo. It leaves dead Error * variables behind, cleaned up manually. Cc: qemu-arm@nongnu.org Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
* hw/arm/virt: Support legacy -nic command line syntaxAshok Kumar2019-11-291-0/+14
| | | | | | | | | | | | | | | | Support the legacy -nic syntax for creating PCI network devices as well as the new-style -device options. This makes life easier for people moving from x86 KVM virtualization to ARM KVM virtualization and expecting their network configuration options to work the same way for both setups. We use "virtio" as the default NIC model if the user doesn't specify one. Signed-off-by: Ashok Kumar <ashoks@broadcom.com> Message-id: 1452091659-17698-1-git-send-email-ashoks@broadcom.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: expanded and clarified commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* acpi: extend aml_and() to accept target argumentIgor Mammedov2019-11-291-1/+1
| | | | | | Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* acpi: extend aml_or() to accept target argumentIgor Mammedov2019-11-291-3/+3
| | | | | | | Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
* acpi: support specified oem table id for build_headerXiao Guangrong2019-11-291-6/+7
| | | | | | | | | | | | | Let build_header() support specified OEM table id so that we can build multiple SSDT later If the oem table id is not specified (aka, NULL), we use the default id instead as the previous behavior Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* i.MX: Add an i.MX25 specific CCM class/instanceJean-Christophe Dubois2019-11-291-1/+1
| | | | | | | | | With this CCM, i.MX25 timer is accurate with "real world time". Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 2c0cf90be767bfc8520661eca891ab22c61f18fe.1449528242.git.jcd@tribudubois.net Reviewed-by Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Split the CCM class into an abstract base class and a concrete classJean-Christophe Dubois2019-11-292-6/+6
| | | | | | | | | | | | | | | | | | The IMX_CCM class is now the base abstract class that is used by EPIT and GPT timer implementation. IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC. For now the i.MX25 continues to use the i.MX31 CCM implementation. An i.MX25 specific CCM will be introduced in a later patch. We also rework initialization to stop using deprecated sysbus device init. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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