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* arm: xlnx-zynqmp: Add boot-cpu propertyPeter Crosthwaite2015-06-192-2/+19
| | | | | | | | | | | Add a string property that specifies the primary boot cpu. All CPUs except the one selected will start-powered-off. This allows for elf boots on any CPU, which prepares support for booting R5 elfs directly on the R5 processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 53331c00d80c7ce9c6a83712348773f1b38fae2b.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Preface CPU variables with "apu"Peter Crosthwaite2015-06-192-13/+15
| | | | | | | | | | | | The CPUs currently supported by zynqmp are the APU (application processing unit) CPUs. There are other CPUs in Zynqmp so unqualified "cpus" in ambiguous. Preface the variables with "APU" accordingly, to prepare support adding the RPU (realtime processing unit) processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiationEric Auger2015-06-192-11/+74
| | | | | | | | | | | | | This patch allows the instantiation of the vfio-calxeda-xgmac device from the QEMU command line (-device vfio-calxeda-xgmac,host="<device>"). A specialized device tree node is created for the guest, containing compat, dma-coherent, reg and interrupts properties. Signed-off-by: Eric Auger <eric.auger@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1434455898-17895-1-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Add SPCR tableAndrew Jones2015-06-151-1/+42
| | | | | | | | | Signed-off-by: Andrew Jones <drjones@redhat.com> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1433929959-29530-3-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/boot: fix rom_reset notifier registration orderEric Auger2015-06-151-9/+11
| | | | | | | | | | | | | | commit ac9d32e39664e060cd1b538ff190980d57ad69e4 had the consequence to register the do_cpu_reset after the rom_reset one. Hence they get executed in the wrong order. This commit restores the registration of do_cpu_reset in arm_load_kernel. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reported-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434111582-9325-1-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/pxa2xx: Convert pxa2xx-ssp to VMStatePeter Maydell2015-06-151-57/+34
| | | | | | | | | The pxa2xx-ssp device is already a QOM device but is still using the old-style register_savevm(); convert to VMState. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434117989-7367-5-git-send-email-peter.maydell@linaro.org
* hw/arm/pxa2xx: Add reset method for pxa2xx_sspPeter Maydell2015-06-151-0/+18
| | | | | | | | The pxa2xx_ssp device was missing a reset method; add one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter..crosthwaite@xilinx.com> Message-id: 1434117989-7367-4-git-send-email-peter.maydell@linaro.org
* hw/arm/pxa2xx: Convert pxa2xx-fir to QOM and VMStatePeter Maydell2015-06-151-55/+86
| | | | | | | | | Convert the pxa2xx-fir device to QOM, including using a VMState for its migration info. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434117989-7367-3-git-send-email-peter.maydell@linaro.org
* hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IOPeter Maydell2015-06-152-5/+5
| | | | | | | | | | The pxa2xx custom coprocessor registers in cp6 and cp14 do device accesses, so mark the non-constant regs as ARM_CP_IO so that icount works correctly and doesn't abort. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434117989-7367-2-git-send-email-peter.maydell@linaro.org
* target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin2015-06-151-1/+1
| | | | | | | | | | | | | | | | | | When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Message-id: 02f601d0a1e6$90c7d630$b2578290$@samsung.com [PMM: Use a local #define rather than a global variable for the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the commit message.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Add cortex-a53 cpu support in machine virtShannon Zhao2015-06-151-0/+5
| | | | | | | | | | | Add cortex-a53 cpu support in machine virt, so it can be used for TCG and KVM. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1433207452-4512-3-git-send-email-shannon.zhao@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* pflash_cfi01: change big-endian property to BIT typePaolo Bonzini2015-06-052-2/+2
| | | | | | Make this consistent with the secure property, added in the next patch. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2015-06-042-4/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/mjt/tags/pull-trivial-patches-2015-06-03' into staging trivial patches for 2015-06-03 # gpg: Signature made Wed Jun 3 14:07:47 2015 BST using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" * remotes/mjt/tags/pull-trivial-patches-2015-06-03: (30 commits) configure: postfix --extra-cflags to QEMU_CFLAGS cadence_gem: Fix Rx buffer size field mask slirp: use less predictable directory name in /tmp for smb config (CVE-2015-4037) translate-all: delete prototype for non-existent function Add -incoming help text hw/display/tc6393xb.c: Fix misusing qemu_allocate_irqs for single irq hw/arm/nseries.c: Fix misusing qemu_allocate_irqs for single irq hw/alpha/typhoon.c: Fix misusing qemu_allocate_irqs for single irq hw/unicore32/puv3.c: Fix misusing qemu_allocate_irqs for single irq hw/lm32/milkymist.c: Fix misusing qemu_allocate_irqs for single irq hw/lm32/lm32_boards.c: Fix misusing qemu_allocate_irqs for single irq hw/ppc/prep.c: Fix misusing qemu_allocate_irqs for single irq hw/sparc/sun4m.c: Fix misusing qemu_allocate_irqs for single irq hw/timer/arm_timer.c: Fix misusing qemu_allocate_irqs for single irq hw/isa/i82378.c: Fix misusing qemu_allocate_irqs for single irq hw/isa/lpc_ich9.c: Fix misusing qemu_allocate_irqs for single irq hw/i386/pc: Fix misusing qemu_allocate_irqs for single irq hw/intc/exynos4210_gic.c: Fix memory leak by adjusting order hw/arm/omap_sx1.c: Fix memory leak spotted by valgrind hw/ppc/e500.c: Fix memory leak ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/nseries.c: Fix misusing qemu_allocate_irqs for single irqShannon Zhao2015-06-031-3/+2
| | | | | | | | | | | | Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * hw/arm/omap_sx1.c: Fix memory leak spotted by valgrindShannon Zhao2015-06-031-1/+1
| | | | | | | | | | | | Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | hw/arm/virt: change indentation in a15memmapEric Auger2015-06-021-14/+14
| | | | | | | | | | | | | | | | | | | | Re-indent in a15memmap after VIRT_PLATFORM_BUS introduction Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1433244554-12898-5-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/virt: add dynamic sysbus device supportEric Auger2015-06-021-1/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows sysbus devices to be instantiated from command line by using -device option. Machvirt creates a platform bus at init. The dynamic sysbus devices are attached to this platform bus device. The platform bus device registers a machine init done notifier whose role will be to bind the dynamic sysbus devices. Indeed dynamic sysbus devices are created after machine init. machvirt also registers a notifier that will build the device tree nodes for the platform bus and its children dynamic sysbus devices. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-4-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/boot: arm_load_kernel implemented as a machine init done notifierEric Auger2015-06-021-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Device tree nodes for the platform bus and its children dynamic sysbus devices are added in a machine init done notifier. To load the dtb once, after those latter nodes are built and before ROM freeze, the actual arm_load_kernel existing code is moved into a notifier notify function, arm_load_kernel_notify. arm_load_kernel now only registers the corresponding notifier. Machine files that do not support platform bus stay unchanged. Machine files willing to support dynamic sysbus devices must call arm_load_kernel before sysbus-fdt arm_register_platform_bus_fdt_creator to make sure dynamic sysbus device nodes are integrated in the dtb. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Shannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-3-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/sysbus-fdt: helpers for platform bus nodes additionEric Auger2015-06-022-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new C module will be used by ARM machine files to generate platform bus node and their dynamic sysbus device tree nodes. Dynamic sysbus device node addition is done in a machine init done notifier. arm_register_platform_bus_fdt_creator does the registration of this latter and is supposed to be called by ARM machine files that support platform bus and their dynamic sysbus. Addition of dynamic sysbus nodes is done only if the user did not provide any dtb. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Shannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-2-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target-arm: Add the GICv2m to the virt boardChristoffer Dall2015-06-021-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Reviewed-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target-arm: Extend the gic node propertiesChristoffer Dall2015-06-021-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding the GICv2m which requires address specifiers and is a subnode of the gic, we extend the gic DT definition to specify the #address-cells and #size-cells properties and add an empty ranges property properties of the DT node, since this is required to add the v2m node as a child of the gic node. Note that we must also expand the irq-map to reference the gic with the right address-cells as a consequence of this change. Reviewed-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-4-git-send-email-christoffer.dall@linaro.org Suggested-by: Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target-arm: Add GIC phandle to VirtBoardInfoChristoffer Dall2015-06-021-15/+11
|/ | | | | | | | | | | | | Instead of passing the GIC phandle around between functions, add it to the VirtBoardInfo just like we do for the clock_phandle. We are about to add the v2m phandle as well, and it's easier not having to pass around a bunch of phandles, return multiple values from functions, etc. Reviewed-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Enable dynamic generation of ACPI v5.1 tablesShannon Zhao2015-05-291-0/+19
| | | | | | | | | | Initialize VirtGuestInfoState and register a machine_init_done notify to call virt_acpi_build(). Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-25-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT tableShannon Zhao2015-05-291-0/+154
| | | | | | | | | | Add PCIe controller in ACPI DSDT table, so the guest can detect the PCIe. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-23-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate MCFG tableShannon Zhao2015-05-291-0/+23
| | | | | | | | | | Generate MCFG table for PCIe controller. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-14-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate RSDP tableShannon Zhao2015-05-291-1/+34
| | | | | | | | | | RSDP points to RSDT which in turn points to other tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-13-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate RSDT tableShannon Zhao2015-05-291-0/+3
| | | | | | | | | | | | | RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86. Here we still use RSDT as UEFI puts ACPI tables below 4G address space, and UEFI ignore the RSDT or XSDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-12-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate GTDT tableShannon Zhao2015-05-292-4/+33
| | | | | | | | | | | | ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate MADT tableShannon Zhao2015-05-291-0/+57
| | | | | | | | | | | MADT describes GIC enabled ARM platforms. The GICC and GICD subtables are used to define the GIC regions. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate FADT table and update ACPI headersShannon Zhao2015-05-291-0/+31
| | | | | | | | | | | | | | In the case of mach virt, it is used to set the Hardware Reduced bit and enable PSCI SMP booting through HVC. So ignore FACS and FADT points to DSDT. Update the header definitions for FADT taking into account the new additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h` Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generation of DSDT table for virt devicesShannon Zhao2015-05-291-0/+132
| | | | | | | | | | | | | | | | DSDT consists of the usual common table header plus a definition block in AML encoding which describes all devices in the platform. After initializing DSDT with header information the namespace is created which is followed by the device encodings. The devices are described using the Resource Template for the 32-Bit Fixed Memory Range and the Extended Interrupt Descriptors. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-8-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARMShannon Zhao2015-05-292-0/+183
| | | | | | | | | | | | | | | | | | | | | Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables - FADT: Generic information about the machine - GTDT: Generic timer description table - MADT: Multiple APIC description table - DSDT: Holds all information about system devices/peripherals, pointed by FADT Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Record PCIe ranges in MemMapEntry arrayShannon Zhao2015-05-291-24/+13
| | | | | | | | | | | To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Move common definitions to virt.hShannon Zhao2015-05-291-20/+1
| | | | | | | | | | | Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-ep108: Add bootloadingPeter Crosthwaite2015-05-181-0/+9
| | | | | | | | | | Add bootloader support using standard ARM bootloader. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b829abaf2b70d02b28e79301553cbd74afc416a1.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-ep108: Add external RAMPeter Crosthwaite2015-05-181-0/+20
| | | | | | | | | | Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2c25e2a4198402a6477aef2975d5df7c415dd341.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Add xlnx-ep108 machinePeter Crosthwaite2015-05-182-1/+54
| | | | | | | | | | | | Add a machine model for the Xilinx ZynqMP SoC EP108 board. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3896b34c862f370dc0679e4428bf3848d1f9f83c.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Add UART supportPeter Crosthwaite2015-05-181-0/+24
| | | | | | | | | | | There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Add GEM supportPeter Crosthwaite2015-05-181-0/+35
| | | | | | | | | | There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Connect CPU Timers to GICPeter Crosthwaite2015-05-181-0/+17
| | | | | | | | | | | Connect the GPIO outputs from the individual CPUs for the timers to the GIC. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Add GICPeter Crosthwaite2015-05-181-0/+59
| | | | | | | | | | Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Introduce Xilinx ZynqMP SoCPeter Crosthwaite2015-05-182-0/+77
| | | | | | | | | | | | | | With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/highbank.c: Wire FIQ between CPU <> GICPeter Maydell2015-05-121-0/+3
| | | | | | | Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-18-git-send-email-peter.maydell@linaro.org
* hw/arm/vexpress.c: Wire FIQ between CPU <> GICFabian Aggeler2015-05-121-0/+2
| | | | | | | | | | | | | Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-17-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-3-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt.c: Wire FIQ between CPU <> GICGreg Bellows2015-05-121-0/+2
| | | | | | | | | | | | Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-16-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-4-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Convert ffs() != 0 callers to ctz32()Stefan Hajnoczi2015-04-281-4/+2
| | | | | | | | | | | | | | | | | | | | There are a number of ffs(3) callers that do roughly: bit = ffs(val); if (bit) { do_something(bit - 1); } This pattern can be converted to ctz32() like this: zeroes = ctz32(val); if (zeroes != 32) { do_something(zeroes); } Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-6-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* Convert (ffs(val) - 1) to ctz32(val)Stefan Hajnoczi2015-04-282-3/+3
| | | | | | | | | | | | | | | | | | | This commit was generated mechanically by coccinelle from the following semantic patch: @@ expression val; @@ - (ffs(val) - 1) + ctz32(val) The call sites have been audited to ensure the ffs(0) - 1 == -1 case never occurs (due to input validation, asserts, etc). Therefore we don't need to worry about the fact that ctz32(0) == 32. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-5-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* hw/arm/nseries: convert ffs(3) to ctz32()Stefan Hajnoczi2015-04-281-1/+4
| | | | | | | | | | It is not clear from the code how a 0 parameter should be handled by the hardware. Keep the same behavior as ffs(0) - 1 == -1. Cc: Andrzej Zaborowski <balrog@zabor.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-3-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* target-arm: rename c1_coproc to cpacr_el1Sergey Fedorov2015-04-261-1/+1
| | | | | | | | | Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> [PMM: also fixed a couple of missed occurrences in cpu.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Switch non-CPU callers from ld/st*_phys to address_space_ld/st*Peter Maydell2015-04-262-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch all the uses of ld/st*_phys to address_space_ld/st*, except for those cases where the address space is the CPU's (ie cs->as). This was done with the following script which generates a Coccinelle patch. A few over-80-columns lines in the result were rewrapped by hand where Coccinelle failed to do the wrapping automatically, as well as one location where it didn't put a line-continuation '\' when wrapping lines on a change made to a match inside a macro definition. ===begin=== #!/bin/sh -e # Usage: # ./ldst-phys.spatch.sh > ldst-phys.spatch # spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch # patch -p1 < out.patch for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do cat <<EOF @ cpu_matches_ld_${FN} @ expression E1,E2; identifier as; @@ ld${FN}_phys(E1->as,E2) @ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @ expression E1,E2; @@ -ld${FN}_phys(E1,E2) +address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL) EOF done for FN in b w_le w_be l_le l_be q_le q_be w l q; do cat <<EOF @ cpu_matches_st_${FN} @ expression E1,E2,E3; identifier as; @@ st${FN}_phys(E1->as,E2,E3) @ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @ expression E1,E2,E3; @@ -st${FN}_phys(E1,E2,E3) +address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL) EOF done ===endit=== Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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