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* disas/mips: disable unused mips16_to_32_reg_map[]Leon Alrae2014-12-161-1/+2
| | | | | | | This array is used by print_mips16_insn_arg() which is guarded by #if 0. Therefore doing the same with the array as it generates clang warnings. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* disas/mips: remove unused mips_msa_control_names_numeric[32]Leon Alrae2014-12-161-7/+0
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* disas/mips.c: disassemble MSA instructionsYongbok Kim2014-11-031-2/+714
| | | | | | | disassemble MIPS SIMD Architecture instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: add TLBINV supportLeon Alrae2014-11-031-0/+2
| | | | | | | | | | | | | | | | For Standard TLB configuration (Config.MT=1): TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified. TLBINVF causes all entries to be invalidated. Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim2014-10-141-0/+2
| | | | | | Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add new Floating Point Comparison instructionsYongbok Kim2014-10-141-0/+44
| | | | | | Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add new Floating Point instructionsLeon Alrae2014-10-141-0/+22
| | | | | | | | | | | | In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt, MAXA.fmt replaced MIPS-3D RECIP1, RECIP2, RSQRT1, RSQRT2 instructions. In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been updated yet. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae2014-10-141-3/+39
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-mips: add compact and CP1 branchesYongbok Kim2014-10-131-3/+64
| | | | | | | | | | | Introduce MIPS32R6 Compact Branch instructions which do not have delay slot - they have forbidden slot instead. However, current implementation does not support forbidden slot yet. Add also BC1EQZ and BC1NEZ instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim2014-10-131-0/+4
| | | | | | Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae2014-10-131-0/+5
| | | | | | | | Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping with MIPS32R6 SDBBP. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae2014-10-131-0/+16
| | | | | | | | Use "R6_" prefix in front of all new Multiply / Divide instructions for easier differentiation between R6 and preR6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae2014-10-131-0/+4
| | | | | | | | | The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6. Additionally, the hint codes in PREF instruction greater than or equal to 24 generate Reserved Instruction Exception. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move LL and SC instructionsLeon Alrae2014-10-131-1/+8
| | | | | | | | The encoding of LL and SC instruction has changed in MIPS32 Release 6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
* target-mips: add SELEQZ and SELNEZ instructionsLeon Alrae2014-10-131-0/+8
| | | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-0/+4873
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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