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* added cpu_resume_from_signal() - irq fixbellard2004-04-251-20/+52
* PowerPC system emulation fixes (Jocelyn Mayer)bellard2004-04-121-1/+1
* win32 port (initial patch by kazu)bellard2004-03-311-0/+4
* do not depend on thunk.h - more log itemsbellard2004-03-211-3/+3
* initial x86-64 host support (Gwenole Beauchesne)bellard2004-03-171-0/+15
* native FPU support in code copy modebellard2004-02-251-1/+17
* experimental code copy support - CPU_INTERRUPT_EXITTB supportbellard2004-02-161-18/+134
* temporary interrupt locking fix (need rework)bellard2004-02-031-0/+1
* PowerPC merge (Jocelyn Mayer)bellard2004-01-181-1/+1
* simpler second page physical address testbellard2004-01-181-2/+3
* PowerPC System emulation (Jocelyn Mayer)bellard2004-01-041-5/+28
* support for new TLB handlingbellard2004-01-041-2/+47
* sparc fixesbellard2004-01-041-8/+8
* PowerPC target support (Jocelyn Mayer) - added better support for uid16bellard2003-11-231-7/+52
* fixed TB linking in case of code invalidation (fixes random segfaults)bellard2003-11-191-1/+12
* unused functions in system modebellard2003-10-301-1/+1
* fixed mmu fault priviledge logicbellard2003-10-271-2/+4
* sparc emulation target (thanx to Thomas M. Ogrisegg)bellard2003-09-301-8/+20
* removed x86 hacksbellard2003-09-171-17/+3
* faster and more accurate segment handlingbellard2003-08-211-16/+4
* pop ss, mov ss, x and sti disable irqs for the next instruction - began dispa...bellard2003-08-201-13/+13
* no error code if hardware interruptbellard2003-08-201-2/+2
* m68k host port (Richard Zidlicky)bellard2003-08-101-0/+17
* soft mmu supportbellard2003-08-101-6/+23
* correct CPL support (should fix flat real mode support)bellard2003-07-291-7/+2
* real mode supportbellard2003-07-261-9/+7
* gdb stub breakpoints supportbellard2003-07-261-1/+1
* ARM fixesbellard2003-07-091-7/+4
* fixed invalid irq jump chainingbellard2003-06-301-0/+7
* reduced irq latencybellard2003-06-301-20/+23
* suppressed ring 0 hacksbellard2003-06-251-15/+8
* hardware interrupt support - support forfull ring 0 exception simulationbellard2003-06-241-131/+195
* new segment accessbellard2003-06-211-10/+10
* main cpu loop is target independentbellard2003-06-151-0/+575
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