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* make: Remove duplicate use of GLIB_CFLAGSStefan Weil2012-02-091-1/+0
| | | | | | | | | | | Makefile, Makefile.hw, Makefile.target and libcacard/Makefile added GLIB_CFLAGS to QEMU_CFLAGS. Makefile.objs does this, too, and is included by all other Makefiles, so GLIB_CFLAGS were added twice (reported by malc). Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: malc <av1474@comtv.ru>
* w32: Build windows and console executablesStefan Weil2012-02-071-1/+15
| | | | | | | | | | | System emulation executables with SDL are typically windows executables. Sometimes console executables are more useful, so create both variants if linker option -mwindows was detected. v2: This version uses QEMU_PROGW / QEMU_PROG instead of QEMU_PROG / QEMU_PROGC. Signed-off-by: Stefan Weil <sw@weilnetz.de>
* qom: add the base Object class (v2)Anthony Liguori2012-01-271-0/+2
| | | | | | | | | | | | | | | | | | | | This class provides the main building block for QEMU Object Model and is extensively documented in the header file. It is largely inspired by GObject. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> --- v1 -> v2 - remove printf() in type registration - fix typo in comment (Paolo) - make Interface private - move object into a new directory and move header into include/qemu/ - don't make object.h depend on qemu-common.h - remove Type and replace it with TypeImpl * (Paolo) - use hash table to store types (Paolo) - aggressively cache parent type (Paolo) - make a type_register and use it with interfaces (Paolo) - fix interface cast comment (Paolo) - add a few more functions required in later series
* arm: SoC model for Calxeda HighbankRob Herring2012-01-261-0/+1
| | | | | | | | Adds support for Calxeda's Highbank SoC. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Add xgmac ethernet modelRob Herring2012-01-261-0/+1
| | | | | | | | | | | | | | | This adds very basic support for the xgmac ethernet core. Missing things include: - statistics counters - WoL support - rx checksum offload - chained descriptors (only linear descriptor ring) - broadcast and multicast handling Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* vga: compile cirrus_vga in hwlibBlue Swirl2012-01-251-1/+0
| | | | | | | | Remove target dependencies and compile Cirrus VGA in hwlib. Address masking can be removed since memory API handles that now. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* hyperv: fix build on non-KVM hostsBlue Swirl2012-01-231-1/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori2012-01-231-3/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * qemu-kvm/uq/master: kvm: Activate in-kernel irqchip support kvm: x86: Add user space part for in-kernel IOAPIC kvm: x86: Add user space part for in-kernel i8259 kvm: x86: Add user space part for in-kernel APIC kvm: x86: Establish IRQ0 override control kvm: Introduce core services for in-kernel irqchip support memory: Introduce memory_region_init_reservation ioapic: Factor out base class for KVM reuse ioapic: Drop post-load irr initialization i8259: Factor out base class for KVM reuse i8259: Completely privatize PicState apic: Open-code timer save/restore apic: Factor out base class for KVM reuse apic: Introduce apic_report_irq_delivered apic: Inject external NMI events via LINT1 apic: Stop timer on reset kvm: Move kvmclock into hw/kvm folder msi: Generalize msix_supported to msi_supported hyper-v: initialize Hyper-V CPUID leaves. hyper-v: introduce Hyper-V support infrastructure. Conflicts: Makefile.target Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
| * kvm: x86: Add user space part for in-kernel IOAPICJan Kiszka2012-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This introduces the KVM-accelerated IOAPIC model 'kvm-ioapic' and extends the IRQ routing setup by the 0->2 redirection when needed. The kvm-ioapic model has a property that allows to define its GSI base for injecting interrupts into the kernel model. This will allow to disentangle PIC and IOAPIC pins for chipsets that support more sophisticated IRQ routes than the PIIX3. So far the base is kept at 0, i.e. PIC and IOAPIC share pins 0..15. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: x86: Add user space part for in-kernel i8259Jan Kiszka2012-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the alternative 'kvm-i8259' device model that exploits KVM in-kernel acceleration. The PIIX3 initialization code is furthermore extended by KVM specific IRQ route setup. GSI injection differs in KVM mode from the user space model. As we can dispatch ISA-range IRQs to both IOAPIC and PIC inside the kernel, we do not need to inject them separately. This is reflected by a KVM-specific GSI handler. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: x86: Add user space part for in-kernel APICJan Kiszka2012-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This introduces the alternative APIC device which makes use of KVM's in-kernel device model. External NMI injection via LINT1 is emulated by checking the current state of the in-kernel APIC, only injecting a NMI into the VCPU if LINT1 is unmasked and configured to DM_NMI. MSI is not yet supported, so we disable this when the in-kernel model is in use. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * ioapic: Factor out base class for KVM reuseJan Kiszka2012-01-191-1/+1
| | | | | | | | | | | | | | | | Split up the IOAPIC analogously to APIC and i8259. KVM will share the IOAPICCommonState, the vmstate, reset logic and certain init parts with the user space model. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * apic: Factor out base class for KVM reuseJan Kiszka2012-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The KVM in-kernel APIC model will reuse parts of the user space model while providing the same frontend view to guest and most management interfaces. Factor out an APIC base class to encapsulate those parts that will be shared by user space and KVM model. This class offers callback hooks for init, base/tpr setting, and the external NMI delivery that will be set via APICCommonInfo structure and implemented specifically in the subclasses. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: Move kvmclock into hw/kvm folderJan Kiszka2012-01-191-2/+2
| | | | | | | | | | | | | | More KVM-specific devices will come, so let's start with moving the kvmclock into a dedicated folder. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * hyper-v: introduce Hyper-V support infrastructure.Vadim Rozenfeld2012-01-191-0/+2
| | | | | | | | | | | | [Jan: fix build with CONFIG_USER_ONLY] Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* | vga: make Cirrus ISA device optionalBlue Swirl2012-01-221-9/+4
| | | | | | | | | | Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | PPC: Bamboo: fold ppc440.c and ppc440_bamboo.c into a single fileAlexander Graf2012-01-211-1/+1
|/ | | | | | | | | The separation of ppc440 and ppc440_bamboo makes some sense, since ppc440 is the SoC while ppc440_bamboo is the actual board. But the separation makes things harder for us for no good reason, so let's just fold them in together with each other. Signed-off-by: Alexander Graf <agraf@suse.de>
* Merge branch 's390-next' of git://repo.or.cz/qemu/agrafAurelien Jarno2012-01-101-1/+4
|\ | | | | | | | | | | | | | | | | | | * 's390-next' of git://repo.or.cz/qemu/agraf: s390: fix cpu hotplug / cpu activity on interrupts s390x: add TR function for EXECUTE Expose drive_add on all architectures Add generic drive hotplugging Compile device-hotplug on all targets [S390] Add hotplug support
| * Compile device-hotplug on all targetsAlexander Graf2012-01-041-1/+4
| | | | | | | | | | | | | | | | | | All guest targets could potentially implement hotplugging. With the next patches in this set I will also reflect this in the monitor interface. So let's always compile it in. It shouldn't hurt. Signed-off-by: Alexander Graf <agraf@suse.de>
* | Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into stagingAnthony Liguori2012-01-041-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pmaydell/arm-devs.for-upstream: add L2x0/PL310 cache controller device arm: add dummy gic security registers arm: Set frequencies for arm_timer arm: add missing scu registers hw/omap_gpmc: Fix region map/unmap when configuring prefetch engine hw/omap1.c: Drop unused includes hw/omap1.c: Separate dpll_ctl from omap_mpu_state hw/omap1.c: Separate PWT from omap_mpu_state hw/omap1.c: Separate PWL from omap_mpu_state hw/omap1.c: omap_mpuio_init() need not be public hw/pl110.c: Add post-load hook to invalidate display hw/pl181.c: Add save/load support
| * | add L2x0/PL310 cache controller deviceRob Herring2012-01-041-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | This is just a dummy device for ARM L2 cache controllers, based on the pl310. The cache type parameter can be defined by a property value and has a meaningful default. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> [Peter Maydell: removed stray blank line at end] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | vmstate, memory: decouple vmstate from memory APIAvi Kivity2012-01-041-1/+1
|/ | | | | | | | | | | | | | Currently creating a memory region automatically registers it for live migration. This differs from other state (which is enumerated in a VMStateDescription structure) and ties the live migration code into the memory core. Decouple the two by introducing a separate API, vmstate_register_ram(), for registering a RAM block for migration. Currently the same implementation is reused, but later it can be moved into a separate list, and registrations can be moved to VMStateDescription blocks. Signed-off-by: Avi Kivity <avi@redhat.com>
* Makefile.target: Remove unnecessary dependency rulesPeter Maydell2011-12-161-6/+0
| | | | | | | | | | Remove some dependency rules which aren't necessary (the automatically generated .d files cover all these). These were leftovers from dyngen days, when the object files also had a dependency on some generated files. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* Merge remote-tracking branch 'stefanha/trivial-patches-next' into stagingAnthony Liguori2011-12-141-2/+0
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| * Makefile.target: Remove out of date commentChen Wei-Ren2011-12-091-2/+0
| | | | | | | | | | | | | | | | | | Remove the out of date comment, i.e., "# libqemu" since libqemu.a is not available anymore. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* | syborg: drop support for Symbian Virtual PlatformStefan Hajnoczi2011-12-121-3/+0
| | | | | | | | | | | | | | | | | | The Symbian Virtual Platform was an ARM-based development and debugging board. Since Symbian has been disbanded and the code is no longer being used it can now be removed. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* | hw/arm_mptimer.c: Turn ARM MPcore private timers into qdev devicesPeter Maydell2011-12-121-0/+1
|/ | | | | | | | Turn the ARM MPcore private timer/watchdog blocks into separate qdev devices. This will allow us to share them neatly between 11MPCore and A9MPcore. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge branch 'tci' of git://qemu.weilnetz.de/qemuBlue Swirl2011-11-021-0/+4
|\ | | | | | | | | | | | | | | | | | | * 'tci' of git://qemu.weilnetz.de/qemu: tcg: Add tcg interpreter to configure / make tcg: Add tci disassembler tcg: Add interpreter for bytecode tcg: Add bytecode generator for tcg interpreter tcg: Make ARRAY_SIZE(tcg_op_defs) globally available tcg: TCG targets may define tcg_qemu_tb_exec
| * tcg: Add tcg interpreter to configure / makeStefan Weil2011-10-311-0/+4
| | | | | | | | Signed-off-by: Stefan Weil <sw@weilnetz.de>
* | Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl2011-11-011-0/+1
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'ppc-next' of git://repo.or.cz/qemu/agraf: (24 commits) pseries: Add partial support for PCI ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate pseries: Allow writes to KVM accelerated TCE table KVM: PPC: Override host vmx/vsx/dfp only when information known ppc: Fix up usermode only builds pseries: Correct vmx/dfp handling in both KVM and TCG cases PPC: Fail configure when libfdt is not available ppc: Avoid decrementer related kvm exits PPC: Disable non-440 CPUs for ppcemb target PPC: Bump qemu-system-ppc to 64-bit physical address space pseries: Under kvm use guest cpu = host cpu by default ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3 ppc: First cut implementation of -cpu host ppc: Remove broken partial PVR matching pseries: Update SLOF firmware image pseries: Add device tree properties for VMX/VSX and DFP under kvm ppc: Generalize the kvmppc_get_clockfreq() function Set an invalid-bits mask for each SPE instructions pseries: Update SLOF firmware image pseries: Use Book3S-HV TCE acceleration capabilities ...
| * pseries: Add partial support for PCIDavid Gibson2011-10-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a PCI bus to the pseries machine. This instantiates the qemu generic PCI bus code, advertises a PCI host bridge in the guest's device tree and implements the RTAS methods specified by PAPR to access PCI config space. It also sets up the memory regions we need to provide windows into the PCI memory and IO space, and advertises those to the guest. However, because qemu can't yet emulate an IOMMU, which is mandatory on pseries, PCI devices which use DMA (i.e. most of them) will not work with this code alone. Still, this is enough to support the virtio_pci device (which probably _should_ use emulated PCI DMA, but is specced to use direct hypervisor access to guest physical memory instead). [agraf] remove typedef which could cause compile errors Signed-off-by: Alexey Kardashevskiy <aik@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* | Add AACI audio playback support to the ARM Versatile/PB platformMathieu Sonet2011-10-311-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver emulates the ARM AACI interface (PL041) connected to a LM4549 codec. It enables audio playback for the Versatile/PB platform. Limitations: - Supports only a playback on one channel (Versatile/Vexpress) - Supports only one TX FIFO in compact-mode or non-compact mode. - Supports playback of 12, 16, 18 and 20 bits samples. - Record is not supported. - The PL041 is hardwired to a LM4549 codec. Versatile/PB test build: linux-2.6.38.5 buildroot-2010.11 alsa-lib-1.0.22 alsa-utils-1.0.22 mpg123-0.66 Qemu host: Ubuntu 10.04 in Vmware/OS X Playback tested successfully with speaker-test/aplay/mpg123. Signed-off-by: Mathieu Sonet <contact@elasticsheep.com> [Peter Maydell: fixed typo in code clearing SL1RXBUSY/SL2RXBUSY bits, as spotted by Andrzej Zaborowski] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* Sparc: split load and store op helpersBlue Swirl2011-10-261-2/+3
| | | | | | | Move load and store op helpers top ldst_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split MMU helpersBlue Swirl2011-10-261-1/+1
| | | | | | | Move MMU helpers to mmu_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for CWP and PSTATE helpersBlue Swirl2011-10-261-1/+1
| | | | | | | | Make CWP and PSTATE helpers take a parameter for CPUState instead of relying on global env. Remove wrapper functions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split CWP and PSTATE op helpersBlue Swirl2011-10-231-2/+2
| | | | | | | Move CWP and PSTATE op helpers to win_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for lazy condition code helpersBlue Swirl2011-10-231-1/+1
| | | | | | | | Make lazy condition code helpers take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split lazy condition code handling op helpersBlue Swirl2011-10-231-2/+2
| | | | | | | Move lazy condition code handling op helpers to cc_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for float and VIS opsBlue Swirl2011-10-231-1/+1
| | | | | | | | Make floating point and VIS ops take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split FPU and VIS op helpersBlue Swirl2011-10-231-2/+3
| | | | | | | | Move FPU op helpers to fop_helper.c. Move VIS op helpers to vis_helper.c, compile it only for Sparc64. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split helper.cBlue Swirl2011-10-231-0/+5
| | | | | | | | Move CPU init to cpu_init.c and interrupt handling to int32_helper.c for Sparc32 and int64_helper.c for Sparc64. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* i8259: Move to hw libraryJan Kiszka2011-10-161-4/+4
| | | | | | | No target-specific bits remaining, let's move it over. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: add Avnet LX60/LX110/LX200 boardsMax Filippov2011-10-161-0/+1
| | | | | | | | | | | These boards carry similar hardware: SDRAM (48M for LX110, 64M for LX60, 96M for LX200), 16 Mbyte FLASH, FPGA, 10/100 Mbps Ethernet PHY and 16550 UART. FPGA may be loaded with almost any Tensilica processor. It is also used to implement Ethernet MAC, e.g. OpenCores 10/100 Mbps Ethernet MAC and LED/DIP switches access. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: rename dc232b board to simMax Filippov2011-10-161-1/+1
| | | | | | | This is to get aligned with the linux name for this machine. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: add fsf coreMax Filippov2011-10-161-0/+1
| | | | | | | This is FSF big endian core implemented through linux overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: add dc232b coreMax Filippov2011-10-161-0/+1
| | | | | | | | This is Diamond 232L Standard Core Rev.B (LE), implemented through linux/gdb overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-xtensa: remove hand-written xtensa cores implementationsMax Filippov2011-10-161-1/+0
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge remote-tracking branch 'qemu-kvm-tmp/memory/batch' into stagingAnthony Liguori2011-10-141-1/+1
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| * Introduce PortioListAvi Kivity2011-10-111-1/+1
| | | | | | | | | | | | | | | | | | | | Add a type and methods for manipulating a list of disjoint I/O ports, used in some older hardware devices. Based on original patch by Richard Henderson. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
* | Merge remote-tracking branch 'qmp/queue/qmp' into stagingAnthony Liguori2011-10-101-3/+3
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