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* target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson2013-02-233-19/+14
| | | | | | Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-arm: Use mul[us]2 in gen_mul[us]_i64_i32Richard Henderson2013-02-231-16/+22
| | | | | | Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-s390x: Use mulu2 for mlgr insnRichard Henderson2013-02-233-11/+1
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-alpha: Use mulu2 for umulh insnRichard Henderson2013-02-233-10/+18
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Apply life analysis to 64-bit multiword arithmetic opsRichard Henderson2013-02-231-8/+20
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Implement muls2 with mulu2Richard Henderson2013-02-231-0/+40
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: Use add2 to implement the ADX extensionRichard Henderson2013-02-231-11/+9
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-arm: Implement muls2_i32Richard Henderson2013-02-232-1/+5
| | | | | | | | We even had the encoding of smull already handy... Cc: Andrzej Zaborowski <balrogg@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-i386: Implement multiword arithmetic opsRichard Henderson2013-02-232-17/+26
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Implement multiword addition helpersRichard Henderson2013-02-231-0/+82
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Implement multiword multiply helpersRichard Henderson2013-02-233-1/+101
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Implement a 64-bit to 32-bit extraction helperRichard Henderson2013-02-231-0/+22
| | | | | | | We're going to have use for this shortly in implementing other helpers. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Add signed multiword multiplication operationsRichard Henderson2013-02-2314-0/+24
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Add 64-bit multiword arithmetic operationsRichard Henderson2013-02-2310-14/+41
| | | | | | Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-sparc: Always implement 32-bit multiword opsRichard Henderson2013-02-232-6/+7
| | | | | | Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg-i386: Always implement 32-bit multiword opsRichard Henderson2013-02-232-12/+13
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson2013-02-238-4/+29
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge branch 'eflags3' of git://github.com/rth7680/qemuBlue Swirl2013-02-2310-1449/+1870
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'eflags3' of git://github.com/rth7680/qemu: (61 commits) target-i386: Use movcond to implement shiftd. target-i386: Discard CC_OP computation in set_cc_op also target-i386: Use movcond to implement rotate flags. target-i386: Use movcond to implement shift flags. target-i386: Add CC_OP_CLR target-i386: Implement tzcnt and fix lzcnt target-i386: Use clz/ctz for bsf/bsr helpers target-i386: Implement ADX extension target-i386: Implement RORX target-i386: Implement SHLX, SARX, SHRX target-i386: Implement PDEP, PEXT target-i386: Implement MULX target-i386: Implement BZHI target-i386: Implement BLSR, BLSMSK, BLSI target-i386: Implement BEXTR target-i386: Implement ANDN target-i386: Implement MOVBE target-i386: Decode the VEX prefixes target-i386: Tidy prefix parsing target-i386: Use CC_SRC2 for ADC and SBB ...
| * target-i386: Use movcond to implement shiftd.Richard Henderson2013-02-191-141/+106
| | | | | | | | | | | | | | With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Discard CC_OP computation in set_cc_op alsoRichard Henderson2013-02-191-3/+11
| | | | | | | | | | | | | | | | The shift and rotate insns use movcond to set CC_OP, and thus achieve a conditional EFLAGS setting. By discarding CC_OP in a later flags setting insn, we can discard that movcond. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Use movcond to implement rotate flags.Richard Henderson2013-02-191-116/+121
| | | | | | | | | | | | | | With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Use movcond to implement shift flags.Richard Henderson2013-02-191-52/+42
| | | | | | | | | | | | | | With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Add CC_OP_CLRRichard Henderson2013-02-194-3/+21
| | | | | | | | | | | | | | Special case xor with self. We need not even store the known zero into cc_src. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement tzcnt and fix lzcntRichard Henderson2013-02-193-48/+54
| | | | | | | | | | | | | | | | We weren't computing flags for lzcnt at all. At the same time, adjust the implementation of bsf/bsr to avoid the local branch, using movcond instead. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Use clz/ctz for bsf/bsr helpersRichard Henderson2013-02-192-37/+14
| | | | | | | | | | | | And mark the helpers as NO_RWG_SE. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement ADX extensionRichard Henderson2013-02-195-5/+146
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement RORXRichard Henderson2013-02-181-0/+32
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement SHLX, SARX, SHRXRichard Henderson2013-02-181-0/+31
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement PDEP, PEXTRichard Henderson2013-02-183-0/+71
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement MULXRichard Henderson2013-02-183-0/+47
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement BZHIRichard Henderson2013-02-181-0/+27
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement BLSR, BLSMSK, BLSIRichard Henderson2013-02-185-1/+95
| | | | | | | | | | | | Do all of group 17 at one time for ease. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement BEXTRRichard Henderson2013-02-181-0/+40
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement ANDNRichard Henderson2013-02-182-7/+22
| | | | | | | | | | | | | | As this is the first of the BMI insns to be implemented, this carries quite a bit more baggage than normal. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Implement MOVBERichard Henderson2013-02-182-28/+110
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Decode the VEX prefixesRichard Henderson2013-02-181-4/+64
| | | | | | | | | | | | No actual required uses of these encodings yet. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Tidy prefix parsingRichard Henderson2013-02-181-82/+52
| | | | | | | | | | | | Avoid duplicating switch statement between 32 and 64-bit modes. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Use CC_SRC2 for ADC and SBBRichard Henderson2013-02-185-85/+75
| | | | | | | | | | | | | | | | Add another slot in ENV and store two of the three inputs. This lets us do less work when carry-out is not needed, and avoids the unpredictable CC_OP after translating these insns. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Make helper_cc_compute_{all,c} constRichard Henderson2013-02-183-14/+33
| | | | | | | | | | | | | | Pass the data in explicitly, rather than indirectly via env. This avoids all sorts of unnecessary register spillage. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Don't reference ENV through most of cc helpersRichard Henderson2013-02-182-282/+180
| | | | | | | | | | | | | | | | | | In preparation for making this a const helper. By using the proper types in the parameters to the helper functions, we get to avoid quite a lot of subsequent casting. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: optimize flags checking after sub using CC_SRCTRichard Henderson2013-02-181-15/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After a comparison or subtraction, the original value of the LHS will currently be reconstructed using an addition. However, in most cases it is already available: store it in a temp-local variable and save 1 or 2 TCG ops (2 if the result of the addition needs to be extended). The temp-local can be declared dead as soon as the cc_op changes again, or also before the translation block ends because gen_prepare_cc will always make a copy before returning it. All this magic, plus copy propagation and dead-code elimination, ensures that the temp local will (almost) never be spilled. Example (cmp $0x21,%rax + jbe): Before After ---------------------------------------------------------------------------- movi_i64 tmp1,$0x21 movi_i64 tmp1,$0x21 movi_i64 cc_src,$0x21 movi_i64 cc_src,$0x21 sub_i64 cc_dst,rax,tmp1 sub_i64 cc_dst,rax,tmp1 add_i64 tmp7,cc_dst,cc_src movi_i32 cc_op,$0x11 movi_i32 cc_op,$0x11 brcond_i64 tmp7,cc_src,leu,$0x0 discard loc11 brcond_i64 rax,cc_src,leu,$0x0 Before After ---------------------------------------------------------------------------- mov (%r14),%rbp mov (%r14),%rbp mov %rbp,%rbx mov %rbp,%rbx sub $0x21,%rbx sub $0x21,%rbx lea 0x21(%rbx),%r12 movl $0x11,0xa0(%r14) movl $0x11,0xa0(%r14) movq $0x21,0x90(%r14) movq $0x21,0x90(%r14) mov %rbx,0x98(%r14) mov %rbx,0x98(%r14) cmp $0x21,%r12 | cmp $0x21,%rbp jbe ... jbe ... Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Update cc_op before TCG branchesRichard Henderson2013-02-181-4/+4
| | | | | | | | | | | | | | | | | | Placing the CC_OP_DYNAMIC at the join is less effective than before the branch, as the branch will have forced global registers to their home locations. This way we have a chance to discard CC_SRC2 before it gets stored. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: introduce gen_jcc1_noeobRichard Henderson2013-02-181-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | A jump that ends a basic block or otherwise falls back to CC_OP_DYNAMIC will always have to call gen_op_set_cc_op. However, not all jumps end a basic block, so introduce a variant that does not do this. This was partially undone earlier (i386: drop cc_op argument of gen_jcc1), redo it now also to prepare for the introduction of src2. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: use gen_op for cmps/scasRichard Henderson2013-02-181-14/+6
| | | | | | | | | | | | | | | | Replace low-level ops with a higher-level "cmp %al, (A0)" in the case of scas, and "cmp T0, (A0)" in the case of cmps. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: kill cpu_T3Paolo Bonzini2013-02-181-11/+8
| | | | | | | | | | | | | | | | | | It is almost unused, and it is simpler to pass a TCG value directly to gen_shiftd_rm_T1_T3. This value is then written to t2 without going through a temporary register. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: expand cmov via movcondRichard Henderson2013-02-181-25/+20
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: introduce gen_cmovcc1Paolo Bonzini2013-02-181-34/+38
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: cleanup temporary macros for CCPreparePaolo Bonzini2013-02-181-47/+39
| | | | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: inline gen_prepare_cc_slowRichard Henderson2013-02-181-45/+46
| | | | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: use CCPrepare to generate conditional jumpsPaolo Bonzini2013-02-181-110/+9
| | | | | | | | | | | | | | | | | | This simplifies all the jump generation code. CCPrepare allows the code to create an efficient brcond always, so there is no need to duplicate the setcc and jcc code. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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