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* target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell2014-02-265-23/+34
| | | | | | | | | | | | | | | To avoid complication in code that otherwise would not need to care about whether EL1 is AArch32 or AArch64, we should store the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF in AArch64) in one place consistently regardless of EL1's mode. Since AArch64 has an extra enable bit (D for debug exceptions) which isn't visible in AArch32, this means we need to keep the enables in env->pstate. (This is also consistent with the general approach we're taking that we handle 32 bit CPUs as being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: A64: Implement WFIPeter Maydell2014-02-261-1/+4
| | | | | | | | | Implement the WFI instruction for A64; this just involves wiring up the instruction, and adding a gen_a64_set_pc_im() which was accidentally omitted from the A64 decoder top loop. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Get MMU index information correct for A64 codePeter Maydell2014-02-262-4/+9
| | | | | | | | | | | Emit the correct MMU index information for loads and stores from A64 code, rather than hardwiring it to "always kernel mode", by storing the exception level in the TB flags, and make cpu_mmu_index() return the right answer when the CPU is in AArch64 mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 OSLAR_EL1 sysreg as WIPeter Maydell2014-02-261-0/+4
| | | | | | | | | Define a dummy version of the AArch64 OSLAR_EL1 system register which just ignores writes. Linux will always write to this (it is the OS lock used for debugging), but we don't support debug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 dummy breakpoint and watchpoint registersPeter Maydell2014-02-262-0/+36
| | | | | | | | | In AArch64 the breakpoint and watchpoint registers are mandatory, so the kernel always accesses them on bootup. Implement dummy versions, which read as written but have no actual effect. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 ID and feature registersPeter Maydell2014-02-262-0/+55
| | | | | | | | | | Implement the AArch64-specific ID and feature registers. Although many of these are currently not used by the architecture (and so always zero for all implementations), we define the full set of fields in the ARMCPU struct for symmetry. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 generic timersPeter Maydell2014-02-262-14/+75
| | | | | | Implement the AArch64 view of the generic timer system registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement AArch64 MPIDRPeter Maydell2014-02-261-2/+4
| | | | | | | Implement the AArch64 MPIDR system register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 TTBR*Peter Maydell2014-02-263-64/+33
| | | | | | | | | | | Implement the AArch64 TTBR* registers. For v7 these were already 64 bits to handle LPAE, but implemented as two separate uint32_t fields. Combine them into a single uint64_t which can be used for all purposes. Since this requires touching every use, take the opportunity to rename the field to the architectural name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 VBAR_EL1Peter Maydell2014-02-262-2/+9
| | | | | | | Implement the A64 view of the VBAR system register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 TCR_EL1Peter Maydell2014-02-262-4/+17
| | | | | | | | | | | | | | Implement the AArch64 TCR_EL1, which is the 64 bit view of the AArch32 TTBCR. (The uses of the bits in the register are completely different, but in any given situation the CPU will always interpret them one way or the other. In fact for QEMU EL1 is always 64 bit, but we share the state field because this is the correct mapping to permit a future implementation of EL2.) We also make the AArch64 view the 'master' as far as migration and reset is concerned. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 SCTLR_EL1Peter Maydell2014-02-262-2/+3
| | | | | | | Implement the AArch64 view of the system control register SCTLR_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 memory attribute registersPeter Maydell2014-02-262-1/+26
| | | | | | | | | | | | | | | | | Implement the AArch64 memory attribute registers. Since QEMU doesn't model caches it does not need to care about memory attributes at all, and we can simply make these read-as-written. We did not previously implement the AArch32 versions of the MAIR registers, which went unnoticed because of the overbroad TLB_LOCKDOWN reginfo definition; provide them now to keep the 64<->32 register relationship clear. We already provided AMAIR registers for 32 bit as simple RAZ/WI; extend that to provide a 64 bit RAZ/WI AMAIR_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 dummy MDSCR_EL1Peter Maydell2014-02-261-0/+6
| | | | | | | | | We don't support letting the guest do debug, but Linux prods the monitor debug system control register anyway, so implement a dummy RAZ/WI version. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 TLB invalidate opsPeter Maydell2014-02-261-0/+73
| | | | | | | | Implement the AArch64 TLB invalidate operations. This is the full set of TLBI ops defined for a CPU which doesn't implement EL2 or EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell2014-02-262-2/+49
| | | | | | | | | Implement all the AArch64 cache invalidate and clean ops (which are all NOPs since QEMU doesn't emulate the cache). The only remaining unimplemented cache op is DC ZVA. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 MIDR_EL1Peter Maydell2014-02-261-0/+3
| | | | | | | | | Implement the AArch64 view of the MIDR system register (for AArch64 it is a simple constant, unlike the complicated mess that TI925 imposes on the 32-bit view). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Implement AArch64 CurrentEL sysregPeter Maydell2014-02-263-1/+12
| | | | | | | Implement the CurrentEL sysreg. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell2014-02-264-11/+25
| | | | | | | | | | | | | Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR) visible to AArch64. These are mostly simple 64-bit extensions of the existing 32 bit system registers and so can share reginfo definitions. CTR needs to have a split definition, but we can clean up the temporary user-mode implementation in favour of using the CPU-specified reset value, and implement the system-mode-required semantics of restricting its EL0 accessibility if SCTLR.UCT is not set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell2014-02-263-3/+15
| | | | | | | | | | | | The raw read and write functions were using the ARM_CP_64BIT flag in ri->type to determine whether to treat the register's state field as uint32_t or uint64_t; however AArch64 register info structs don't use that flag. Abstract out the "how big is the field?" test into a function and fix it to work for AArch64 registers. For this to work we must ensure that the reginfo structs put into the hashtable have the correct state field for their use, not the placeholder STATE_BOTH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: arm_gic_kvm: Add KVM VGIC save/restore logicChristoffer Dall2014-02-261-2/+422
| | | | | | | | | | | | | | | | | Save and restore the ARM KVM VGIC state from the kernel. We rely on QEMU to marshal the GICState data structure and therefore simply synchronize the kernel state with the QEMU emulated state in both directions. We take some care on the restore path to check the VGIC has been configured with enough IRQs and CPU interfaces that we can properly restore the state, and for separate set/clear registers we first fully clear the registers and then set the required bits. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687921-26921-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: vgic device control api supportChristoffer Dall2014-02-264-15/+80
| | | | | | | | | | | | | | | | | | | Support creating the ARM vgic device through the device control API and setting the base address for the distributor and cpu interfaces in KVM VMs using this API. Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be created prior to creating the VCPUs, we first test if we can use the device control API in kvm_arch_irqchip_create (using the test flag from the device control API). If we cannot, it means we have to fall back to KVM_CREATE_IRQCHIP and use the older ioctl at this point in time. If however, we can use the device control API, we don't do anything and wait until the arm_gic_kvm driver initializes and let that use the device control API. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687720-26806-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* kvm: Common device control API functionsChristoffer Dall2014-02-263-0/+62
| | | | | | | | | | | | | | Introduces two simple functions: int kvm_device_ioctl(int fd, int type, ...); int kvm_create_device(KVMState *s, uint64_t type, bool test); These functions wrap the basic ioctl-based interactions with KVM in a way similar to other KVM ioctl wrappers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687720-26806-4-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* kvm: Introduce kvm_arch_irqchip_createChristoffer Dall2014-02-264-2/+29
| | | | | | | | | | | | | | Introduce kvm_arch_irqchip_create an arch-specific hook in preparation for architecture-specific use of the device control API to create IRQ chips. Following patches will implement the ARM irqchip create method to prefer the device control API over the older KVM_CREATE_IRQCHIP API. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687720-26806-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* linux-headers: Update from v3.14-rc3Christoffer Dall2014-02-265-4/+74
| | | | | | | | Update to tag v3.14-rc3 (6d0abeca3242a88cab8232e4acd7e2bf088f3bc2) Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687720-26806-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gic: Fix GIC_SET_LEVELChristoffer Dall2014-02-261-1/+1
| | | | | | | | | | | | The GIC_SET_LEVEL macro unfortunately overwrote the entire level bitmask instead of just or'ing on the necessary bits, causing active level PPIs on a core to clear PPIs on other cores. Cc: qemu-stable@nongnu.org Reported-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1393031030-8692-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Load correct access bits from ARMv5 level 2 page table descriptorsPeter Maydell2014-02-261-1/+1
| | | | | | | | | | | | | | | | | | | In ARMv5 level 2 page table descriptors, each 4K or 64K page is split into four subpages, each of which can have different access permission settings, which are specified by four two-bit fields in the l2 descriptor. A long-standing cut-and-paste error meant we were using the wrong bits in the virtual address to select the access-permission field for 4K pages. The error has presumably not been noticed before because most guests don't make use of the ability to set the access permissions differently for each 1K subpage: if the guest gives the whole page the same access permissions it doesn't matter which of the 4 AP fields we select. (The whole issue is irrelevant for ARMv7 CPUs anyway because subpages aren't supported there.) Reported-by: Vivek Rai <Vivek.Rai@emulex.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392667690-8731-1-git-send-email-peter.maydell@linaro.org
* hw/arm/musicpal: Remove nonexistent CDTP2, CDTP3 registersPeter Maydell2014-02-261-4/+2
| | | | | | | | | | | | | The ethernet device in the musicpal only has two tx queues, but we modelled it with four CTDP registers, presumably a cut and paste from the rx queue registers. Since the tx_queue[] array is only 2 entries long this allowed a guest to overrun this buffer. Remove the nonexistent registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392737293-10073-1-git-send-email-peter.maydell@linaro.org Acked-by: Jan Kiszka <jan.kiszka@web.de> Cc: qemu-stable@nongnu.org
* hw/intc/exynos4210_combiner: Don't overrun output_irq array in initPeter Maydell2014-02-261-1/+1
| | | | | | | | | | | The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs; use the correct constant in the loop initializing our output sysbus IRQs so that we don't overrun the output_irq[] array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392659611-8439-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Andreas Färber <afaerber@suse.de> Cc: qemu-stable@nongnu.org
* target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS opsPeter Maydell2014-02-261-2/+2
| | | | | | | | Correct some obviously nonsensical bit manipulation spotted by Coverity when constructing the short-form PAR value for ATS operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392659525-8335-1-git-send-email-peter.maydell@linaro.org
* hw/timer/arm_timer: Avoid array overrun for bad addressesPeter Maydell2014-02-261-0/+2
| | | | | | | | | | | | | The integrator's timer read/write functions log an error for bad addresses in guest accesses, but were falling through and using an out of bounds array index rather than returning early. Fix this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1392647854-8067-4-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
* hw/net/stellaris_enet: Avoid unintended sign extensionPeter Maydell2014-02-261-1/+2
| | | | | | | | | | | | | Add a cast to avoid an unintended sign extension that would mean we returned 0xffffffff in the high 32 bits for an IA0 read if bit 31 in the MAC address was 1. (This is harmless since we'll only be doing 4 byte reads, but it could be confusing, so best avoided.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1392647854-8067-3-git-send-email-peter.maydell@linaro.org
* hw/misc/arm_sysctl: Fix bad boundary check on mb clock accessesPeter Maydell2014-02-261-2/+2
| | | | | | | | | | | | Fix incorrect use of sizeof() rather than ARRAY_SIZE() to guard accesses into the mb_clock[] array, which was allowing a malicious guest to overwrite the end of the array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1392647854-8067-2-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
* xilinx: Delete hw/include/xilinx.hPeter Crosthwaite2014-02-264-13/+1
| | | | | | | This is now obsolete - remove the header and all its inclusions. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* xilinx: Inline usages of xilinx_axi*_init()Peter Crosthwaite2014-02-262-38/+19
| | | | | | | | | Inline the only usage of each of xilinx_axiethernet_init and xilinx_axidma_init. Converts this init to at least a semi-recent QOM styling. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* xilinx: Inline usage of xilinx_ethlite_create()Peter Crosthwaite2014-02-262-20/+8
| | | | | | | | Inline the only usage. Converts this init to at least a semi-recent QOM styling. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* xilinx: Inline usages of xilinx_timer_create()Peter Crosthwaite2014-02-264-18/+20
| | | | | | | | Inline these usages. Converts these init to at least a semi-recent QOM styling. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* xilinx: Inline usages of xilinx_intc_create()Peter Crosthwaite2014-02-264-18/+18
| | | | | | | | Inline these usages. Converts these init to at least a semi-recent QOM styling. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* microblaze/ml605: Define macros for irq/memory mapsPeter Crosthwaite2014-02-261-3/+12
| | | | | | | | Define (missing) macros for the interrupt and memory maps for the sake of self documentation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* ppc/virtex_ml507: Define macros for irq/memory mapsPeter Crosthwaite2014-02-261-3/+11
| | | | | | | | Define macros for the interrupt and memory maps for the sake of self documentation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* microblaze/s3adsp_1800: Define macros for irq mapPeter Crosthwaite2014-02-261-1/+6
| | | | | | | Define macros for the interrupt map for the sake of self documentation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* modules: do not include gmodule-2.0 in static buildsPaolo Bonzini2014-02-252-1/+10
| | | | | | | | | | | | | | | | gmodule-2.0's pkg-config files include -Wl,--export-dynamic, which breaks static builds. It is a glib bug, but we need to support --static builds for the linux-user targets, and in the end all that is needed to fix this is: * outlaw --enable-modules --static, which makes little sense anyway * only include gmodule-2.0's cflags and ldflags if --enable-modules is specified on the command line. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1393346215-5636-1-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'remotes/spice/tags/pull-spice-3' into stagingPeter Maydell2014-02-251-1/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | qxl: add sanity check # gpg: Signature made Mon 24 Feb 2014 12:01:27 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/spice/tags/pull-spice-3: qxl: add sanity check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * qxl: add sanity checkGerd Hoffmann2014-02-241-1/+7
| | | | | | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* | Merge remote-tracking branch 'remotes/mdroth/qga-pull-2014-02-24' into stagingPeter Maydell2014-02-257-78/+132
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/mdroth/qga-pull-2014-02-24: qemu-ga: isa-serial support on Windows qga: Fix memory allocation pasto qga: Don't require 'time' argument in guest-set-time command qga: vss-win32: Fix interference with snapshot deletion by other VSS request qga: vss-win32: Fix interference with snapshot creation by other VSS requesters qga: vss-win32: Use NULL as an invalid pointer for OpenEvent and CreateEvent Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | qemu-ga: isa-serial support on WindowsMiki Mishael2014-02-232-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for isa-serial method for qemu-ga on Windows, Added -p command line parameter for serial port name specification, e.g. "-p COM15". Signed-off-by: Miki Mishael <mmishael@redhat.com> Signed-off-by: Dmitry Fleytman <dfleytma@redhat.com> *added default isa-serial path to help output Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| * | qga: Fix memory allocation pastoMarkus Armbruster2014-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qmp_guest_file_seek() allocates memory for a GuestFileRead object instead of the GuestFileSeek object it actually uses. Harmless, because the GuestFileRead is slightly larger. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| * | qga: Don't require 'time' argument in guest-set-time commandMichal Privoznik2014-02-233-29/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the description to the guest-set-time states, the command is there to ease time synchronization after resume. If guest was suspended for longer period of time, its system time can go off so badly, that even NTP refuses to set it. That's why the command was invented: to give users chance to set the time (not necessarily 100% correct). However, there's is no real need for us to require users to pass an arbitrary time. Especially if we can read the correct value from RTC (boiling down to reading host's time). Hence this commit enables logic: guest-set-time() == guest-set-time($now_from_rtc) Signed-off-by: Michal Privoznik <mprivozn@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| * | qga: vss-win32: Fix interference with snapshot deletion by other VSS requestTomoki Sekiyama2014-02-231-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a VSS requester such as vshadow.exe or diskshadow.exe requests to delete snapshots, qemu-ga VSS provider's DeleteSnapshots() is also called and returns E_NOTIMPL, that makes the deletion fail. To avoid this issue, return S_OK and set values that represent no snapshots are deleted by qemu-ga VSS provider. Signed-off-by: Tomoki Sekiyama <tomoki.sekiyama@hds.com> Reviewed-by: Gal Hammer <ghammer@redhat.com> Reviewed-by: Yan Vugenfirer <yvugenfi@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| * | qga: vss-win32: Fix interference with snapshot creation by other VSS requestersTomoki Sekiyama2014-02-232-27/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a VSS requester such as vshadow.exe or diskshadow.exe requests to create disk snapshots, Windows may choose qemu-ga VSS provider if it is only provider registered on the system. However, because it provides only a function to freeze the filesystem, the snapshotting fails. This patch adds a check into CQGAVssProvider::IsVolumeSupported() to reject the request from other VSS requesters, so that the other provider is chosen. The check of requester is done by confirming event channels between qemu-ga's requester and provider established. To ensure that the events are initialized when CQGAVssProvider::IsVolumeSupported() is called, it moves the initialization earlier. Signed-off-by: Tomoki Sekiyama <tomoki.sekiyama@hds.com> Reviewed-by: Gal Hammer <ghammer@redhat.com> Reviewed-by: Yan Vugenfirer <yvugenfi@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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