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* arm: SoC model for Calxeda HighbankRob Herring2012-01-262-0/+331
| | | | | | | | Adds support for Calxeda's Highbank SoC. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm_boot: support board IDs more than 16 bits widePeter Maydell2012-01-261-6/+5
| | | | | | | | | | Support passing a board ID value to the kernel in r1 that is more than 16 bits wide. This is needed to pass the '-1 == invalid' value for boards which only support device tree booting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
* arm: add secondary cpu boot callbacks to arm_boot.cMark Langsdorf2012-01-262-11/+60
| | | | | | | | | | Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(), to allow platforms more control of how secondary CPUs are brought up. The new functions default to NULL and aren't called unless they are populated so there are no changes to existing platform models. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* ahci: add support for non-PCI based controllersRob Herring2012-01-261-0/+44
| | | | | | | | | Add support for ahci on sysbus. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Add xgmac ethernet modelRob Herring2012-01-262-0/+422
| | | | | | | | | | | | | | | This adds very basic support for the xgmac ethernet core. Missing things include: - statistics counters - WoL support - rx checksum offload - chained descriptors (only linear descriptor ring) - broadcast and multicast handling Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* vga: compile cirrus_vga in hwlibBlue Swirl2012-01-253-4/+1
| | | | | | | | Remove target dependencies and compile Cirrus VGA in hwlib. Address masking can be removed since memory API handles that now. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* memory: change dirty setting APIs to take a sizeBlue Swirl2012-01-2512-48/+48
| | | | | | | Instead of each target knowing or guessing the guest page size, just pass the desired size of dirtied memory area. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* memory: fix dirty mask function length handlingBlue Swirl2012-01-251-5/+6
| | | | | | | | Fix handling of cases like start = 0xfff, length = 2. Change length to ram_addr_t to handle larger lengths. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* vga: fix -nodefaults -device VGABlue Swirl2012-01-251-0/+1
| | | | | | | Flag -nodefaults should also imply no VGA. This was broken in a369da5f31ddbdeb32a7f76622e480d3995fbb00. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* hyperv: fix build on non-KVM hostsBlue Swirl2012-01-232-2/+4
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori2012-01-2340-593/+1902
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * qemu-kvm/uq/master: kvm: Activate in-kernel irqchip support kvm: x86: Add user space part for in-kernel IOAPIC kvm: x86: Add user space part for in-kernel i8259 kvm: x86: Add user space part for in-kernel APIC kvm: x86: Establish IRQ0 override control kvm: Introduce core services for in-kernel irqchip support memory: Introduce memory_region_init_reservation ioapic: Factor out base class for KVM reuse ioapic: Drop post-load irr initialization i8259: Factor out base class for KVM reuse i8259: Completely privatize PicState apic: Open-code timer save/restore apic: Factor out base class for KVM reuse apic: Introduce apic_report_irq_delivered apic: Inject external NMI events via LINT1 apic: Stop timer on reset kvm: Move kvmclock into hw/kvm folder msi: Generalize msix_supported to msi_supported hyper-v: initialize Hyper-V CPUID leaves. hyper-v: introduce Hyper-V support infrastructure. Conflicts: Makefile.target Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
| * kvm: Activate in-kernel irqchip supportJan Kiszka2012-01-192-1/+8
| | | | | | | | | | | | | | | | Make the basic in-kernel irqchip support selectable via -machine ...,kernel_irqchip=on. Leave it off by default until it can fully replace user space models. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: x86: Add user space part for in-kernel IOAPICJan Kiszka2012-01-193-2/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | This introduces the KVM-accelerated IOAPIC model 'kvm-ioapic' and extends the IRQ routing setup by the 0->2 redirection when needed. The kvm-ioapic model has a property that allows to define its GSI base for injecting interrupts into the kernel model. This will allow to disentangle PIC and IOAPIC pins for chipsets that support more sophisticated IRQ routes than the PIIX3. So far the base is kept at 0, i.e. PIC and IOAPIC share pins 0..15. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: x86: Add user space part for in-kernel i8259Jan Kiszka2012-01-194-5/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the alternative 'kvm-i8259' device model that exploits KVM in-kernel acceleration. The PIIX3 initialization code is furthermore extended by KVM specific IRQ route setup. GSI injection differs in KVM mode from the user space model. As we can dispatch ISA-range IRQs to both IOAPIC and PIC inside the kernel, we do not need to inject them separately. This is reflected by a KVM-specific GSI handler. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: x86: Add user space part for in-kernel APICJan Kiszka2012-01-195-6/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | This introduces the alternative APIC device which makes use of KVM's in-kernel device model. External NMI injection via LINT1 is emulated by checking the current state of the in-kernel APIC, only injecting a NMI into the VCPU if LINT1 is unmasked and configured to DM_NMI. MSI is not yet supported, so we disable this when the in-kernel model is in use. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: x86: Establish IRQ0 override controlJan Kiszka2012-01-196-3/+14
| | | | | | | | | | | | | | | | KVM is forced to disable the IRQ0 override when we run with in-kernel irqchip but without IRQ routing support of the kernel. Set the fwcfg value correspondingly. This aligns us with qemu-kvm. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: Introduce core services for in-kernel irqchip supportJan Kiszka2012-01-193-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the basic infrastructure to active in-kernel irqchip support, inject interrupts into these models, and maintain IRQ routes. Routing is optional and depends on the host arch supporting KVM_CAP_IRQ_ROUTING. When it's not available on x86, we looe the HPET as we can't route GSI0 to IOAPIC pin 2. In-kernel irqchip support will once be controlled by the machine property 'kernel_irqchip', but this is not yet wired up. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * memory: Introduce memory_region_init_reservationJan Kiszka2012-01-192-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | Introduce a memory region type that can reserve I/O space. Such regions are useful for modeling I/O that is only handled outside of QEMU, i.e. in the context of an accelerator like KVM. Any access to such a region from QEMU is a bug, but could theoretically be triggered by guest code (DMA to reserved region). So only warning about such events once, then ignore them. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * ioapic: Factor out base class for KVM reuseJan Kiszka2012-01-194-115/+218
| | | | | | | | | | | | | | | | Split up the IOAPIC analogously to APIC and i8259. KVM will share the IOAPICCommonState, the vmstate, reset logic and certain init parts with the user space model. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * ioapic: Drop post-load irr initializationJan Kiszka2012-01-191-12/+0
| | | | | | | | | | | | | | | | | | As all devices undergo a reset prior to vmloa, and the reset value of irr is 0, we do not need to do this clearing for older vmstates explicitly. Dropping this redundant code will also make KVM integration a bit simpler. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * i8259: Factor out base class for KVM reuseJan Kiszka2012-01-194-129/+254
| | | | | | | | | | | | | | | | | | | | | | Analogously to the APIC, we will reuse some parts of the user space i8259 model for KVM. The base class provides a common device state, the vmstate, the property list, a reset core and some shared init bits. This also introduces a common helper to instantiate a single i8259 chip from the cascade-creating i8259_init function. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * i8259: Completely privatize PicStateJan Kiszka2012-01-192-10/+14
| | | | | | | | | | | | | | Use DeviceState instead of PicState in the public i8259 API. This is cleaner and allows to reorganize the PIC data structures for KVM reuse. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * apic: Open-code timer save/restoreJan Kiszka2012-01-193-20/+67
| | | | | | | | | | | | | | | | | | | | | | | | To enable migration between accelerated and non-accelerated APIC models, we will need to handle the timer saving and restoring specially and can no longer rely on the automatics of VMSTATE_TIMER. Specifically, accelerated model will not start any QEMUTimer. This patch therefore factors out the generic bits into apic_next_timer and use a post-load callback to implemented model-specific logic. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * apic: Factor out base class for KVM reuseJan Kiszka2012-01-195-299/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The KVM in-kernel APIC model will reuse parts of the user space model while providing the same frontend view to guest and most management interfaces. Factor out an APIC base class to encapsulate those parts that will be shared by user space and KVM model. This class offers callback hooks for init, base/tpr setting, and the external NMI delivery that will be set via APICCommonInfo structure and implemented specifically in the subclasses. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * apic: Introduce apic_report_irq_deliveredJan Kiszka2012-01-193-4/+10
| | | | | | | | | | | | | | The in-kernel i8259 and IOAPIC backends for KVM will need this, so encapsulate the shared bits. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * apic: Inject external NMI events via LINT1Jan Kiszka2012-01-193-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | On real hardware, NMI button events are injected via the LINT1 line of the APICs. E.g. kdump expect this wiring and gets upset if the per-APIC LINT1 mask is not respected, i.e. if NMIs are injected to VCPUs that should not receive them. Change the APIC emulation code to reflect this. Based on qemu-kvm patch by Lai Jiangshan. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Reported-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * apic: Stop timer on resetJan Kiszka2012-01-191-0/+2
| | | | | | | | | | | | | | | | All LVTs are masked on reset, so the timer becomes ineffective. Letting it tick nevertheless is harmless, but will at least create a spurious trace event. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * kvm: Move kvmclock into hw/kvm folderJan Kiszka2012-01-195-5/+6
| | | | | | | | | | | | | | More KVM-specific devices will come, so let's start with moving the kvmclock into a dedicated folder. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * msi: Generalize msix_supported to msi_supportedJan Kiszka2012-01-195-9/+16
| | | | | | | | | | | | | | | | Rename msix_supported to msi_supported and control MSI and MSI-X activation this way. That was likely to original intention for this flag, but MSI support came after MSI-X. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * hyper-v: initialize Hyper-V CPUID leaves.Vadim Rozenfeld2012-01-191-2/+63
| | | | | | | | Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
| * hyper-v: introduce Hyper-V support infrastructure.Vadim Rozenfeld2012-01-194-0/+123
| | | | | | | | | | | | [Jan: fix build with CONFIG_USER_ONLY] Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* | Merge remote-tracking branch 'afaerber/prep-up' into stagingAnthony Liguori2012-01-239-135/+553
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * afaerber/prep-up: prep: Use i82378 PCI->ISA bridge for 'prep' machine prep: Add i82378 PCI-to-ISA bridge emulation prep: Add i82374 DMA emulation MAINTAINERS: Add PCI host bridge files to PReP machine prep: qdev'ify Raven host bridge (SysBus) prep_pci: Update I/O to MemoryRegion ops prep_pci: Simplify I/O endianness prep: qdev'ify Raven host bridge (PCIDevice) prep: Use ISA m48t59 prep: Fix offset of BIOS MemoryRegion
| * | prep: Use i82378 PCI->ISA bridge for 'prep' machineAndreas Färber2012-01-201-48/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Speaker I/O, ISA bus, i8259 PIC, RTC and DMA are no longer set up individually by the machine. Effectively, no-op speaker I/O is replaced by pcspk; PIT and i82374 DMA are introduced. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Remove related dead, alternative code. Wire up PCI host bridge IRQs via GPIO-in IRQs of PCI->ISA bridge. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Alexander Graf <agraf@suse.de> Cc: Jan Kiszka <jan.kiszka@siemens.com>
| * | prep: Add i82378 PCI-to-ISA bridge emulationAndreas Färber2012-01-204-0/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare Intel 82378 emulation for use by PReP platforms. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Create ISA bus in this device (suggested by Markus). Rebase onto Memory API, mark memory ops as Little Endian. Add VMState. Provide access to i8259 IRQs via qdev GPIOs. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Markus Armbruster <armbru@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: Jan Kiszka <jan.kiszka@siemens.com>
| * | prep: Add i82374 DMA emulationAndreas Färber2012-01-203-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare Intel 82374 emulation for use by Intel 82378 PCI->ISA bridge. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Confine to CONFIG_I82374. Add VMState. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | MAINTAINERS: Add PCI host bridge files to PReP machineAndreas Färber2012-01-201-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Andreas Färber <andreas.faerber@web.de> Acked-by: Alexander Graf <agraf@suse.de>
| * | prep: qdev'ify Raven host bridge (SysBus)Andreas Färber2012-01-203-38/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop pci_prep_init() in favor of extended device state. Inspired by patches from Hervé and Alex. Assign the 4 IRQs from the board after device instantiation. This moves the knowledge out of prep_pci and allows for future machines with different IRQ wiring (IBM 40P). Suggested by Alex. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de> Cc: Hervé Poussineau <hpoussin@reactos.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Anthony Liguori <aliguori@us.ibm.com>
| * | prep_pci: Update I/O to MemoryRegion opsAndreas Färber2012-01-201-38/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert to new-style read/write callbacks. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Alexander Graf <agraf@suse.de> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Avi Kivity <avi@redhat.com> Cc: Benoît Canet <benoit.canet@gmail.com>
| * | prep_pci: Simplify I/O endiannessAndreas Färber2012-01-201-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prep PowerPC CPU is Big Endian. An explicit byte swap therefore effectively becomes Little Endian. Remove explicit byte swaps and mark as Little Endian. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de> Cc: Michael S. Tsirkin <mst@redhat.com>
| * | prep: qdev'ify Raven host bridge (PCIDevice)Andreas Färber2012-01-201-9/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move initialization of vendor ID, etc. to PCIDeviceInfo. Introduce VMState. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de> Cc: Hervé Poussineau <hpoussin@reactos.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Anthony Liguori <aliguori@us.ibm.com>
| * | prep: Use ISA m48t59Andreas Färber2012-01-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies the code later when the i8259 moves to the i82378 PCI->ISA bridge and happens to fix a SysBus m48t59 io_base issue introduced by commit 0fb56ffc5edd66f12ccfc0d71af5f9c79c0a2612 (m48t59: drop obsolete address base arithmetic). Suggested by Hervé and Jan. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Hervé Poussineau <hpoussin@reactos.org> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Blue Swirl <blauwirbel@gmail.com>
| * | prep: Fix offset of BIOS MemoryRegionAndreas Färber2012-01-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 0c90c52fab5ea92d7f12b29bfe26a7cd75d9efcb (ppc_prep: convert to memory API) OHW was "Trying to execute code outside RAM or ROM at 0xfff00700". The BIOS MemoryRegion is created with a fixed size of 1 MiB. Ensure that the full size can be accessed since the exception vectors are located at 0xfff00000 and the BIOS may want to use them. It thereby no longer depends on the actual BIOS binary size. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Avi Kivity <avi@redhat.com> Cc: Alexander Graf <agraf@suse.de>
* | | e1000: bounds packet size against buffer sizeAnthony Liguori2012-01-231-0/+3
| | | | | | | | | | | | | | | | | | | | | Otherwise we can write beyond the buffer and corrupt memory. This is tracked as CVE-2012-0029. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* | | target-sparc: Fix mixup of uint64 and uint64_tAndreas Färber2012-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 793a137a41ad4125011c7022cf16a1baa40a5ab6 (target-sparc: Implement BMASK/BSHUFFLE.) introduced a stray usage of softfloat uint64 type. Use uint64_t instead. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Richard Henderson <rth@twiddle.net> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | | sga: fix copypastaBlue Swirl2012-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | Fix the name of the init function. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | | vga: make Cirrus ISA device optionalBlue Swirl2012-01-2216-23/+54
| | | | | | | | | | | | | | | Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | | vga: improve VGA logicBlue Swirl2012-01-2212-64/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve VGA selection logic, push check for device availabilty to vl.c. Create the devices at board level unconditionally. Remove now unused pci_try_create*() functions. Make PCI VGA devices optional. Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | | grackle_pci: Clean up qdev namesAndreas Färber2012-01-211-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename SysBus device from 'grackle' to 'grackle-pcihost' to resolve a name conflict. Also mark both devices as no_user. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Alexander Graf <agraf@suse.de> Cc: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | | MAINTAINERS: Add PCI-PCI bridge to New World Mac machineAndreas Färber2012-01-211-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* | | PPC: Pseries: Check for PCI boundariesAlexander Graf2012-01-211-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We call pci_host_config_{read,write}_common() which perform PCI config accesses. However they don't do all limit checking the way we expect it to. So let's introduce a small wrapper around them, making them behave the way we would without touching generic code. This patch is based on a patch by David Gibson which put this logic into the generic code. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
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