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* disas/libvixl: Update to upstream VIXL 1.7Peter Maydell2015-02-0511-210/+537
| | | | | | | | | Update our copy of libvixl to upstream's 1.7 release. This includes upstream's fix for the issue we had a local patch for in commit 94cc44a9e. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422274779-13359-2-git-send-email-peter.maydell@linaro.org
* target-arm: Fix brace style in reindented codePeter Maydell2015-02-051-13/+23
| | | | | | | | | This patch fixes the brace style in the code reindented in the previous commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Reindent ancient page-table-walk codePeter Maydell2015-02-051-96/+96
| | | | | | | | | | | | A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Use mmu_idx in get_phys_addr()Peter Maydell2015-02-051-51/+163
| | | | | | | | | | | | Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
* target-arm: Pass mmu_idx to get_phys_addr()Peter Maydell2015-02-051-14/+96
| | | | | | | | | | | | | Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Split AArch64 cases out of ats_write()Peter Maydell2015-02-051-7/+26
| | | | | | | | | | | | | Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Don't define any MMU_MODE*_SUFFIXesPeter Maydell2015-02-051-2/+0
| | | | | | | | | | | target-arm doesn't use any of the MMU-mode specific cpu ldst accessor functions. Suppress their generation by not defining any of the MMU_MODE*_SUFFIX macros. ("user" and "kernel" are too simplistic as descriptions of indexes 0 and 1 anyway.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell2015-02-052-3/+42
| | | | | | | | | | | | | | | The MMU index to use for unprivileged loads and stores is more complicated than we currently implement: * for A64, it should be "if at EL1, access as if EL0; otherwise access at current EL" * for A32/T32, it should be "if EL2, UNPREDICTABLE; otherwise access as if at EL0". In both cases, if we want to make the access for Secure EL0 this is not the same mmu_idx as for Non-Secure EL0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
* target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell2015-02-055-29/+102
| | | | | | | | | | | | | | | | | | | | | | | | We currently claim that for ARM the mmu_idx should simply be the current exception level. However this isn't actually correct -- secure EL0 and EL1 should have separate indexes from non-secure EL0 and EL1 since their VA->PA mappings may differ. We also will want an index for stage 2 translations when we properly support EL2. Define and document all seven mmu index values that we require, and pass the mmu index in the TB flags rather than exception level or priv/user bit. This change doesn't update the get_phys_addr() code, so our page table walking still assumes a simplistic "user or priv?" model for the moment. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> --- This leaves some odd gaps in the TB flags usage. I will circle back and clean this up later (including moving the other common flags like the singlestep ones to the top of the flags word), but I didn't want to bloat this patchseries further.
* target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STTPeter Maydell2015-02-051-1/+1
| | | | | | | | | | | | | | | | | | The LDT/STT (load/store unprivileged) instruction decode was using the wrong MMU index value. This meant that instead of these insns being "always access as if user-mode regardless of current privilege" they were "always access as if kernel-mode regardless of current privilege". This went unnoticed because AArch64 Linux doesn't use these instructions. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> --- I'm not counting this as a security issue because I'm assuming nobody treats TCG guests as a security boundary (certainly I would not recommend doing so...)
* target-arm: Make arm_current_el() return sensible values for M profilePeter Maydell2015-02-051-0/+4
| | | | | | | | | | | | Although M profile doesn't have the same concept of exception level as A profile, it does have a notion of privileged versus not, which we currently track in the privmode TB flag. Support returning this information if arm_current_el() is called on an M profile core, so that we can identify the correct MMU index to use (and put the MMU index in the TB flags) without having to special-case M profile. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
* cpu_ldst.h: Allow NB_MMU_MODES to be 7Peter Maydell2015-02-051-3/+25
| | | | | | | | | | Support guest CPUs which need 7 MMU index values. Add a comment about what would be required to raise the limit further (trivial for 8, TCG backend rework for 9 or more). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* hw/arm/virt: explain device-to-transport mapping in create_virtio_devices()Laszlo Ersek2015-02-051-4/+33
| | | | | | | Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-id: 1422592273-4432-1-git-send-email-lersek@redhat.com [PMM: added note recommending UUIDs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: check that LSB <= MSB in BFI instructionKirill Batuzov2015-02-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The documentation states that if LSB > MSB in BFI instruction behaviour is unpredictable. Currently QEMU crashes because of assertion failure in this case: tcg/tcg-op.h:2061: tcg_gen_deposit_i32: Assertion `len <= 32' failed. While assertion failure may meet the "unpredictable" definition this behaviour is undesirable because it allows an unprivileged guest program to crash the emulator with the OS and other programs. This patch addresses the issue by throwing illegal instruction exception if LSB > MSB. Only ARM decoder is affected because Thumb decoder already has this check in place. To reproduce issue run the following program int main(void) { asm volatile (".long 0x07c00c12" :: ); return 0; } compiled with gcc -marm -static badop_arm.c -o badop_arm Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Squash input denormals in FRECPS and FRSQRTSPeter Maydell2015-02-051-0/+12
| | | | | | | | | | | The helper functions for FRECPS and FRSQRTS have special case handling that includes checks for zero inputs, so squash input denormals if necessary before those checks. This fixes incorrect output when the FPCR DZ bit is set to enable squashing of input denormals. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
* Fix FMULX not squashing denormalized inputs when FZ is set.Xiangyu Hu2015-02-051-0/+6
| | | | | | | | | | | | | | While FMULX returns a 2.0f float when two operators are infinity and zero, those operators should be unpacked from raw inputs first. Inconsistent cases would occur when operators are denormalized floats in flush-to-zero mode. A wrong codepath will be entered and 2.0f will not be returned without this patch. Fix by checking whether inputs need to be flushed before running into different codepaths. Signed-off-by: Xiangyu Hu <libhu.so@gmail.com> Message-id: 1422459650-12490-1-git-send-email-libhu.so@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add checks that cpreg raw accesses are handledPeter Maydell2015-02-051-0/+31
| | | | | | | | | | | | Add assertion checking when cpreg structures are registered that they either forbid raw-access attempts or at least make an attempt at handling them. Also add an assert in the raw-accessor-of-last-resort, to avoid silently doing a read or write from offset zero, which is actually AArch32 CPU register r0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422282372-13735-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
* target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell2015-02-052-108/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1422282372-13735-2-git-send-email-peter.maydell@linaro.org [PMM: changed ARM_CP_NO_MIGRATE to ARM_CP_ALIAS on new SP_EL1 and SP_EL2 reginfo stanzas since there was a (semantic) merge conflict with the patchset that added those]
* target-arm: Add missing SP_ELx register definitionGreg Bellows2015-02-051-0/+8
| | | | | | | | | Added CP register definitions for SP_EL1 and SP_EL2. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422029835-4696-5-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Change reset to highest available ELGreg Bellows2015-02-052-3/+28
| | | | | | | | | | Update to arm_cpu_reset() to reset into the highest available exception level based on the set ARM features. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422029835-4696-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add extended RVBAR supportGreg Bellows2015-02-051-6/+25
| | | | | | | | | | | Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers point to the same location and only the highest EL version exists at any one time. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422029835-4696-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix RVBAR_EL1 register encodingGreg Bellows2015-02-051-1/+1
| | | | | | | | | Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1 Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422029835-4696-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target_arm: Parameterise the irq lines for armv7m_initAlistair Francis2015-02-053-6/+9
| | | | | | | | | | | This patch allows the board to specifiy the number of NVIC interrupt lines when using armv7m_init. Signed-off-by: Alistair Francis <alistair23@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5a0b0fcc778df0340899f488053acc9493679e03.1422077994.git.alistair23@gmail.com [PMM: removed stale FIXME comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target_arm: Remove memory region init from armv7m_initAlistair Francis2015-02-053-36/+24
| | | | | | | | | | This patch moves the memory region init code from the armv7m_init function to the stellaris_init function Signed-off-by: Alistair Francis <alistair23@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 4836be7e1d708554d6eb0bc639dc2fbf7dac0458.1422077994.git.alistair23@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2015-02-05' ↵Peter Maydell2015-02-057-71/+58
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging qmp hmp balloon: Cleanups around error reporting # gpg: Signature made Thu 05 Feb 2015 07:15:11 GMT using RSA key ID EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" * remotes/armbru/tags/pull-error-2015-02-05: balloon: Eliminate silly QERR_ macros balloon: Factor out common "is balloon active" test balloon: Inline qemu_balloon(), qemu_balloon_status() qmp: Eliminate silly QERR_COMMAND_NOT_FOUND macro qmp: Simplify recognition of capability negotiation command qmp: Clean up qmp_query_spice() #ifndef !CONFIG_SPICE dummy hmp: Compile hmp_info_spice() only with CONFIG_SPICE qmp hmp: Improve error messages when SPICE is not in use qmp hmp: Factor out common "using spice" test Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * balloon: Eliminate silly QERR_ macrosMarkus Armbruster2015-01-292-8/+4
| | | | | | | | | | | | | | | | | | | | | | The QERR_ macros are leftovers from the days of "rich" error objects. They're used with error_set() and qerror_report(), and expand into the first *two* arguments. This trickiness has become pointless. Clean up the balloon ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
| * balloon: Factor out common "is balloon active" testMarkus Armbruster2015-01-291-14/+15
| | | | | | | | | | Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
| * balloon: Inline qemu_balloon(), qemu_balloon_status()Markus Armbruster2015-01-291-26/+10
| | | | | | | | | | | | | | | | ... and simplify a bit. Permits factoring out common error checks in the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
| * qmp: Eliminate silly QERR_COMMAND_NOT_FOUND macroMarkus Armbruster2015-01-293-5/+4
| | | | | | | | | | | | | | | | | | | | The QERR_ macros are leftovers from the days of "rich" error objects. They're used with error_set() and qerror_report(), and expand into the first *two* arguments. This trickiness has become pointless. Clean this one up. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
| * qmp: Simplify recognition of capability negotiation commandMarkus Armbruster2015-01-291-8/+3
| | | | | | | | | | Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
| * qmp: Clean up qmp_query_spice() #ifndef !CONFIG_SPICE dummyMarkus Armbruster2015-01-291-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | QMP command query-spice exists only #ifdef CONFIG_SPICE. Due to QAPI limitations, we need a dummy function anyway, but it's unreachable. Our current dummy function goes out of its way to produce the exact same error as the QMP core does for unknown commands. Cute, but both unclean and unnecessary. Replace by straight abort(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
| * hmp: Compile hmp_info_spice() only with CONFIG_SPICEMarkus Armbruster2015-01-291-0/+2
| | | | | | | | | | | | | | | | | | | | It's dead code when CONFIG_SPICE is off. If it wasn't, it would crash dereferencing the null pointer returned by the qmp_query_spice() dummy in qmp.c. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
| * qmp hmp: Improve error messages when SPICE is not in useMarkus Armbruster2015-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7572150 adopted QERR_DEVICE_NOT_ACTIVE for the purpose, probably because adding another error seemed cumbersome overkill. Produces "No spice device has been activated", which is awkward. We've since abandoned our quest for "rich" error objects. Time to undo the damage to this error message. Replace it by "SPICE is not in use". Keep the stupid DeviceNotActive ErrorClass for compatibility, even though Libvirt doesn't use it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
| * qmp hmp: Factor out common "using spice" testMarkus Armbruster2015-01-293-10/+16
| | | | | | | | | | | | | | | | | | Into qemu_using_spice(). For want of a better place, put it next the existing monitor command handler dummies in qemu-spice.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20150204.0' ↵Peter Maydell2015-02-052-1/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging VFIO fixes: - Fix wrong initializer (Chen Fan) - Add missing object_unparent (Alex Williamson) # gpg: Signature made Wed 04 Feb 2015 18:49:24 GMT using RSA key ID 3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" * remotes/awilliam/tags/vfio-update-20150204.0: vfio-pci: Fix missing unparent of dynamically allocated MemoryRegion vfio: fix wrong initialize vfio_group_list Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | vfio-pci: Fix missing unparent of dynamically allocated MemoryRegionAlex Williamson2015-02-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d8d95814609e added explicit object_unparent() calls for dynamically allocated MemoryRegions. The VFIOMSIXInfo structure also contains such a MemoryRegion, covering the mmap'd region of a PCI BAR above the MSI-X table. This structure is freed as part of the class exit function and therefore also needs an explicit object_unparent(). Failing to do this results in random segfaults due to fields within the structure, often the class pointer, being reclaimed and corrupted by the time object_finalize_child_property() is called for the object. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Cc: qemu-stable@nongnu.org # 2.2
| * | vfio: fix wrong initialize vfio_group_listChen Fan2015-02-041-1/+1
|/ / | | | | | | | | Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* | Merge remote-tracking branch 'remotes/rth/tags/pull-tg-s390-20150203' into ↵Peter Maydell2015-02-037-60/+140
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging s390 translator bug fixes # gpg: Signature made Tue 03 Feb 2015 20:39:15 GMT using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tg-s390-20150203: target-s390x: fix and optimize slb* and slbg* computation of carry/borrow flag target-s390x: support OC and NC in the EX instruction disas/s390.c: Remove unused variables target-s390x: Mark check_privileged() as !CONFIG_USER_ONLY target-s390: Implement ECAG target-s390: Implement LURA, LURAG, STURG target-s390: Fix STURA target-s390: Fix STIDP target-s390: Implement EPSW target-s390: Implement SAM specification exception Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-s390x: fix and optimize slb* and slbg* computation of carry/borrow flagTorbjorn Granlund2015-02-031-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the bug with borrow_in being set incorrectly, but it also simplifies the logic to be much more plain, improving speed. It fixes both the 32-bit SLB* and 64-bit SLBG*. The SLBG* change has been well-tested. I haven't tested the SLB* change explicitly, but the code was copy-pasted from the tested code. The error of these functions' current implementations would not likely be triggered by compiler-generated code, since the only error was in the state of the carry/borrow flag. Compilers rarely generate an instruction sequence such as carry-set -> carry-set-and-use -> carry-use. (With Paolo's fix and mine, there are still a couple of failures from GMP's testsuite, but they are almost surely due to incorrect code generation from gcc 4.9. But since this gcc is running under qemu, it might be qemu bugs. I intend to investigate this.) Signed-off-by: Torbjorn Granlund <torbjorng@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390x: support OC and NC in the EX instructionPaolo Bonzini2015-02-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to run the GMP testsuite. Reported-by: Torbjorn Granlund <torbjorng@google.com> Tested-by: Torbjorn Granlund <torbjorng@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | disas/s390.c: Remove unused variablesPeter Maydell2015-02-031-35/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variables s390_opformats and s390_num_opformats are unused and provoke clang warnings: disas/s390.c:849:33: warning: variable 's390_opformats' is not needed and will not be emitted [-Wunneeded-internal-declaration] static const struct s390_opcode s390_opformats[] = ^ disas/s390.c:875:18: warning: unused variable 's390_num_opformats' [-Wunused-const-variable] static const int s390_num_opformats = ^ Delete them, since QEMU doesn't use them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 1419373100-17690-3-git-send-email-peter.maydell@linaro.org Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390x: Mark check_privileged() as !CONFIG_USER_ONLYPeter Maydell2015-02-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function check_privileged() is only used in the softmmu configs; wrap it in an #ifndef CONFIG_USER_ONLY to avoid clang warnings on the linux-user builds. [rth: Remove inline marker too; it was only there to prevent exactly this warning in GCC.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 1419373100-17690-2-git-send-email-peter.maydell@linaro.org Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390: Implement ECAGRichard Henderson2015-02-032-0/+9
| | | | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390: Implement LURA, LURAG, STURGRichard Henderson2015-02-034-0/+55
| | | | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390: Fix STURARichard Henderson2015-02-031-1/+1
| | | | | | | | | | | | | | | | | | We were storing 16 bits instead of 32. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390: Fix STIDPRichard Henderson2015-02-032-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | The implementation had been incomplete, as we did not store the machine type. Note that the machine_type member is still unset during initialization, so this has no effect yet. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390: Implement EPSWRichard Henderson2015-02-032-0/+20
| | | | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-s390: Implement SAM specification exceptionRichard Henderson2015-02-032-8/+31
| | | | | | | | | | | | | | | | | | | | | Also, these are user-mode instructions; allow their use in CONFIG_USER_ONLY. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20150203' into stagingPeter Maydell2015-02-0310-44/+52
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some bugfixes and cleanups for s390x, both in the new pci code and in old code. # gpg: Signature made Tue 03 Feb 2015 13:01:04 GMT using RSA key ID C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" * remotes/cohuck/tags/s390x-20150203: pc-bios/s390-ccw: update binary pc-bios/s390-ccw: fix sparse warnings s390x/ipl: Improved code indentation in s390_ipl_init() s390x/kvm: unknown DIAGNOSE code should give a specification exception s390x/kvm: Fix diag-308 register decoding s390x/pci: fix dma notifications in rpcit instruction s390x/pci: check for invalid function handle s390x/pci: avoid sign extension in stpcifc s390: Plug memory leak on s390_pci_generate_event() error path Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | pc-bios/s390-ccw: update binaryCornelia Huck2015-02-031-0/+0
| | | | | | | | | | | | | | | | Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
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