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* ppc: First cut implementation of -cpu hostDavid Gibson2011-10-304-1/+33
| | | | | | | | | | | | | | | | | | | | | For convenience with kvm, x86 allows the user to specify -cpu host on the qemu command line, which means make the guest cpu the same as the host cpu. This patch implements the same option for ppc targets. For now, this just read the host PVR (Processor Version Register) and selects one of our existing CPU specs based on it. This means that the option will not work if the host cpu is not supported by TCG, even if that wouldn't matter for use under kvm. In future, we can extend this in future to override parts of the cpu spec based on information obtained from the host (via /proc/cpuinfo, the host device tree, or explicit KVM calls). That will let us handle cases where the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated CPU. With appropriate annotation of the CPU specs we'll also then be able to use host cpus under kvm even when there isn't a matching full TCG model. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Remove broken partial PVR matchingDavid Gibson2011-10-301-30/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ppc target contains a ppc_find_by_pvr() function, which looks up a CPU spec based on a PVR (that is, based on the value in the target cpu's Processor Version Register). PVR values contain information on both the cpu model (upper 16 bits, usually) and on the precise revision (low 16 bits, usually). ppc_find_by_pvr, as well as making exact PVR matches, attempts to find "close" PVR matches, when we don't have a CPU spec for the exact revision specified. This sounds like a good idea, execpt that the current logic is completely nonsensical. It seems to assume CPU families are subdivided bit by bit in the PVR in a way they just aren't. Specifically, it requires a match on all bits of the specified pvr up to the last non-zero bit. This has the bizarre effect that when the low bits are simply a sequential revision number (a common though not universal pattern), then odd specified revisions must be matched exactly, whereas even specified revisions will also match the next odd revision, likewise for powers of 4, 8 and so forth. To correctly do inexact matching we'd need to re-organize the table of CPU specs to include a mask showing what PVR range the spec is compatible with (similar to the cputable code in the Linux kernel). For now, just remove the bogosity by only permitting exact PVR matches. That at least makes the matching simple and consistent. If we need inexact matching we can add the necessary per-subfamily masks later. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Update SLOF firmware imageDavid Gibson2011-10-303-1/+1
| | | | | | | | | | This patch is a general update to the SLOF firmware image used on the pseries machine. This doesn't contain updates for specific features but contains a number of bugfixes and enhancements in the main SLOF tree from Thomas Huth. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Add device tree properties for VMX/VSX and DFP under kvmDavid Gibson2011-10-303-0/+39
| | | | | | | | | | | | | | | | | | | | | Sufficiently recent PAPR specifications define properties "ibm,vmx" and "ibm,dfp" on the CPU node which advertise whether the VMX vector extensions (or the later VSX version) and/or the Decimal Floating Point operations from IBM's recent POWER CPUs are available. Currently we do not put these in the guest device tree and the guest kernel will consequently assume they are not available. This is good, because they are not supported under TCG. VMX is similar enough to Altivec that it might be trivial to support, but VSX and DFP would both require significant work to support in TCG. However, when running under kvm on a host which supports these instructions, there's no reason not to let the guest use them. This patch, therefore, checks for the relevant support on the host CPU and, if present, advertises them to the guest as well. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Generalize the kvmppc_get_clockfreq() functionDavid Gibson2011-10-301-11/+24
| | | | | | | | | | | | | | | Currently the kvmppc_get_clockfreq() function reads the host's clock frequency from /proc/device-tree, which is useful to past to the guest in KVM setups. However, there are some other host properties advertised in the device tree which can also be relevant to the guests. This patch, therefore, replaces kvmppc_get_clockfreq() which can retrieve any named, single integer property from the host device tree's CPU node. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* Set an invalid-bits mask for each SPE instructionsFabien Chouteau2011-10-301-229/+271
| | | | | | | | | | | SPE instructions are defined by pairs. Currently, the invalid-bits mask is set for the first instruction, but the second one can have a different mask. example: GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Update SLOF firmware imageDavid Gibson2011-10-303-1/+1
| | | | | | | | | | | | | | | | This patch updates the SLOF submodule and precompiled image. The new SLOF versions contains two changes of note: * The previous SLOF has a bug in SCSI condition handling that was exposed by recent updates to qemu's SCSI emulation. This update fixes the bug. * The previous SLOF has a bug in its addressing of SCSI devices, which can be exposed under certain conditions. The new SLOF also fixes this. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Use Book3S-HV TCE acceleration capabilitiesDavid Gibson2011-10-304-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | The pseries machine of qemu implements the TCE mechanism used as a virtual IOMMU for the PAPR defined virtual IO devices. Because the PAPR spec only defines a small DMA address space, the guest VIO drivers need to update TCE mappings very frequently - the virtual network device is particularly bad. This means many slow exits to qemu to emulate the H_PUT_TCE hypercall. Sufficiently recent kernels allow this to be mitigated by implementing H_PUT_TCE in the host kernel. To make use of this, however, qemu needs to initialize the necessary TCE tables, and map them into itself so that the VIO device implementations can retrieve the mappings when they access guest memory (which is treated as a virtual DMA operation). This patch adds the necessary calls to use the KVM TCE acceleration. If the kernel does not support acceleration, or there is some other error creating the accelerated TCE table, then it will still fall back to full userspace TCE implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Allow KVM Book3S-HV on PPC970 CPUSDavid Gibson2011-10-303-12/+96
| | | | | | | | | | | | | | | | | | | | | | | | | At present, using the hypervisor aware Book3S-HV KVM will only work with qemu on POWER7 CPUs. PPC970 CPUs also have hypervisor capability, but they lack the VRMA feature which makes assigning guest memory easier. In order to allow KVM Book3S-HV on PPC970, we need to specially allocate the first chunk of guest memory (the "Real Mode Area" or RMA), so that it is physically contiguous. Sufficiently recent host kernels allow such contiguous RMAs to be allocated, with a kvm capability advertising whether the feature is available and/or necessary on this hardware. This patch enables qemu to use this support, thus allowing kvm acceleration of pseries qemu machines on PPC970 hardware. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de> --- agraf: fix to use memory api
* pseries: Support SMT systems for KVM Book3S-HVDavid Gibson2011-10-304-3/+46
| | | | | | | | | | | | | | | | | | | | | | | | Alex Graf has already made qemu support KVM for the pseries machine when using the Book3S-PR KVM variant (which runs the guest in usermode, emulating supervisor operations). This code allows gets us very close to also working with KVM Book3S-HV (using the hypervisor capabilities of recent POWER CPUs). This patch moves us another step towards Book3S-HV support by correctly handling SMT (multithreaded) POWER CPUs. There are two parts to this: * Querying KVM to check SMT capability, and if present, adjusting the cpu numbers that qemu assigns to cause KVM to assign guest threads to cores in the right way (this isn't automatic, because the POWER HV support has a limitation that different threads on a single core cannot be in different guests at the same time). * Correctly informing the guest OS of the SMT thread to core mappings via the device tree. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc/e500_pci: Fix an array overflow issueLiu Yu-B132012011-10-301-16/+22
| | | | | | | | When access PPCE500_PCI_IW1 the previous index get overflow. The patch fix the issue and update all to keep consistent style. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc/e500_pci: Fix code styleLiu Yu-B132012011-10-301-20/+56
| | | | | | | | Put trailing statements on next line. Signed-off-by: Liu Yu <yu.liu@freescale.com> Reviewed-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* MAINTAINERS: update wiki URL and machine names for target-xtensaMax Filippov2011-10-301-3/+8
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Optimize some forms of deposit.Richard Henderson2011-10-301-14/+51
| | | | | | | | | | | | | If the deposit replaces the entire word, optimize to a move. If we're inserting to the top of the word, avoid the mask of arg2 as we'll be shifting out all of the garbage and shifting in zeros. If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit when possible. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* hw/9pfs: Make VirtFS tracing work correctlyAneesh Kumar K.V2011-10-303-114/+112
| | | | | | | | | | this patch fix multiple issues with VirtFS tracing. a) Add tracepoint to the correct code path. We handle error in complete_pdu b) Fix indentation in python script c) Fix variable naming issue in python script Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec-all: Fix void pointer arithmeticStefan Weil2011-10-301-2/+1
| | | | | | | | | | | | | Adding an offset to a void pointer works with gcc but is not allowed by the current C standards. With -pedantic, gcc complains: exec-all.h:344: error: pointer of type ‘void *’ used in arithmetic Fix this, and also replace (unsigned long) by (uintptr_t) in the same statement. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Add linux-headers/asm to .gitignoreDavid Gibson2011-10-301-0/+1
| | | | | | | | | linux-headers/asm is a symlink generated during configure. It should not, therefore be committed to git, nor show up in git diffs and the like. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge branch 'rth/vis2' of git://repo.or.cz/qemu/rthBlue Swirl2011-10-2711-1043/+1400
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'rth/vis2' of git://repo.or.cz/qemu/rth: target-sparc: Implement FALIGNDATA inline. target-sparc: Implement BMASK/BSHUFFLE. target-sparc: Implement ALIGNADDR* inline. target-sparc: Implement EDGE* instructions. target-sparc: Implement fpack{16,32,fix}. target-sparc: Implement PDIST. target-sparc: Do exceptions management fully inside the helpers. target-sparc: Change fpr representation to doubles. target-sparc: Undo cpu_fpr rename. target-sparc: Extract float128 move to a function. target-sparc: Extract common code for floating-point operations. target-sparc: Make FPU/VIS helpers const when possible. target-sparc: Pass float64 parameters instead of dt0/1 temporaries. target-sparc: Add accessors for double-precision fpr access. target-sparc: Mark fprs dirty in store accessor. target-sparc: Add accessors for single-precision fpr access.
| * target-sparc: Implement FALIGNDATA inline.Richard Henderson2011-10-263-19/+26
| | | | | | | | | | | | This is a relatively simple sequence of shifts. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Implement BMASK/BSHUFFLE.Richard Henderson2011-10-263-4/+40
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Implement ALIGNADDR* inline.Richard Henderson2011-10-263-14/+22
| | | | | | | | | | | | | | | | While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not implemeneted at all. However, this is a very simple operation so we're better off doing this inline. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Implement EDGE* instructions.Richard Henderson2011-10-261-2/+175
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Implement fpack{16,32,fix}.Richard Henderson2011-10-263-1/+96
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Implement PDIST.Richard Henderson2011-10-263-2/+41
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Do exceptions management fully inside the helpers.Richard Henderson2011-10-263-91/+146
| | | | | | | | | | | | | | | | This reduces the size of the individual translation blocks, since we only emit a single call for each FOP rather than three. In addition, clear_float_exceptions expands inline to a single byte store. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Change fpr representation to doubles.Richard Henderson2011-10-268-211/+202
| | | | | | | | | | | | | | | | This allows a more efficient representation for 64-bit hosts. It should be about the same for 32-bit hosts, as we can still access the individual pieces of the double. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Undo cpu_fpr rename.Richard Henderson2011-10-261-28/+28
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Extract float128 move to a function.Richard Henderson2011-10-261-32/+18
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Extract common code for floating-point operations.Richard Henderson2011-10-261-454/+381
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Make FPU/VIS helpers const when possible.Richard Henderson2011-10-264-92/+78
| | | | | | | | | | | | This also removes the unused ENV parameter from these helpers. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Pass float64 parameters instead of dt0/1 temporaries.Richard Henderson2011-10-266-449/+381
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Add accessors for double-precision fpr access.Richard Henderson2011-10-261-112/+130
| | | | | | | | | | | | | | | | | | Begin using i64 quantities to manipulate double-precision values. On a 64-bit host this will, for the moment, generate less efficient code; on a 32-bit host code quality should be largely unchanged. Code quality for 64-bit will be adjusted with a subsequent patch. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Mark fprs dirty in store accessor.Richard Henderson2011-10-261-46/+8
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Add accessors for single-precision fpr access.Richard Henderson2011-10-261-195/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | Load, store, and "create destination". This version attempts to change the behaviour of the translator as little as possible. We previously used cpu_tmp32 as the temporary destination, and we continue to use that. This will eventually allow a change in representation of the fprs. Change the name of the cpu_fpr array to make certain that all instances are converted. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | Merge branch 'target-arm.for-upstream' of ↵Andrzej Zaborowski2011-10-278-12/+760
|\ \ | |/ |/| | | git://git.linaro.org/people/pmaydell/qemu-arm
| * target-arm: Fix use of free() in cpu_arm_close()Andreas Färber2011-10-201-1/+1
| | | | | | | | | | | | | | env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm/machine.c: Restore VFP registers correctlyDmitry Koshelev2011-10-191-1/+1
| | | | | | | | | | | | | | | | | | Fix the restoring of VFP registers on vmload. Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com> Reviewed-by: Juan Quintela <quintela@redhat.com> [peter.maydell: improved commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell2011-10-194-0/+90
| | | | | | | | | | | | | | Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * softfloat: Implement fused multiply-addPeter Maydell2011-10-193-0/+619
| | | | | | | | | | | | | | | | Implement fused multiply-add as a softfloat primitive. This implements "a+b*c" as a single step without any intermediate rounding; it is specified in IEEE 754-2008 and implemented in a number of CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Add ARM UDIV/SDIV supportPeter Maydell2011-10-193-1/+24
| | | | | | | | | | | | | | | | Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell2011-10-193-4/+5
| | | | | | | | | | | | | | | | | | | | Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: v6 media multiply space: UNDEF on unassigned encodingsPeter Maydell2011-10-191-4/+20
| | | | | | | | | | | | | | | | Clean up the decoding of the v6 media multiply space so that we UNDEF on unassigned encodings rather than randomly interpreting them as some instruction in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * rsqrte_f32: No need to copy sign bit.Christophe LYON2011-10-191-2/+1
| | | | | | | | | | | | | | Indeed, the result is known to be always positive. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Sparc: split load and store op helpersBlue Swirl2011-10-263-2418/+2437
| | | | | | | | | | | | | | Move load and store op helpers top ldst_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Sparc: convert win_helper to trace frameworkBlue Swirl2011-10-262-22/+16
| | | | | | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Sparc: convert interrupt helpers to trace frameworkBlue Swirl2011-10-263-26/+23
| | | | | | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Sparc: convert mmu_helper to trace frameworkBlue Swirl2011-10-262-44/+30
| | | | | | | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Sparc: split MMU helpersBlue Swirl2011-10-264-861/+880
| | | | | | | | | | | | | | Move MMU helpers to mmu_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Sparc: fix coding style in helper.cBlue Swirl2011-10-261-43/+52
| | | | | | | | | | | | | | Before the next patch, fix coding style of the areas affected. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Sparc: avoid AREG0 for division op helpersBlue Swirl2011-10-264-82/+88
| | | | | | | | | | | | | | | | Make [su]div{,cc} helpers take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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