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* disas: Implement disassembly output for A64Claudio Fontana2014-02-087-3/+118
| | | | | | | | | | | | | | | | | | | Use libvixl to implement disassembly output in debug logs for A64, for use with both AArch64 hosts and targets. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: * added support for target disassembly * switched to custom QEMUDisassembler so the output format matches what QEMU expects * make sure we correctly fall back to "just print hex" if we didn't build the AArch64 disassembler because of lack of a C++ compiler * rename from 'aarch64' to 'arm-a64' because this is a disassembler for the A64 instruction set * merge aarch64.c and aarch64-cxx.cc into one C++ file * simplify the aarch64.c<->aarch64-cxx.cc interface] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* disas/libvixl: Fix upstream libvixl compilation issuesPeter Maydell2014-02-083-18/+17
| | | | | | | | | | | Fix various minor issues with upstream libvixl so that it will compile successfully on the platforms QEMU cares about: * remove unused GBytes constant (it clashes with the glib headers) * fix suffixes on constants to use 'LL' for 64 bit constants so we can compile on 32 bit hosts Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* disas: Add subset of libvixl sources for A64 disassemblerPeter Maydell2014-02-0815-0/+6620
| | | | | | | | | | Add the subset of the libvixl sources that are needed for the A64 disassembler support. These sources come from https://github.com/armvixl/vixl commit 578645f14e122d2b which is VIXL release 1.1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* rules.mak: Link with C++ if we have a C++ compilerPeter Maydell2014-02-081-2/+6
| | | | | | | | | If we have a C++ compiler available, link with it, because we might be linking some C++ files in. This allows us to include C++ object files in the QEMU binary proper. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* rules.mak: Support .cc as a C++ source file suffixPeter Maydell2014-02-081-1/+5
| | | | | | | | | The A64 disassembler libvixl uses .cc as its suffix for C++ source files, so add support for it (we already support .cpp). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* arm_gic: Add GICC_APRn state to the GICStateChristoffer Dall2014-02-083-2/+27
| | | | | | | | | | | | | The GICC_APRn registers are not currently supported by the ARM GIC v2.0 emulation. This patch adds the missing state. Note that we also change the number of APRs to use a define GIC_NR_APRS based on the maximum number of preemption levels. This patch also adds RAZ/WI accessors for the four registers on the emulated CPU interface. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* vmstate: Add uint32 2D-array supportChristoffer Dall2014-02-081-0/+6
| | | | | | | | Add support for saving VMState of 2D arrays of uint32 values. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm_gic: Support setting/getting binary point regChristoffer Dall2014-02-083-5/+20
| | | | | | | | | | Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm_gic: Keep track of SGI sourcesChristoffer Dall2014-02-083-14/+96
| | | | | | | | | | | | | | | | | | Right now the arm gic emulation doesn't keep track of the source of an SGI (which apparently Linux guests don't use, or they're fine with assuming CPU 0 always). Add the necessary matrix on the GICState structure and maintain the data when setting and clearing the pending state of an IRQ and make the state visible to the guest. Note that we always choose to present the source as the lowest-numbered CPU in case multiple cores have signalled the same SGI number to a core on the system. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm_gic: Fix GIC pending behaviorChristoffer Dall2014-02-082-18/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing implementation of the pending behavior in gic_set_irq, gic_complete_irq, and the distributor pending set/clear registers does not follow the semantics of the GICv2.0 specs, but may implement the 11MPCore support. Therefore, maintain the existing semantics for 11MPCore and v7M NVIC and change the behavior to be in accordance with the GICv2.0 specs for "generic implementations" (s->revision == 1 || s->revision == 2). Generic implementations distinguish between setting a level-triggered interrupt pending through writes to the GICD_ISPENDR and when hardware raises the interrupt line. Writing to the GICD_ICPENDR will not cause the interrupt to become non-pending if the line is still active, and conversely, if the line is deactivated but the interrupt is marked as pending through a write to GICD_ISPENDR, the interrupt remains pending. Handle this situation in the GIC_TEST_PENDING (which now becomes a static inline named gic_test_pending) and let the 'pending' field correspond only to the latched state of the D-flip flop in the GICv2.0 specs Figure 4-10. The following changes are added: gic_test_pending: Make this a static inline and split out the 11MPCore from the generic behavior. For the generic behavior, consider interrupts pending if: ((s->irq_state[irq].pending & (cm) != 0) || (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm)) gic_set_irq: Split out the 11MPCore from the generic behavior. For the generic behavior, always GIC_SET_LEVEL() on positive level, but only GIC_SET_PENDING for edge-triggered interrupts and always simply GIC_CLEAR_LEVEL() on negative level. gic_complete_irq: Only resample the line for line-triggered interrupts on an 11MPCore. Generic implementations will sample the line directly in gic_test_pending(). Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton2014-02-081-22/+61
| | | | | | | | | Add support for the AArch32 floating-point half-precision to double- precision conversion VCVTB and VCVTT instructions. Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: fixed a minor missing-braces style issue] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell2014-02-081-3/+20
| | | | | | | Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée2014-02-081-1/+70
| | | | | | | | | Add the byte-reverse operations REV64, REV32 and REV16 from the two-reg-misc group. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell2014-02-081-2/+83
| | | | | | | Add the narrowing integer instructions in the 2-reg-misc class. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell2014-02-083-6/+41
| | | | | | | Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell2014-02-081-2/+134
| | | | | | | | | | Implement the simple 2-register-misc operations we can share with the scalar-two-register-misc code. (SUQADD, USQADD, SQABS, SQNEG also fall into this category, but aren't implemented in the scalar-2-register case yet either.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell2014-02-081-1/+109
| | | | | | | Add a skeleton decode for the SIMD 2-reg misc group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell2014-02-081-1/+86
| | | | | | | | | Implement the simple 64 bit integer operations from the SIMD scalar 2-register misc group (C3.6.12): the comparisons against zero, plus ABS and NEG. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell2014-02-081-19/+87
| | | | | | | | | Implement the remaining integer instructions in the scalar-three-reg-same group: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL, SQDMULH, SQRDMULH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement scalar pairwise opsPeter Maydell2014-02-081-1/+113
| | | | | | | Implement the instructions in the scalar pairwise group (C3.6.8). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTRPeter Maydell2014-02-081-0/+3
| | | | | | | | | We have macros for marking TCGv values as unused, checking if they are unused and comparing them to each other. However these only exist for TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell2014-02-081-1/+123
| | | | | | | | Implement the pairwise integer operations in the 3-reg-same SIMD group: ADDP, SMAXP, SMINP, UMAXP and UMINP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell2014-02-081-4/+127
| | | | | | | | | | | Implement the SIMD 3-reg-same instructions where the size == 3 case is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX, UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL, SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.) This completes the non-pairwise integer instructions in this category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell2014-02-081-22/+112
| | | | | | | | | | | | | Implement the SIMD 3-reg-same instructions SQADD, UQADD, SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL, SQRSHL, UQRSHL; these are all simple calls to existing Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL for the 3-reg-same-scalar category (but not the others because they can have non-size-64 operands and the scalar_3reg_same function doesn't support that yet.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch ↵Peter Maydell2014-02-089-37/+92
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/juanquintela/tags/migration/20140204-1' into staging migration/next for 20140204 # gpg: Signature made Tue 04 Feb 2014 15:52:00 GMT using RSA key ID 5872D723 # gpg: Can't check signature: public key not found * remotes/juanquintela/tags/migration/20140204-1: Don't abort on memory allocation error Don't abort on out of memory when creating page cache XBZRLE cache size should not be larger than guest memory size migration:fix free XBZRLE decoded_buf wrong Add check for cache size smaller than page size Set xbzrle buffers to NULL after freeing them to avoid double free errors exec: fix ram_list dirty map optimization vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-type Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Don't abort on memory allocation errorOrit Wasserman2014-02-043-7/+17
| | | | | | | | | | | | | | | | | | It is better to fail migration in case of failure to allocate new cache item Signed-off-by: Orit Wasserman <owasserm@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
| * Don't abort on out of memory when creating page cacheOrit Wasserman2014-02-042-6/+30
| | | | | | | | | | | | Signed-off-by: Orit Wasserman <owasserm@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
| * XBZRLE cache size should not be larger than guest memory sizeOrit Wasserman2014-02-041-0/+7
| | | | | | | | | | | | Signed-off-by: Orit Wasserman <owasserm@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
| * migration:fix free XBZRLE decoded_buf wrongGonglei (Arei)2014-02-043-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | When qemu do live migration with xbzrle, qemu malloc decoded_buf at destination end but free it at source end. It will crash qemu by double free error in some scenarios. Splitting the XBZRLE structure for clear logic distinguishing src/dst side. Signed-off-by: ChenLiang <chenliang88@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Orit Wasserman <owasserm@redhat.com> Signed-off-by: GongLei <arei.gonglei@huawei.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
| * Add check for cache size smaller than page sizeOrit Wasserman2014-02-042-1/+13
| | | | | | | | | | | | Signed-off-by: Orit Wasserman <owasserm@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
| * Set xbzrle buffers to NULL after freeing them to avoid double free errorsOrit Wasserman2014-02-041-0/+3
| | | | | | | | | | | | | | Signed-off-by: Orit Wasserman <owasserm@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
| * exec: fix ram_list dirty map optimizationAlexey Kardashevskiy2014-02-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ae2810c4bb3b383176e8e1b33931b16c01483aab patch introduced optimization for ram_list.dirty_memory update. However it can only work correctly if hpratio is 1 as the @bitmap parameter stores 1 bits per system page size (may vary, 4K or 64K on PPC64) and ram_list.dirty_memory stores 1 bit per TARGET_PAGE_SIZE (which is hardcoded to 4K). This fixes hpratio!=1 case to fall back to the slow path. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Juan Quintela <quintela@redhat.com>
| * vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-typePeter Maydell2014-02-043-13/+7
| | | | | | | | | | | | | | | | | | | | | | The VMSTATE_STRUCT_POINTER macros are a bit odd in that they must be passed an argument "FooType *" rather than just taking the FooType. They're only used in one place, so it's easy to tidy this up. This also lets us use the macro to replace the hand-rolled VMSTATE_PTIMER. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Juan Quintela <quintela@redhat.com>
* | Merge remote-tracking branch 'remotes/kraxel/tags/pull-roms-1' into stagingPeter Maydell2014-02-079-11/+11
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update seabios to 1.7.4 # gpg: Signature made Mon 03 Feb 2014 14:42:44 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-roms-1: Update seabios binaries to 1.7.4 Update seabios submodule to 1.7.4 roms: remove explicit MAKEFLAGS from recursive make invocations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | Update seabios binaries to 1.7.4Gerd Hoffmann2014-02-037-0/+0
| | | | | | | | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | Update seabios submodule to 1.7.4Gerd Hoffmann2014-02-031-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not that many changes as we already have a git snapshot pretty close to final 1.7.4 in the tree. Most notably change is the vgabios change which fixes the windows guest regression. Full git shortlog: Gerd Hoffmann (2): run qemu_cfg_e820 only for CONFIG_QEMU=y change boot order load log level Kevin O'Connor (10): Minor - move sgdt/lgdt macros from stacks.c to x86.h. Separate out sec32init sections even when not doing code relocation. floppy: Fix incorrect LBA to CHS translation. floppy: Fix accesses to DOR register. vgabios: Avoid memory references via %esp register in vgabios. Small improvements to irqentry_extrastack assembler. floppy: Encode command and flags into single value in floppy pio code. On disk format request, verify cylinders and pass to driver. floppy: Implement cylinder seeking when accessing a different cylinder. coreboot: Make sure to print the SeaBIOS version in cbmem debug output. Kyösti Mälkki (1): Fix CBMEM console overflow
| * | roms: remove explicit MAKEFLAGS from recursive make invocationsBruce Rogers2014-02-031-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using $(MAKE) within a makefile, we shouldn't be explicitly including $(MAKEFLAGS) on the command-line. It causes problems when that makefile is recursively invoked. When the roms/Makefile is invoked as in make -C roms bios a spurious 'w' appears on the sub-make invocation, due to the erroneous $(MAKEFLAGS) inclusion. Signed-off-by: Bruce Rogers <brogers@suse.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | | Merge remote-tracking branch 'remotes/stefanha/tags/qtest-for-peter' into ↵Peter Maydell2014-02-071-22/+23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging qtest resource cleanup patches # gpg: Signature made Tue 04 Feb 2014 08:29:12 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/qtest-for-peter: qtest: unlink UNIX domain sockets after connecting qtest: unlink QEMU pid file after startup Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | qtest: unlink UNIX domain sockets after connectingStefan Hajnoczi2014-02-031-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UNIX domain sockets are leaked when tests call abort(3) (indirectly via glib assert functions). Unlink the files immediately after the connection has been established to avoid leaks. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | | qtest: unlink QEMU pid file after startupStefan Hajnoczi2014-02-031-11/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | After starting the QEMU process and initializing the QMP connection, we can read the pid file and unlink it. Just stash away the pid instead of the pid filename. This way we can avoid pid file leaks since running tests may abort(3) without cleanup. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* | | Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell2014-02-068-134/+206
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/kvm/uq/master: target-i386: Move KVM default-vendor hack to instance_init target-i386: Don't change x86_def_t struct on cpu_x86_register() target-i386: Eliminate CONFIG_KVM #ifdefs kvm: add support for hyper-v timers kvm: make hyperv vapic assist page migratable kvm: make hyperv hypercall and guest os id MSRs migratable. kvm: make availability of Hyper-V enlightenments dependent on KVM_CAP_HYPERV KVM: fix coexistence of KVM and Hyper-V leaves kvm: print suberror on all internal errors target-i386: kvm_check_features_against_host(): Kill feature word array target-i386: kvm_cpu_fill_host(): Fill feature words in a loop target-i386: kvm_cpu_fill_host(): Set all feature words at end of function target-i386: kvm_cpu_fill_host(): No need to check xlevel2 target-i386: kvm_cpu_fill_host(): No need to check CPU vendor target-i386: kvm_cpu_fill_host(): No need to check level target-i386: kvm_cpu_fill_host(): Kill unused code Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target-i386: Move KVM default-vendor hack to instance_initEduardo Habkost2014-02-031-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we will not have a cpu_x86_find_by_name() function anymore, move the KVM default-vendor hack to instance_init. Unfortunately we can't move that code to class_init because it depends on KVM being initialized. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | target-i386: Don't change x86_def_t struct on cpu_x86_register()Eduardo Habkost2014-02-031-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As eventually the x86_def_t data is going to be provided by the CPU class, it's better to not touch it, and handle the special cases on the X86CPU object itself. Current behavior of the code should stay exactly the same. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | target-i386: Eliminate CONFIG_KVM #ifdefsEduardo Habkost2014-02-031-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The compiler is already able to eliminate the kvm_arch_get_supported_cpuid() calls in kvm_cpu_fill_host() and filter_features_for_kvm(), so we can eliminate the CONFIG_KVM #ifdefs there. Also, kvm_cpu_fill_host() and host_cpuid() don't need to check CONFIG_KVM, as they don't have any KVM-specific function calls. Tested to build successfully with CONFIG_KVM disabled, using the following CFLAGS combinations: "-DNDEBUG", "-DNDEBUG -O', "-DNDEBUG -O0", "-DNDEBUG -O1", "-DNDEBUG -O2". Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | kvm: add support for hyper-v timersVadim Rozenfeld2014-02-037-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://msdn.microsoft.com/en-us/library/windows/hardware/ff541625%28v=vs.85%29.aspx This code is generic for activating reference time counter or virtual reference time stamp counter Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | kvm: make hyperv vapic assist page migratableVadim Rozenfeld2014-02-033-1/+32
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | kvm: make hyperv hypercall and guest os id MSRs migratable.Vadim Rozenfeld2014-02-033-2/+39
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | kvm: make availability of Hyper-V enlightenments dependent on KVM_CAP_HYPERVPaolo Bonzini2014-02-031-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MS docs specify HV_X64_MSR_HYPERCALL as a mandatory interface, thus we must provide the MSRs even if the user only specified features that, like relaxed timing, in principle don't require them. And the MSRs are only there if the hypervisor has KVM_CAP_HYPERV. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | KVM: fix coexistence of KVM and Hyper-V leavesPaolo Bonzini2014-02-031-22/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kvm_arch_init_vcpu's initialization of the KVM leaves at 0x40000100 is broken, because KVM_CPUID_FEATURES is left at 0x40000001. Move it to 0x40000101 if Hyper-V is enabled. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | | kvm: print suberror on all internal errorsRadim Krčmář2014-02-031-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KVM introduced internal error exit reason and suberror at the same time, and later extended it with internal error data. QEMU does not report suberror on hosts between these two events because we check for the extension. (half a year in 2009, but it is misleading) Fix by removing KVM_CAP_INTERNAL_ERROR_DATA condition on printf. (partially improved by bb44e0d12df70 and ba4047cf848a3 in the past) Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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