summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* xen: Clean up build systemJan Kiszka2011-07-173-13/+6
| | | | | | | | | Introduce CONFIG_XEN_BACKEND so that this new config solely controls the target-independent backend build and CONFIG_XEN can focus on per-target building. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* Fix signal handling of SIG_IPI when io-thread is enabledAlexandre Raymond2011-07-161-1/+9
| | | | | | | | | | | | | | | Both the signal thread (via sigwait()) and the cpu thread (via a normal signal handler) were attempting to catch SIG_IPI. This resulted in random freezes under Darwin. This patch separates SIG_IPI from the rest of the signals handled by the signal thread, because it is independently caught by the cpu thread. Signed-off-by: Alexandre Raymond <cerbere@gmail.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix signal handling when io-thread is disabledAlexandre Raymond2011-07-161-1/+1
| | | | | | | | | | | | | | | | | Changes since v1: - take pthread_sigmask() out of the ifdef as it is now common to both parts. This fix effectively blocks, in the main thread, the signals handled by signalfd or the compatibility signal thread. This way, such signals are received synchronously in the main thread through sigfd_handler() instead of triggering the signal handler directly, asynchronously. Signed-off-by: Alexandre Raymond <cerbere@gmail.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/README: Expand advice on number of TCG ops per target insnPeter Maydell2011-07-161-1/+9
| | | | | | | | | Expand the note on the number of TCG ops generated per target insn, to be clearer about the range of applicability of the 20 op rule of thumb. Also add a note about the hard MAX_OP_PER_INSTR limit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* set ELF_HWCAP for SPARC and SPARC64Artyom Tarasenko2011-07-141-2/+4
| | | | | | | | setting ELF_HWCAP fixes dynamic library loading for Linux/sparc64 This patch allows loading busybox from Debian 6 initrd Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: fix FPU and AM enable checks for translationBlue Swirl2011-07-142-23/+35
| | | | | | | | | Translation used incorrectly CPUState fields directly to check for FPU enable state and 32 bit address masking on Sparc64. Fix by using TB flags instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: C99 comment fix for block-transfer ASIsTsuneo Saito2011-07-141-14/+14
| | | | | | | Fixed C99 comments on block-tranfer ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Add JPS1 ASI_BLK_AIU[PS]L ASIs for ldfa and stfaTsuneo Saito2011-07-141-0/+4
| | | | | | | Support JPS1 little endian block transfer ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for stfaTsuneo Saito2011-07-141-1/+5
| | | | | | | Support UA2007 block store ASIs for stfa instructions. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for ldfaTsuneo Saito2011-07-141-1/+5
| | | | | | | Support UA2007 block load ASIs for ldfa instructions. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: fp_disabled checks on stfa/stdfa/stqfaTsuneo Saito2011-07-141-0/+9
| | | | | | | | stfa/stdfa/stqfa instructions should raise fp_disabled exceptions if %pstate.PEF==0 or %fprs.FEF==0. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Implement stfa/stdfa/stqfa instrcutions properlyTsuneo Saito2011-07-142-6/+11
| | | | | | | | This patch implements sparcv9 stfa/stdfa/stqfa instructions with non block-store ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: fp_disabled checks on ldfa/lddfa/ldqfaTsuneo Saito2011-07-141-0/+9
| | | | | | | | ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions if %pstate.PEF==0 or %fprs.FEF==0. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Implement ldfa/lddfa/ldqfa instructions properlyTsuneo Saito2011-07-141-5/+11
| | | | | | | | This patch implements sparcv9 ldfa/lddfa/ldqfa instructions with non block-load ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* os-posix: set groups properly for -runasStefan Hajnoczi2011-07-121-0/+6
| | | | | | | | | | | | | Andrew Griffiths reports that -runas does not set supplementary group IDs. This means that gid 0 (root) is not dropped when switching to an unprivileged user. Add an initgroups(3) call to use the -runas user's /etc/groups membership to update the supplementary group IDs. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Acked-by: Chris Wright <chrisw@sous-sol.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* esp: cancel current request only if some request is in flightHervé Poussineau2011-07-121-1/+1
| | | | | | | | | | | | This bug was introduced in 94d3f98a3f3caddd7875f9a11776daeb84962a7b: scsi_cancel_io was checking if some request was pending before trying to cancel it, while scsi_req_cancel always cancels the request. This may lead to a crash of Qemu due to dereferencing a NULL pointer, as exhibited by NetBSD 5.1 installer on MIPS Magnum emulation. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-alpha, target-ppc: Remove unnecessary setjmp.h includePeter Maydell2011-07-122-4/+0
| | | | | | | | | | Remove the include of setjmp.h from the cpu.h of target-alpha and target-ppc. This is unnecessary because cpu-defs.h already includes this header; this change brings these two targets into line with all the rest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Remove unneeded setjmp.h (fix compilation on Debian "lenny")Stefan Weil2011-07-121-1/+0
| | | | | | | | | | | | Some versions of png.h cannot be included after setjmp.h, even when PNG_SKIP_SETJMP_CHECK was defined. setjmp.h was included from qemu-common.h and is not needed there. Removing the include statement fixes compilation of ui/vnc-enc-tight.c with CONFIG_VNC_PNG defined. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Reload local variables after return from longjmpJan Kiszka2011-07-121-0/+4
| | | | | | | | | | | Recent compilers look deep into cpu_exec, find longjmp as a noreturn function and decide to smash some stack variables as they won't be used again. This may lead to env becoming invalid after return from setjmp, causing crashes. Fix it by reloading env from cpu_single_env in that case. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec-all.h: Make MAX_OP_PER_INSTR large enough for target-arm's usesPeter Maydell2011-07-121-5/+1
| | | | | | | | | | | | | | | | | The target-arm frontend's worst-case TCG ops per instr is 194 (and in general many of the "load multiple registers" ARM instructions generate more than 100 TCG ops). Raise MAX_OP_PER_INSTR accordingly to avoid possible buffer overruns. Since it doesn't make any sense for the "64 bit guest on 32 bit host" case to have a smaller limit than the normal case, we collapse the two cases back into each other again. (This increase costs us about 14K in extra static buffer space and 21K of extra margin at the end of a 32MB codegen buffer.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec.c: Fix calculation of code_gen_buffer_max_sizePeter Maydell2011-07-121-2/+2
| | | | | | | | | | | | When calculating the point at which we should not try to put another TB into the code gen buffer, we have to allow not just for OPC_MAX_SIZE but OPC_BUF_SIZE. This is because the target translate.c will only stop when an instruction has put it past the OPC_MAX_SIZE limit, so we have to include the MAX_OP_PER_INSTR margin which that final insn might have used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* spapr: use specific endian ld/st_physAlexander Graf2011-07-122-8/+8
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* s390-virtio: use specific endian ld/st_physAlexander Graf2011-07-122-8/+8
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ppc405_uc: use specific endian ld/st_physAlexander Graf2011-07-121-20/+23
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* pl080: use specific endian ld/st_physAlexander Graf2011-07-121-4/+4
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* msix: use specific endian ld/st_physAlexander Graf2011-07-121-1/+1
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* msi: use specific endian ld/st_physAlexander Graf2011-07-121-1/+1
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* intel-hda: use specific endian ld/st_physAlexander Graf2011-07-121-17/+4
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* hpet: use specific endian ld/st_physAlexander Graf2011-07-121-1/+1
| | | | | Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec: add endian specific phys ld/st functionsAlexander Graf2011-07-122-10/+203
| | | | | | | | | | | | | | | | Device code some times needs to access physical memory and does that through the ld./st._phys functions. However, these are the exact same functions that the CPU uses to access memory, which means they will be endianness swapped depending on the target CPU. However, devices don't know about the CPU's endianness, but instead access memory directly using their own interface to the memory bus, so they need some way to read data with their native endianness. This patch adds _le and _be functions to ld./st._phys. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ide: Initialise buffers with zerosKevin Wolf2011-07-051-1/+5
| | | | | | | | | Just in case there's still a way how a guest can read out buffers when it's not supposed to, let's zero the buffers during initialisation so that we don't leak information to the guest. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
* ide: Ignore reads during PIO in and writes during PIO outKevin Wolf2011-07-051-8/+36
| | | | | | | | | | | | | | | | This fixes https://bugs.launchpad.net/qemu/+bug/786209: When the DRQ_STAT bit is set, the IDE core permits both data reads and data writes, regardless of whether the current transfer was initiated as a read or write. This potentially leaks uninitialized host memory into the guest, if, before doing anything else to an IDE device, the guest begins a write transaction (e.g. WIN_WRITE), but then *reads* from the IO port instead of writing to it. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
* block: drive_init(): Improve CHS setting error messageLuiz Capitulino2011-07-051-1/+1
| | | | | | | | The current message doesn't clearly communicate the error cause. Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block: drive_init(): Simplify interface type settingLuiz Capitulino2011-07-051-8/+4
| | | | | | Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* virtio-blk: Turn drive serial into a qdev propertyMarkus Armbruster2011-07-057-13/+31
| | | | | | | | | | It needs to be a qdev property, because it belongs to the drive's guest part. Precedence: commit a0fef654 and 6ced55a5. Bonus: info qtree now shows the serial number. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block/raw-posix: Linux compat-ioctl warning workaroundJohannes Stezenbach2011-07-051-0/+14
| | | | | | | | | | | | | | | | | | | | On Linux x86_64 host with 32bit userspace, running qemu or even just "qemu-img create -f qcow2 some.img 1G" causes a kernel warning: ioctl32(qemu-img:5296): Unknown cmd fd(3) cmd(00005326){t:'S';sz:0} arg(7fffffff) on some.img ioctl32(qemu-img:5296): Unknown cmd fd(3) cmd(801c0204){t:02;sz:28} arg(fff77350) on some.img ioctl 00005326 is CDROM_DRIVE_STATUS, ioctl 801c0204 is FDGETPRM. The warning appears because the Linux compat-ioctl handler for these ioctls only applies to block devices, while qemu also uses the ioctls on plain files. Work around by calling fstat() the ensure the ioctls are only used on block devices. Signed-off-by: Johannes Stezenbach <js@sig21.net> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qemu-img: Add cache command line optionFederico Simoncelli2011-07-052-16/+70
| | | | | | | | | | | | | | qemu-img currently writes disk images using writeback and filling up the cache buffers which are then flushed by the kernel preventing other processes from accessing the storage. This is particularly bad in cluster environments where time-based algorithms might be in place and accessing the storage within certain timeouts is critical. This patch adds the option to choose a cache method when writing disk images. Signed-off-by: Federico Simoncelli <fsimonce@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* Documentation: Remove outdated host_device noteKevin Wolf2011-07-051-6/+0
| | | | | | | People shouldn't explicitly specify host_device any more. raw is doing the Right Thing. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* pxa2xx_lcd: add proper rotation supportVasily Khoruzhick2011-07-045-22/+144
| | | | | | | | Until now, pxa2xx_lcd only supported 90deg rotation, but some machines (for example Zipit Z2) needs 270deg rotation. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* arm: Add const attribute to some arm_boot_info pointersStefan Weil2011-07-044-7/+7
| | | | | | | | | | | | | Parameter 'info' is const, so add the missing attribute. v2: Add 'const' to the local variable info in do_cpu_reset() and to the boot_info field in CPUARMState (suggested by Peter Maydell). Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* esp: correctly fill bus id with requested lunHervé Poussineau2011-07-021-1/+1
| | | | | | | | | This bug showed up after 1455084ea2c48abf23c4e4e15e378ee43457f381, and may be seen only on operating systems *not* using DMA to give commands to SCSI adapter. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG/PPC: use stack for TCG tempsBlue Swirl2011-07-022-4/+10
| | | | | | Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivxArtyom Tarasenko2011-07-011-10/+22
| | | | | | | | udivx and sdvix don't modify condition flags, so they shall not overwrite cpu_cc_* Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl2011-07-0118-207/+493
|\ | | | | | | | | | | | | | | | | | | | | | | | | * 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: move TLBs to their own arrays PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type PPC: E500: Use MAS registers instead of internal TLB representation PPC: Only set lower 32bits with mtmsr PPC: update openbios firmware PPC: mpc8544ds: Add hypervisor node PPC: calculate kernel,initrd,cmdline locations dynamically target-ppc: Handle memory-forced I/O controller access PPC: E500: Implement reboot controller
| * PPC: move TLBs to their own arraysAlexander Graf2011-06-176-37/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, we've created a union over multiple different TLB types and allocated that union. While it's a waste of memory (and cache) to allocate TLB information for a TLB type with much information when you only need little, it also inflicts another issue. With the new KVM API, we can now share the TLB between KVM and qemu, but for that to work we need to have both be in the same layout. We can't just stretch it over to fit some internal different TLB representation. Hence this patch moves all TLB types to their own array, allowing us to only address and allocate exactly the boundaries required for the specific TLB type at hand. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU typeAlexander Graf2011-06-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | We have some KVM interaction code in Qemu that tries to be clever and ignore some capabilities when running on BookE style MMUs. Unfortunately, the default CPU bamboo was defaulting to was not a BookE-style MMU, resulting in the check to fail. With this patch, guests can run again on 440 with -enable-kvm. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC: E500: Use MAS registers instead of internal TLB representationAlexander Graf2011-06-174-143/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The natural format for e500 cores to do TLB manipulation with are the MAS registers. Instead of converting them into some internal representation and back again when the guest reads them, we can just keep the data identical to the way the guest passed it to us. The main advantage of this approach is that we're getting closer to being able to share MMU data with KVM using shared memory, so that we don't need to copy lots of MMU data back and forth all the time. For this to work however, another patch is required that gets rid of the TLB union, as that destroys our memory layout that needs to be identical with the kernel one. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC: Only set lower 32bits with mtmsrAlexander Graf2011-06-171-11/+6
| | | | | | | | | | | | | | | | | | | | | | As Nathan pointed out correctly, the mtmsr instruction does not modify the high 32 bits of MSR. It also doesn't matter if SF is set or not, the instruction always behaves the same. This patch moves it a bit closer to the spec. Reported-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC: update openbios firmwareAlexander Graf2011-06-172-2/+4
| | | | | | | | | | | | | | | | There were some changes upstream to account for broken usage of mtmsr, so before applying the mtmsr patch we need to update OpenBIOS, otherwise the PPC target would break. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC: mpc8544ds: Add hypervisor nodeAlexander Graf2011-06-173-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | When running a PPC guest with KVM that can do PV operations, we need to indicate the guest which instructions to use for a hypercall and that it is running as KVM guest. This logic was available on openbios based machines already. This patch also adds said functionality to the mpc8544ds machine. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com>
OpenPOWER on IntegriCloud