summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* target-xtensa: refactor standard core configurationMax Filippov2014-02-244-21/+13
| | | | | | | | Coalesce all standard configuration sections into single DEFAULT_SECTIONS macro for all cores. This allows to add new features in a single place: overlay_tool.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add basic tests for cache opcodesMax Filippov2014-02-242-0/+98
| | | | | | | Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: allow using core configuration in testsMax Filippov2014-02-2430-32/+37
| | | | | | | Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add overridable test_init macroMax Filippov2014-02-242-2/+6
| | | | | | | Some test suites, like MMU, need per-test initialization. Don't make them redefine test macro, add test_init for that purpose. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add basic checks to icache opcodesMax Filippov2014-02-243-0/+33
| | | | | | | | | Check privilege level for privileged instructions (IHU, III, IIU and IPFL are privileged), memory accessibility for instructions that reference memory (IH* and IPFL) and windowed register validity for all instruction cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add basic checks to dcache opcodesMax Filippov2014-02-241-0/+38
| | | | | | | | | Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB, DIWBI, DPFL are privileged), memory accessibility for instructions that reference memory (all DH* and DPFL) and windowed register validity for all data cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: add RRRI4 opcode format fieldsMax Filippov2014-02-241-0/+9
| | | | | | This encoding is used by cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* opencores_eth: flush queue whenever can_receive can go from false to trueMax Filippov2014-02-241-2/+31
| | | | | | | | | | | | The following registers control whether MAC can receive frames: - MODER.RXEN bit that enables/disables receiver; - TX_BD_NUM register that specifies number of RX descriptors. Notify QEMU networking core when the MAC is ready to receive frames. Discard frame and raise BUSY interrupt when the frame arrives but the current RX descriptor is not empty. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/xtensa: add support for ML605 and KC705 FPGA boardMax Filippov2014-02-241-4/+47
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de>
* Merge remote-tracking branch ↵Peter Maydell2014-02-2117-574/+1794
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20140220' into staging target-arm queue: * Fix a bug causing an assertion in the NVIC on ARMv7M models * More A64 Neon instructions * Refactor cpreg API to separate out access check functions, as groundwork for AArch64 system mode * Fix bug in linux-user A64 store-exclusive of XZR # gpg: Signature made Thu 20 Feb 2014 11:12:57 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140220: (30 commits) linux-user: AArch64: Fix exclusive store of the zero register target-arm: A64: Implement unprivileged load/store target-arm: A64: Implement narrowing three-reg-diff operations target-arm: A64: Implement the wide 3-reg-different operations target-arm: A64: Add most remaining three-reg-diff widening ops target-arm: A64: Add opcode comments to disas_simd_three_reg_diff target-arm: A64: Implement store-exclusive for system mode target-arm: Fix incorrect type for value argument to write_raw_cp_reg target-arm: Remove failure status return from read/write_raw_cp_reg target-arm: Remove unnecessary code now read/write fns can't fail target-arm: Drop success/fail return from cpreg read and write functions target-arm: Convert miscellaneous reginfo structs to accessfn target-arm: Convert generic timer reginfo to accessfn target-arm: Convert performance monitor reginfo to accessfn target-arm: Split cpreg access checks out from read/write functions target-arm: Stop underdecoding ARM946 PRBS registers target-arm: Log bad system register accesses with LOG_UNIMP target-arm: Remove unused ARMCPUState sr substruct target-arm: Restrict check_ap() use of S and R bits to v6 and earlier target-arm: Define names for SCTLR bits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * linux-user: AArch64: Fix exclusive store of the zero registerJanne Grunau2014-02-201-2/+4
| | | | | | | | | | | | Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: A64: Implement unprivileged load/storePeter Maydell2014-02-201-32/+37
| | | | | | | | | | | | | | Implement the unprivileged load and store instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell2014-02-201-1/+59
| | | | | | | | | | | | | | | | Implement the narrowing three-reg-diff operations: ADDHN, RADDHN, SUBHN and RSUBHN. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell2014-02-201-1/+40
| | | | | | | | | | | | | | | | Implement the wide three-reg-different operations: SADDW, UADDW, SSUBW and USUBW. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell2014-02-201-21/+88
| | | | | | | | | | | | | | | | Add the remainder of the 64x64->128 operations in the three-reg-diff category except for PMULL, PMULL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Add opcode comments to disas_simd_three_reg_diffPeter Maydell2014-02-201-11/+11
| | | | | | | | | | | | | | | | | | The opcode switch in disas_simd_three_reg_diff() is missing the customary comments indicating which cases correspond to which instructions. Add them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement store-exclusive for system modePeter Maydell2014-02-201-6/+62
| | | | | | | | | | | | | | | | System mode store-exclusive use a different code path to usermode ones; implement this missing code, in a similar way to the 32 bit version. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: Fix incorrect type for value argument to write_raw_cp_regPeter Maydell2014-02-201-1/+1
| | | | | | | | | | | | | | | | | | | | The write_raw_cp_reg's value argument should be a uint64_t, since that's what all its callers hand it and what all the functions it calls take. A (harmless) typo meant we were accidentally declaring it as int64_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Remove failure status return from read/write_raw_cp_regPeter Maydell2014-02-201-24/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | The read_raw_cp_reg and write_raw_cp_reg functions can now never fail (in fact they should never have failed previously unless there was a bug in a reginfo that meant no raw accessor was provided for a might-trap register). This allows us to clean up their prototypes so the write function returns void and the read function returns the value read, which in turn lets us simplify the callers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell2014-02-202-6/+0
| | | | | | | | | | | | | | | | Now that cpreg read and write functions can't fail and throw an exception, we can remove the code from the translator that synchronises the guest PC in case an exception is thrown. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell2014-02-206-238/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All cpreg read and write functions now return 0, so we can clean up their prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to This is a fairly mechanical change which makes only the bare minimum set of changes to the callers of read and write functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Convert miscellaneous reginfo structs to accessfnPeter Maydell2014-02-201-25/+19
| | | | | | | | | | | | | | | | Convert the remaining miscellaneous cases of reginfo read/write functions returning EXCP_UDEF to use an accessfn instead: TEEHBR, and the ATS address-translation operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Convert generic timer reginfo to accessfnPeter Maydell2014-02-201-56/+66
| | | | | | | | | | | | | | | | | | | | Convert the reginfo structs for the generic timer registers to use access functions rather than returning EXCP_UDEF from their read handlers. In some cases this allows us to remove a read handler completely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Convert performance monitor reginfo to accessfnPeter Maydell2014-02-201-42/+28
| | | | | | | | | | | | | | | | | | | | Convert the performance monitor reginfo definitions to use an accessfn rather than returning EXCP_UDEF from read and write functions. This also allows us to fix a couple of XXX cases where we weren't imposing the access restrictions on RAZ/WI or constant registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Split cpreg access checks out from read/write functionsPeter Maydell2014-02-205-4/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several of the system registers handled via the ARMCPRegInfo mechanism have access trap control bits controlling whether the registers are accessible to lower privilege levels. Replace the existing mechanism (allowing the read and write functions to return EXCP_UDEF if access is denied) with a dedicated "check access rights" function pointer in the ARMCPRegInfo. This will allow us to simplify some of the register definitions, which no longer need read/write functions purely to handle the access checks. We take the opportunity to define the return value from the access checking function in a way that allows us to set the correct exception syndrome information for exceptions taken to AArch64 (which may need to distinguish access failures due to a configurable trap or enable from other kinds of access failure). This commit defines the new mechanism but does not move any of the registers across to use it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Stop underdecoding ARM946 PRBS registersPeter Maydell2014-02-201-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM946 has 8 PRBS (protection region base and size) registers. Currently we implement these with a CP_ANY reginfo; however this underdecodes (since there are 16 possible values of CRm but only 8 registers) and we catch the invalid values in the read and write functions. However this causes issues with migration since we only migrate the first of a wildcard register set, so we only migrate c6_region[0]. It also makes it awkward to pull reginfo access checks out into their own function. Avoid all these problems by just defining separate reginfo structs for each of the 8 registers; this also lets us avoid having any read or write functions and will result in more efficient direct field accesses from generated code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell2014-02-202-1/+19
| | | | | | | | | | | | | | | | | | | | | | Log guest attempts to access unimplemented system registers via the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit instruction sets). This is particularly useful for debugging problems where the guest is trying to use a system register that QEMU doesn't implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Remove unused ARMCPUState sr substructPeter Maydell2014-02-201-5/+0
| | | | | | | | | | | | | | | | | | Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is a hangover from the original separate system register implementation used by the SuSE linux-user-mode-only AArch64 target. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Restrict check_ap() use of S and R bits to v6 and earlierPeter Maydell2014-02-201-0/+3
| | | | | | | | | | | | | | | | | | | | The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier. In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard the use of them in check_ap() so that we don't get incorrect results for ARMv8 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * target-arm: Define names for SCTLR bitsPeter Maydell2014-02-203-9/+61
| | | | | | | | | | | | | | | | | | The SCTLR is full of bits for enabling or disabling various things, and so there are many places in the code which check if certain bits are set. Define some named constants for the SCTLR bits so these checks are easier to read. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUsPeter Maydell2014-02-201-1/+15
| | | | | | | | | | | | | | | | Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_* constant to include all the ones currently supported by the kernel headers we are using. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: A64: Implement remaining 3-same instructionsPeter Maydell2014-02-205-4/+130
| | | | | | | | | | | | | | | | | | Implement the remaining instructions in the SIMD 3-reg-same and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE, FACGT, FMLA and FMLS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * softfloat: Support halving the result of muladd operationPeter Maydell2014-02-202-0/+41
| | | | | | | | | | | | | | | | | | | | | | The ARMv8 instruction set includes a fused floating point reciprocal square root step instruction which demands an "(x * y + z) / 2" fused operation. Support this by adding a flag to the softfloat muladd operations which requests that the result is halved before rounding. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement floating point pairwise insnsAlex Bennée2014-02-201-38/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the floating-point pairwise operations FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the code which was previously handling only integer pairwise operations, and push the integer-specific decode and handling of unallocated cases up one level in the call tree, so we can also call it from the floating-point section of the decoder. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée2014-02-203-12/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds all forms of the SIMD floating point and set instructions: FCM(GT|GE|EQ|LE|LT) Most of the heavy lifting is done by either the existing neon helpers or some new helpers for the 64bit double cases. Most of the code paths are common although the 2misc versions are a little special as they compare against zero. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [PMM: fixed some minor bugs, added the 2-misc-scalar encoding] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement scalar three different instructionsPeter Maydell2014-02-201-1/+94
| | | | | | | | | | | | | | | | Implement the scalar three different instruction group: it only has three instructions in it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell2014-02-201-33/+82
| | | | | | | | | | | | | | | | | | Implement the SIMD scalar indexed instructions. The encoding here is nearly identical to the vector indexed grouping, so we combine the two. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement long vector x indexed insnsPeter Maydell2014-02-201-5/+139
| | | | | | | | | | | | | | | | Implement the 'long' operations in the vector x indexed element category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell2014-02-203-1/+275
| | | | | | | | | | | | | | | | Implement all the SIMD vector x indexed element instructions in the subcategory which are not 'long' ops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * hw/intc/arm_gic: Fix NVIC assertion failurePeter Maydell2014-02-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 40d225009ef accidentally changed the behaviour of gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs, so this meant we hit an assertion: gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed. Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
* | Merge remote-tracking branch ↵Peter Maydell2014-02-211-33/+26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/stefanha/tags/qtest-monitor-process-pull-request' into staging qtest resource cleanup pull request # gpg: Signature made Wed 19 Feb 2014 14:46:34 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/qtest-monitor-process-pull-request: qtest: kill QEMU process on g_assert() failure qtest: make QEMU our direct child process qtest: drop unused child_pid field Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | qtest: kill QEMU process on g_assert() failureStefan Hajnoczi2014-02-191-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QEMU process stays running if the test case fails. This patch fixes the leak by installing a SIGABRT signal handler which invokes qtest_end(). Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
| * | qtest: make QEMU our direct child processStefan Hajnoczi2014-02-191-29/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qtest_init() cannot use exec*p() to launch QEMU since the exec*p() functions take an argument array while qtest_init() takes char *extra_args. Therefore we execute /bin/sh -c <command-line> and let the shell parse the argument string. This left /bin/sh as our child process and our child's child was QEMU. We still want QEMU's pid so the -pidfile option was used to let QEMU report its pid. The pidfile needs to be unlinked when the test case exits or fails. In other words, the pidfile creates a new problem for us! Simplify all this using the shell 'exec' command. It allows us to replace the /bin/sh process with QEMU. Then we no longer need to use -pidfile because we already know our fork child's pid. Note: Yes, it seems silly to exec /bin/sh when we could just exec QEMU directly. But remember qtest_init() takes a single char *extra_args command-line fragment instead of a real argv[] array, so we need /bin/sh's argument parsing behavior. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
| * | qtest: drop unused child_pid fieldStefan Hajnoczi2014-02-191-2/+0
| |/ | | | | | | | | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
* | Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell2014-02-219-65/+219
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Tracing pull request # gpg: Signature made Wed 19 Feb 2014 15:42:20 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: trace-events: Fix typo in "offset" Add ust generated files to .gitignore Update documentation for LTTng ust tracing Adapt Makefiles to the new LTTng ust interface Modified the tracetool framework for LTTng 2.x Fix configure script for LTTng 2.x Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | trace-events: Fix typo in "offset"Kevin Wolf2014-02-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | s/offet/offset/ Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | Add ust generated files to .gitignoreMohamad Gebai2014-02-191-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Mohamad Gebai <mohamad.gebai@polymtl.ca> Reviewed-by: Alex Bennée <alex@bennee.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | Update documentation for LTTng ust tracingMohamad Gebai2014-02-191-0/+36
| | | | | | | | | | | | | | | | | | Signed-off-by: Mohamad Gebai <mohamad.gebai@polymtl.ca> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | Adapt Makefiles to the new LTTng ust interfaceMohamad Gebai2014-02-192-0/+30
| | | | | | | | | | | | | | | | | | | | | Add generation of new files for LTTng ust. Signed-off-by: Mohamad Gebai <mohamad.gebai@polymtl.ca> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | Modified the tracetool framework for LTTng 2.xMohamad Gebai2014-02-193-56/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * A new format is required to generate definitions for ust tracepoints. Files ust_events_h.py and ust_events_c.py define common macros, while new function ust_events_h in events.py does the actual definition of each tracepoint. * ust.py generates the new interface for calling userspace tracepoints with LTTng 2.x, replacing trace_name(args) to tracepoint(name, args). * As explained in ust_events_c.py, -Wredundant-decls gives a warning when compiling with gcc 4.7 or older. This is specific to lttng-ust so for now use a pragma clause to avoid getting a warning. Signed-off-by: Mohamad Gebai <mohamad.gebai@polymtl.ca> Reviewed-by: Alex Bennée <alex@bennee.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
OpenPOWER on IntegriCloud