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* hw/vfio/pci: rename group_list into vfio_group_listEric Auger2014-12-221-11/+11
| | | | | | | better fit in the rest of the namespace Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/vfio/pci: split vfio_get_deviceEric Auger2014-12-222-57/+83
| | | | | | | | | | | | | vfio_get_device now takes a VFIODevice as argument. The function is split into 2 parts: vfio_get_device which is generic and vfio_populate_device which is bus specific. 3 new fields are introduced in VFIODevice to store dev_info. vfio_put_base_device is created. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/vfio/pci: Introduce VFIORegionEric Auger2014-12-222-94/+103
| | | | | | | | | | | | | | This structure is going to be shared by VFIOPCIDevice and VFIOPlatformDevice. VFIOBAR includes it. vfio_eoi becomes an ops of VFIODevice specialized by parent device. This makes possible to transform vfio_bar_write/read into generic vfio_region_write/read that will be used by VFIOPlatformDevice too. vfio_mmap_bar becomes vfio_map_region Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/vfio/pci: handle reset at VFIODeviceEric Auger2014-12-221-30/+63
| | | | | | | | | | | | | Since we can potentially have both PCI and platform devices in the same VFIO group, this latter now owns a list of VFIODevices. A unified reset handler, vfio_reset_handler, is registered, looping through this VFIODevice list. 2 specialized operations are introduced (vfio_compute_needs_reset and vfio_hot_reset_multi): they allow to implement type specific behavior. also reset_works and needs_reset VFIOPCIDevice fields are moved into VFIODevice. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/vfio/pci: add type, name and group fields in VFIODeviceEric Auger2014-12-221-9/+18
| | | | | | | | | | | | | | Add 3 new fields in the VFIODevice struct. Type is set to VFIO_DEVICE_TYPE_PCI. The type enum value will later be used to discriminate between VFIO PCI and platform devices. The name is set to domain:bus:slot:function. Currently used to test whether the device already is attached to the group. Later on, the name will be used to simplify all traces. The group is simply moved from VFIOPCIDevice to VFIODevice. Signed-off-by: Eric Auger <eric.auger@linaro.org> [Fix g_strdup_printf() usage] Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/vfio/pci: introduce minimalist VFIODevice with fdEric Auger2014-12-191-54/+63
| | | | | | | | | | | | | Introduce a new base VFIODevice strcut that will be used by both PCI and Platform VFIO device. Move VFIOPCIDevice fd field there. Obviously other fields from VFIOPCIDevice will be moved there but this patch file is introduced to ease the review. Also vfio_mask_single_irqindex, vfio_unmask_single_irqindex, vfio_disable_irqindex now take a VFIODevice handle as argument. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/vfio/pci: generalize mask/unmask to any IRQ indexEric Auger2014-12-191-10/+10
| | | | | | | | | | | | To prepare for platform device introduction, rename vfio_mask_intx and vfio_unmask_intx into vfio_mask_single_irqindex and respectively unmask_single_irqindex. Also use a nex index parameter. With that name and prototype the function will be usable for other indexes than VFIO_PCI_INTX_IRQ_INDEX. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* hw/vfio/pci: Rename VFIODevice into VFIOPCIDeviceEric Auger2014-12-191-104/+106
| | | | | | | This prepares for the introduction of VFIOPlatformDevice Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* vfio: move hw/misc/vfio.c to hw/vfio/pci.c Move vfio.h into include/hw/vfioKim Phillips2014-12-198-5/+8
| | | | | | | | This is done in preparation for the addition of VFIO platform device support. Signed-off-by: Kim Phillips <kim.phillips@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* vfio: fix adding memory listener to the right address spaceFrank Blaschka2014-12-191-1/+1
| | | | | | | | | Depending on the device, container->space->as contains the valid AddressSpace. Using address_space_memory breaks devices sitting behind an iommu (and using a separate address space). Signed-off-by: Frank Blaschka <blaschka@linux.vnet.ibm.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* vfio: migration to trace pointsEric Auger2014-12-192-198/+280
| | | | | | | | This patch removes all DPRINTF and replace them by trace points. A few DPRINTF used in error cases were transformed into error_report. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20141216-1' into ↵Peter Maydell2014-12-174-19/+42
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging cirrus hwcursor fixes. set secondary-vga category. # gpg: Signature made Tue 16 Dec 2014 14:44:09 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vga-20141216-1: vga: set catagory bit for secondary vga device move hw cursor pos from cirrus to vga cirrus: Force use of shadow pixmap when HW cursor is enabled vga: Add mechanism to force the use of a shadow surface Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * vga: set catagory bit for secondary vga deviceGonglei2014-12-161-0/+1
| | | | | | | | | | Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * move hw cursor pos from cirrus to vgaGerd Hoffmann2014-12-162-16/+17
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| * cirrus: Force use of shadow pixmap when HW cursor is enabledBenjamin Herrenschmidt2014-12-161-1/+8
| | | | | | | | | | | | | | | | The HW cursor cannot be painted on a shared surface. This fixes HW cursor display in Windows NT 4.0 and Windows 98. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * vga: Add mechanism to force the use of a shadow surfaceBenjamin Herrenschmidt2014-12-162-2/+16
| | | | | | | | | | | | | | | | This prevents surface sharing which will be necessary to fix cirrus HW cursor support. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch 'remotes/xtensa/tags/20141217-xtensa' into stagingPeter Maydell2014-12-1710-362/+426
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xtensa updates for 2.3: - fix cross-page opcode handling; - move window overflow exception generation decision to translation phase; - don't generate dead code after privilege, window overflow or coprocessor exception; - add monitor command 'info opcount' for dumping TCG opcode counters. # gpg: Signature made Wed 17 Dec 2014 02:57:01 GMT using RSA key ID F83FA044 # gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" * remotes/xtensa/tags/20141217-xtensa: target-xtensa: don't generate dead code target-xtensa: record available window in TB flags target-xtensa: test cross-page opcode target-xtensa: fix translation for opcodes crossing page boundary tcg: add separate monitor command to dump opcode counters Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-xtensa: don't generate dead codeMax Filippov2014-12-171-279/+321
| | | | | | | | | | | | | | | | | | | | | | | | Don't generate TCG operations when privilege, register window or coprocessor checks fail. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * | target-xtensa: record available window in TB flagsMax Filippov2014-12-174-62/+42
| | | | | | | | | | | | | | | | | | | | | | | | Record last valid 4-register window pane number in TB flags so that a window overflow exception throw point is known at the translation time. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * | target-xtensa: test cross-page opcodeMax Filippov2014-12-171-13/+13
| | | | | | | | | | | | | | | | | | Alter cross-page TB test to also test cross-page opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| * | target-xtensa: fix translation for opcodes crossing page boundaryMax Filippov2014-12-171-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If TB ends with an opcode that crosses page boundary and the following page is not executable then EPC1 for the code fetch exception wrongly points at the beginning of the TB. Always treat instruction that crosses page boundary as a separate TB. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| * | tcg: add separate monitor command to dump opcode countersMax Filippov2014-12-175-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently 'info jit' outputs half of the information to monitor and the rest to qemu log. Dumping opcode counts to monitor as a part of 'info jit' command doesn't sound useful. Add new monitor command 'info opcount' that only dumps opcode counters. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
* | | Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141216' into stagingPeter Maydell2014-12-1711-392/+620
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/lalrae/tags/mips-20141216: (30 commits) target-mips: remove excp_names[] from linux-user as it is unused disas/mips: disable unused mips16_to_32_reg_map[] disas/mips: remove unused mips_msa_control_names_numeric[32] target-mips: convert single case switch into if statement target-mips: Fix DisasContext's ulri member initialization target-mips: Use local float status pointer across MSA macros target-mips: Add missing calls to synchronise SoftFloat status linux-user: Use the 5KEf processor for 64-bit emulation target-mips: Also apply the CP0.Status mask to MTTC0 target-mips: gdbstub: Clean up FPU register handling target-mips: Correct 32-bit address space wrapping target-mips: Tighten ISA level checks target-mips: Fix CP0.Config3.ISAOnExc write accesses target-mips: Output CP0.Config2-5 in the register dump target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP target-mips: Correct the writes to Status and Cause registers via gdbstub target-mips: Correct the handling of writes to CP0.Status for MIPSr6 target-mips: Correct MIPS16/microMIPS branch size calculation target-mips: Restore the order of helpers target-mips: Remove unused `FLOAT_OP' macro ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target-mips: remove excp_names[] from linux-user as it is unusedLeon Alrae2014-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
| * | | disas/mips: disable unused mips16_to_32_reg_map[]Leon Alrae2014-12-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This array is used by print_mips16_insn_arg() which is guarded by #if 0. Therefore doing the same with the array as it generates clang warnings. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | disas/mips: remove unused mips_msa_control_names_numeric[32]Leon Alrae2014-12-161-7/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target-mips: convert single case switch into if statementLeon Alrae2014-12-161-3/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
| * | | target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki2014-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set DisasContext's ulri member to 0 or 1 as with other bool members. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Use local float status pointer across MSA macrosMaciej W. Rozycki2014-12-161-35/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce line wrapping throughout MSA helper macros by using a local float status pointer rather than referring to the float status through the environment each time. No functional change. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-164-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing calls to synchronise the SoftFloat status with the CP1.FSCR: + for the rounding and flush-to-zero modes upon processor reset, + for the flush-to-zero mode on FSCR updates through the GDB stub. Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE macro. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | linux-user: Use the 5KEf processor for 64-bit emulationMaciej W. Rozycki2014-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the 20Kc original MIPS64 ISA processor used for 64-bit user emulation with the 5KEf processor that implements the MIPS64r2 ISA, complementing the choice of the 24Kf processor for 32-bit emulation. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki2014-12-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make CP0.Status writes made with the MTTC0 instruction respect this register's mask just like all the other places. Also preserve the current values of masked out bits. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: gdbstub: Clean up FPU register handlingMaciej W. Rozycki2014-12-161-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite the FPU register access parts of `mips_cpu_gdb_read_register' and `mips_cpu_gdb_write_register' for consistency between each other. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2014-12-162-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the address space is unconditionally wrapped on 32-bit processors, that is ones that do not implement at least the MIPS III ISA. Also make MIPS16 SAVE and RESTORE instructions use address calculation rather than plain arithmetic operations for stack pointer manipulation so that their semantics for stack accesses follows the architecture specification. That in particular applies to user software run on 64-bit processors with the CP0.Status.UX bit clear where the address space is wrapped to 32 bits. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Tighten ISA level checksMaciej W. Rozycki2014-12-163-15/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tighten ISA level checks down to MIPS II that many of our instructions are missing. Also make sure any 64-bit instruction enables are only applied to 64-bit processors, that is ones that implement at least the MIPS III ISA. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki2014-12-163-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors. This bit is mandatory for any processor that implements the microMIPS instruction set. This bit is r/w for processors that implement both the standard MIPS and the microMIPS instruction set. This bit is r/o and hardwired to 1 if only the microMIPS instruction set is implemented. There is no other bit ever writable in CP0.Config3 so defining a corresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I think an overkill. Therefore make the ability to write the bit rely on the presence of ASE_MICROMIPS set in the instruction flags. The read-only case of the microMIPS instruction set being implemented only can be added when we add support for such a configuration. We do not currently have such support, we have no instruction flag that would control the presence of the standard MIPS instruction set nor any associated code in instruction decoding. This change is needed to boot a microMIPS Linux kernel successfully, otherwise it hangs early on as interrupts are enabled and then the exception handler invoked loops as its first instruction is interpreted in the wrong execution mode and triggers another exception right away. And then over and over again. We already check the current setting of the CP0.Config3.ISAOnExc in `set_hflags_for_handler' to set the ISA bit correctly on the exception handler entry so it is the ability to set it that is missing only. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki2014-12-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include CP0.Config2 through CP0.Config5 registers in the register dump produced with the `info registers' monitor command. Align vertically with the registers already output. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki2014-12-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by using register addition operations. This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying `rs' to `rd' verbatim. This is not the case with OPC_ADDIU where a sign-extension from bit #31 is made, unless in the uninteresting case of `rs' being 0, losing the upper 32 bits of the value copied for any proper 64-bit values. This also serves as an optimization as one op is produced in generated code rather than two (again, unless `rs' is 0, where it doesn't change anything). Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki2014-12-163-86/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make writes to CP0.Status and CP0.Cause have the same effect as executing corresponding MTC0 instructions would in Kernel Mode. Also ignore writes in the user emulation mode. Currently for requests from the GDB stub we write all the bits across both registers, ignoring any read-only locations, and do not synchronise the environment to evaluate side effects. We also write these registers in the user emulation mode even though a real kernel presents them as read only. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki2014-12-161-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct these issues with the handling of CP0.Status for MIPSr6: * only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that is for processors that do implement Supervisor Mode, let the bit pattern be written to CP0.Status.UM:R0 freely (of course the value written to read-only CP0.Status.R0 will be discarded anyway); this is in accordance to the relevant architecture specification[1], * check the newly written pattern rather than the current contents of CP0.Status for the KSU bits being 0b11, * use meaningful macro names to refer to CP0.Status bits rather than magic numbers. References: [1] "MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64 Privileged Resource Architecture", MIPS Technologies, Inc., Document Number: MD00091, Revision 6.00, March 31, 2014, Table 9.45 "Status Register Field Descriptions", pp. 210-211. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki2014-12-162-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct MIPS16/microMIPS branch size calculation in PC adjustment needed: - to set the value of CP0.ErrorEPC at the entry to the reset exception, - for the purpose of branch reexecution in the context of device I/O. Follow the approach taken in `exception_resume_pc' for ordinary, Debug and NMI exceptions. MIPS16 and microMIPS branches can be 2 or 4 bytes in size and that has to be reflected in calculation. Original MIPS ISA branches, which is where this code originates from, are always 4 bytes long, just as all original MIPS ISA instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Restore the order of helpersMaciej W. Rozycki2014-12-161-159/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restore the order of helpers that used to be: unary operations (generic, then MIPS-specific), binary operations (generic, then MIPS-specific), compare operations. At one point FMA operations were inserted at a random place in the file, disregarding the preexisting order, and later on even more operations sprinkled across the file. Revert the mess by moving FMA operations to a new ternary class inserted after the binary class and move the misplaced unary and binary operations to where they belong. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki2014-12-161-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the `FLOAT_OP' macro, unused since commit b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for the MIPS FPU emulation.]. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki2014-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the call to `update_fcr31' in `helper_float_cvtw_s' after the exception flag check, for consistency with the remaining helpers that do it last too. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki2014-12-161-5/+8
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Fix formatting in `mips_defs'Maciej W. Rozycki2014-12-161-19/+21
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki2014-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Enable vectored interrupt support for the 74Kf CPUMaciej W. Rozycki2014-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable vectored interrupt support for the 74Kf CPU, reflecting hardware. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processorsMaciej W. Rozycki2014-12-161-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the M14K and M14Kc processors from MIPS Technologies that are the original implementation of the microMIPS ISA. They are dual instruction set processors, implementing both the microMIPS and the standard MIPSr32 ISA. These processors correspond to the M4K and 4KEc CPUs respectively, except with support for the microMIPS instruction set added, support for the MCU ASE added and two extra interrupt lines, making a total of 8 hardware interrupts plus 2 software interrupts. The remaining parts of the microarchitecture, in particular the pipeline, stayed unchanged. The presence of the microMIPS ASE is is reflected in the configuration added. We currently have no support for the MCU ASE, including in particular the ACLR, ASET and IRET instructions in either encoding, and we have no support for the extra interrupt lines, including bits in CP0.Status and CP0.Cause registers, so these features are not marked, making our support diverge from real hardware. Signed-off-by: Sandra Loosemore <sandra@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * | | target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki2014-12-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the data type used for the CP0.Config4 and CP0.Config5 registers and their mask signed, for consistency with the remaining 32-bit CP0 registers, like CP0.Config0, etc. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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