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* target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno2012-10-311-48/+37
| | | | | | | | | The result of a division by 0, or a division of INT_MIN by -1 in the signed case, is unpredictable. Just replace 0 by 1 in that case so that it doesn't trigger a floating point exception on the host. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: implement movn/movz using movcondAurelien Jarno2012-10-311-15/+12
| | | | | | | | Avoid the branches in movn/movz implementation and replace them with movcond. Also update a wrong command. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: don't use local temps for store conditionalAurelien Jarno2012-10-311-5/+6
| | | | | | | | | | | | Store conditional operations only need local temps in user mode. Fix the code to use temp local only in user mode, this spares two memory stores in system mode. At the same time remove a wrong a wrong copied & pasted comment, store operations don't have a register destination. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: implement unaligned loads using TCGAurelien Jarno2012-10-313-159/+62
| | | | | | | | | | | | | Load/store from helpers should be avoided as they are quite inefficient. Rewrite unaligned loads instructions using TCG and aligned loads. The number of actual loads operations to implement an unaligned load instruction is reduced from up to 8 to 1. Note: As we can't rely on shift by 32 or 64 undefined behaviour, the code loads already shift by one constants. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: simplify load/store microMIPS helpersAurelien Jarno2012-10-311-64/+9
| | | | | | | | | load/store microMIPS helpers are reinventing the wheel. Call do_lw, do_ll, do_sw and do_sl instead of using a macro calling the cpu_* load/store functions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: optimize load operationsAurelien Jarno2012-10-311-4/+12
| | | | | | | Only allocate t1 when needed. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: cleanup load/store operationsAurelien Jarno2012-10-311-64/+35
| | | | | | | | Load/store operations use macros for historical reasons. Now that there is no point in keeping them, replace them by direct calls to qemu_ld/st. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: restore CPU state after an FPU exceptionAurelien Jarno2012-10-311-90/+95
| | | | | | | | | | | Rework *raise_exception*() functions so that they can be called from other helpers, passing the return address as an argument. Use do_raise_exception() function in update_fcr31() to correctly restore the CPU state after an FPU exception. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: use softfloat constants when possibleAurelien Jarno2012-10-311-48/+44
| | | | | | | | | | | | | | softfloat already has a few constants defined, use them instead of redefining them in target-mips. Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and FP_TO_INT64_OVERFLOW as even if they have the same value, they are technically different (and defined differently in the MIPS ISA). Remove the unused constants. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: cleanup float to int conversion helpersAurelien Jarno2012-10-311-39/+79
| | | | | | | | | | Instead of accessing the flags from the floating point control register after updating it, read the softfloat flags. This is just code cleanup and should not change the behaviour. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix FPU exceptionsAurelien Jarno2012-10-311-13/+19
| | | | | | | | | | | | | | For each FPU instruction that can trigger an FPU exception, to call call update_fcr31() after. Remove the manual NaN assignment in case of float to float operation, as softfloat is already taking care of that. However for float to int operation, the value has to be changed to the MIPS one. In the cvtpw_ps case, the two registers have to be handled separately to guarantee a correct final value in both registers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: keep softfloat exception set to 0 between instructionsAurelien Jarno2012-10-311-63/+10
| | | | | | | | | Instead of clearing the softfloat exception flags before each floating point instruction, reset them to 0 in update_fcr31() when an exception is detected. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno2012-10-313-105/+64
| | | | | | | | | | Use the new softfloat floatXX_muladd() functions to implement the madd, msub, nmadd and nmsub instructions. At the same time replace the name of the helpers by the name of the instruction, as the only reason for the previous names was to keep the macros simple. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* softfloat: implement fused multiply-add NaN propagation for MIPSAurelien Jarno2012-10-311-0/+27
| | | | | | | | | Add a pickNaNMulAdd function for MIPS, implementing NaN propagation rules for MIPS fused multiply-add instructions. Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: do not save CPU state when using retranslationAurelien Jarno2012-10-311-20/+0
| | | | | | | | When the CPU state after a possible retranslation is going to be handled through code retranslation, we don't need to save the CPU state before. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: correctly restore btarget upon exceptionAurelien Jarno2012-10-311-0/+11
| | | | | | | | When the CPU state is restored through retranslation after an exception, btarget should also be restored. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: don't remove op if output needs to be synced to memoryAurelien Jarno2012-10-311-4/+4
| | | | | | | | | | | Commit 9c43b68de628a1e2cba556adfb71c17028eb802e do not correctly check for dead outputs when they need to be synced to memory in case of half-dead operations. Fix that by applying the same pattern than for the default case. Tested-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-alpha: Use TCG_CALL_NO_WGRichard Henderson2012-10-311-10/+10
| | | | | | | Mark helper functions that raise exceptions, but otherwise do not change TCG register state, with TCG_CALL_NO_WG. Signed-off-by: Richard Henderson <rth@twiddle.net>
* chardev: Use timer instead of bottom-half to postpone open eventJan Kiszka2012-10-313-12/+13
| | | | | | | | | | | | | | As the block layer may decide to flush bottom-halfs while the machine is still initializing (e.g. to read geometry data from the disk), our postponed open event may be processed before the last frontend registered with a muxed chardev. Until the semantics of BHs have been clarified, use an expired timer to achieve the same effect (suggested by Paolo Bonzini). This requires to perform the alarm timer initialization earlier as otherwise timer subsystem can be used before being ready. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
* target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno2012-10-311-36/+0
| | | | | | | | All switch() decoding instruction have a default entry, so it is possible to have unused enum entries. Remove conditional definitions of MIPS64 opcode enums, as it only makes the code less readable. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Change TODO fileJia Liu2012-10-311-2/+1
| | | | | | | Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP testcasesJia Liu2012-10-31487-0/+19151
| | | | | | | Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP processorsJia Liu2012-10-311-0/+52
| | | | | | | Add 74kf and mips64dspr2-generic-cpu model for test. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP accumulator instructionsJia Liu2012-10-313-0/+995
| | | | | | | Add MIPS ASE DSP Accumulator and DSPControl Access instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP compare-pick instructionsJia Liu2012-10-313-0/+635
| | | | | | | Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP bit/manipulation instructionsJia Liu2012-10-313-0/+311
| | | | | | | Add MIPS ASE DSP Bit/Manipulation instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP multiply instructionsJia Liu2012-10-313-0/+1499
| | | | | | | Add MIPS ASE DSP Multiply instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP GPR-based shift instructionsJia Liu2012-10-313-0/+618
| | | | | | | Add MIPS ASE DSP GPR-Based Shift instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP arithmetic instructionsJia Liu2012-10-313-3/+1812
| | | | | | | Add MIPS ASE DSP Arithmetic instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP load instructionsJia Liu2012-10-311-0/+88
| | | | | | | Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP branch instructionsJia Liu2012-10-311-0/+36
| | | | | | | Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu2012-10-311-27/+95
| | | | | Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP resources access checkJia Liu2012-10-314-2/+53
| | | | | | | Add MIPS ASE DSP resources access check. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Add ASE DSP internal functionsJia Liu2012-10-312-1/+1064
| | | | | | | Add internal functions using by MIPS ASE DSP instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tap-win32: stubs to fix win32 buildMichael S. Tsirkin2012-10-301-0/+10
| | | | | | | | Add missing stubs to win32 to fix link failure. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tests/tcg: fix unused result warningsCatalin Patulea2012-10-302-7/+22
| | | | | | | | With i386-linux-user target on x86_64 host, this does not introduce any new test failures. Signed-off-by: Catalin Patulea <catalinp@google.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* configure: use -Wwombat to test whether gcc recognizes -Wno-wombatPeter Maydell2012-10-301-1/+5
| | | | | | | | | | | | | | | | gcc will silently accept unrecognized -Wno-wombat warning suppression options (it only mentions them if it has to print a compiler warning for some other reason). Since we already run a check for whether gcc recognizes the warning options we use, we can easily make this use the positive sense of the option when checking for support for the suppression option. This doesn't have any effect except that it avoids gcc emitting extra messages about unrecognized command line options when it is printing other warning messages. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Revert setting cpu_dst to gen_dest_gprRichard Henderson2012-10-301-1/+1
| | | | | | | | | | | | There is some read-after-write error within the OP=2 insns which prevents setting cpu_dst to the real output register. Until this is found and fixed, always write to a temporary first. Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge branch 'qspi.2' of git://developer.petalogix.com/public/qemuBlue Swirl2012-10-303-50/+340
|\ | | | | | | | | | | | | * 'qspi.2' of git://developer.petalogix.com/public/qemu: xilinx_zynq: added QSPI controller xilinx_spips: Generalised to model QSPI m25p80: Support for Quad SPI
| * xilinx_zynq: added QSPI controllerPeter Crosthwaite2012-10-291-12/+28
| | | | | | | | | | | | | | | | Added the QSPI controller to the Zynq. 4 SPI devices are attached to allow modelling of the different geometries. E.G. Dual parallel and dual stacked mode can both be tested with this one arrangement. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * xilinx_spips: Generalised to model QSPIPeter Crosthwaite2012-10-291-34/+255
| | | | | | | | | | | | | | | | | | Extended the xilinx spips controller to model QSPI as well. Paremeterised the operational difference with the normal spi controller (num_ss_bits, width of the tx/rx fifo heads etc.). Multiple bus functionality is modelled (needed for QSPI dual parallel mode. LQSPI is modelled. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| * m25p80: Support for Quad SPIPeter Crosthwaite2012-10-291-4/+57
| | | | | | | | | | | | | | | | | | Added the Quad mode read and write commands. Data remains serialized on a single wire, i.e. the quad mode instructions just behave the same as single mode, with the expection of modelling the varying number of dummy/mode bytes between the address bytes and the first data word. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* | Merge branch 's390-for-upstream' of git://repo.or.cz/qemu/agrafAurelien Jarno2012-10-3012-84/+1315
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 's390-for-upstream' of git://repo.or.cz/qemu/agraf: s390: sclp ascii console support s390: sclp signal quiesce support s390: sclp event support s390: sclp base support s390: use sync regs for register transfer s390/kvm_stat: correct sys_perf_event_open syscall number s390x: fix -initrd in virtio machine
| * | s390: sclp ascii console supportHeinz Graalfs2012-10-292-1/+307
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code adds console support by implementing SCLP's ASCII Console Data event. This is the same console as LPARs ASCII console or z/VMs sysascii. The console can be specified manually with something like -chardev stdio,id=charconsole0 -device sclpconsole,chardev=charconsole0,id=console0 Newer kernels will autodetect that console and prefer that over virtio console. When data is received from the character layer it creates a service interrupt to trigger a Read Event Data command from the guest that will pick up the received character byte-stream. When characters are echo'ed by the linux guest a Write Event Data occurs which is forwarded by the Event Facility to the console that supports a corresponding mask value. Console resizing is not supported. The character layer byte-stream is buffered using a fixed size iov buffer. Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | s390: sclp signal quiesce supportHeinz Graalfs2012-10-293-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the sclp signal quiesce event via the SCLP Event Facility. This allows to gracefully shutdown a guest by using system_powerdown notifiers. It creates a service interrupt that will trigger a Read Event Data command from the guest. This code will then add an event that is interpreted by linux guests as ctrl-alt-del. Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | s390: sclp event supportHeinz Graalfs2012-10-296-2/+579
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several SCLP features are considered to be events. Those events don't provide SCLP commands on their own, instead they are all based on Read Event Data, Write Event Data, Write Event Mask and the service interrupt. Follow-on patches will provide SCLP's Signal Quiesce (via system_powerdown) and the ASCII console. Further down the road the sclp line mode console and configuration change events (e.g. cpu hotplug) can be implemented. Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | s390: sclp base supportHeinz Graalfs2012-10-296-60/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a more generic infrastructure for handling Service-Call requests on s390. Currently we only support a small subset of Read SCP Info directly in target-s390x. This patch provides the base infrastructure for supporting more commands and moves Read SCP Info. In the future we could add additional commands for hotplug, call home and event handling. Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | s390: use sync regs for register transferChristian Borntraeger2012-10-291-20/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer kernels provide the guest registers in kvm_run. Lets use those if available (i.e. the capability is set). This avoids ioctls on cpu_synchronize_state making intercepts faster. In addition, we have now the prefix register, the access registers the control registers up to date. This helps in certain cases, e.g. for resolving kernel module addresses with gdb on a guest. On return, we update the registers according to the level statement, i.e. we put all registers for KVM_PUT_FULL_STATE and _RESET_STATE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | s390/kvm_stat: correct sys_perf_event_open syscall numberHeinz Graalfs2012-10-291-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct sys_perf_event_open syscall number for s390 architecture - the hardcoded syscall number 298 is for x86 but should be different for other architectures. In case we figure out via /proc/cpuinfo that we are running on s390 the appropriate syscall number is used from map syscall_numbers; other architectures can extend this. Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | s390x: fix -initrd in virtio machineAlexander Graf2012-10-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using -initrd in the virtio machine, we need to indicate the initrd start and size inside the kernel image. These parameters need to be stored in native endianness. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Richard Henderson <rth@twiddle.net> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
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