hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	char/cadence_uart: Fix can_receive logic	Peter Crosthwaite	2014-01-08	1	-1/+9
*	char/cadence_uart: Remove TX timer & add TX FIFO state	Peter Crosthwaite	2014-01-08	1	-31/+13
*	char/cadence_uart: Define Missing SR/ISR fields	Peter Crosthwaite	2014-01-08	1	-0/+4
*	char/cadence_uart: Simplify status generation	Peter Crosthwaite	2014-01-08	1	-25/+8
*	char/cadence_uart: s/r_fifo/rx_fifo	Peter Crosthwaite	2014-01-08	1	-4/+4
*	char/cadence_uart: Fix reset.	Peter Crosthwaite	2014-01-08	1	-3/+4
*	char/cadence_uart: Add missing uart_update_state	Peter Crosthwaite	2014-01-08	1	-0/+1
*	char/cadence_uart: Mark struct fields as public/private	Peter Crosthwaite	2014-01-08	1	-0/+2
*	target-arm: Give the FPSCR rounding modes names	Alexander Graf	2014-01-08	2	-4/+13
*	target-arm: A64: Add support for floating point cond select	Claudio Fontana	2014-01-08	1	-1/+44
*	target-arm: A64: Add support for floating point conditional compare	Claudio Fontana	2014-01-08	1	-1/+34
*	target-arm: A64: Add support for floating point compare	Claudio Fontana	2014-01-08	3	-1/+113
*	target-arm: A64: Add fmov (scalar, immediate) instruction	Alexander Graf	2014-01-08	1	-1/+31
*	target-arm: A64: Add "Floating-point data-processing (3 source)" insns	Alexander Graf	2014-01-08	1	-1/+94
*	target-arm: A64: Add "Floating-point data-processing (2 source)" insns	Alexander Graf	2014-01-08	1	-1/+181
*	target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum	Peter Maydell	2014-01-08	4	-52/+20
*	target-arm: A64: Fix vector register access on bigendian hosts	Peter Maydell	2014-01-08	1	-34/+35
*	target-arm: A64: Add support for dumping AArch64 VFP register state	Alexander Graf	2014-01-08	1	-0/+16
*	default-configs: Add config for aarch64-linux-user	Peter Maydell	2014-01-08	1	-0/+3
*	.travis.yml: Add aarch64-* targets	Alex Bennée	2014-01-08	1	-0/+1
*	linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext	Will Newton	2014-01-08	1	-3/+7
*	linux-user: AArch64: define TARGET_CLONE_BACKWARDS	Claudio Fontana	2014-01-08	1	-0/+1
*	target-arm: A64: support for ld/st/cl exclusive	Michael Matz	2014-01-08	2	-6/+277
*	target-arm: Widen exclusive-access support struct fields to 64 bits	Peter Maydell	2014-01-08	4	-46/+64
*	target-arm: aarch64: add support for ld lit	Alexander Graf	2014-01-08	1	-2/+45
*	target-arm: A64: add support for conditional compare insns	Claudio Fontana	2014-01-08	1	-13/+60
*	target-arm: A64: add support for add/sub with carry	Claudio Fontana	2014-01-08	1	-2/+103
*	target-arm: Widen thread-local register state fields to 64 bits	Peter Maydell	2014-01-07	5	-13/+36
*	target-arm: A64: Implement minimal set of EL0-visible sysregs	Peter Maydell	2014-01-07	3	-1/+115
*	target-arm: A64: Implement MRS/MSR/SYS/SYSL	Peter Maydell	2014-01-07	1	-30/+82
*	target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder	Peter Maydell	2014-01-07	5	-12/+17
*	target-arm: Update generic cpreg code for AArch64	Peter Maydell	2014-01-04	3	-9/+211
*	target-arm: Pull "add one cpreg to hashtable" into its own function	Peter Maydell	2014-01-04	1	-42/+52
*	target-arm: A64: implement FMOV	Peter Maydell	2013-12-23	1	-1/+85
*	target-arm: A64: Add decoder skeleton for FP instructions	Peter Maydell	2013-12-23	1	-1/+169
*	target-arm: A64: implement SVC, BRK	Alexander Graf	2013-12-23	1	-2/+49
*	target-arm: A64: add support for 3 src data proc insns	Alexander Graf	2013-12-23	1	-2/+95
*	target-arm: A64: add support for move wide instructions	Alex Bennée	2013-12-23	1	-2/+49
*	target-arm: A64: add support for add, addi, sub, subi	Alex Bennée	2013-12-23	1	-6/+286
*	target-arm: A64: add support for ld/st with index	Alex Bennée	2013-12-23	1	-1/+124
*	target-arm: A64: add support for ld/st with reg offset	Alex Bennée	2013-12-23	1	-1/+143
*	target-arm: A64: add support for ld/st unsigned imm	Alex Bennée	2013-12-23	1	-1/+88
*	target-arm: A64: add support for ld/st pair	Peter Maydell	2013-12-23	1	-2/+277
*	PPC: Fix compilation with TCG debug	Alexander Graf	2013-12-22	1	-62/+81
*	Merge tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu	Aurelien Jarno	2013-12-21	3	-52/+50
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\| *	s390x/ioinst: CHSC has to set a condition code	Thomas Huth	2013-12-18	1	-0/+1
\| *	s390x/kvm: Fixed condition code for unknown SIGP orders	Thomas Huth	2013-12-18	1	-6/+11
\| *	s390x/kvm: Simplified the calculation of the SIGP order code	Thomas Huth	2013-12-18	1	-5/+3
\| *	s390x/kvm: Implemented SIGP START	Thomas Huth	2013-12-18	1	-0/+11
\| *	s390x/kvm: Fix coding style in handle_sigp()	Thomas Huth	2013-12-18	1	-12/+12