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* .travis.yml: Run make check for all targets, not just someDavid Gibson2015-10-081-9/+1
| | | | | | | | | | | | | | | | | | | ed173cb ".travis.yml: remove "make check" from main matrix" stopped running make check for all the Travis build targets for various reasons. It continued to run make check on one Travis build, which builds for a big list of all (? nearly all) our supported softmmu targets. Unfortunately, due to a spacing / quoting error it only actually builds for the alpha, arm, aarch64 and cris targets. Specifically, the list of targets is split over several lines. Even with YAML folding, this will leave spaces in the list, meaning $TARGETS won't have the value we need. I had a look at the YAML spec and I couldn't quickly see a way of splitting the list so that it doesn't end up with spaces, so this patch fixes the problem by putting the whole list on one huge line. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* hw: char: Remove unnecessary variableShraddha Barke2015-10-081-3/+1
| | | | | | | Compress lines and remove the variable. Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* hw: timer: Remove unnecessary variableShraddha Barke2015-10-081-3/+1
| | | | | | | Compress lines and remove the variable. Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* qapi: add missing @Marc-André Lureau2015-10-081-1/+1
| | | | | | Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* MAINTAINERS: Add NSIS file for W32, W64 hostsStefan Weil2015-10-081-0/+1
| | | | | | | The NSIS installer configuration is maintained by me. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-ppc: Remove unnecessary variableShraddha Barke2015-10-081-2/+1
| | | | | | | Compress lines and remove the variable. Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-microblaze: Remove unnecessary variableShraddha Barke2015-10-081-3/+1
| | | | | | | Compress lines and remove the variable. Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* s/cpu_get_real_ticks/cpu_get_host_ticks/Christopher Covington2015-10-087-20/+20
| | | | | | | | | | | This should help clarify the purpose of the function that returns the host system's CPU cycle count. Signed-off-by: Christopher Covington <cov@codeaurora.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> ppc portion Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* pc: check for underflow in load_linuxPaolo Bonzini2015-10-081-0/+4
| | | | | | | | If (setup_size+1)*512 is small enough, kernel_size -= setup_size can allocate a huge amount of memory. Avoid that. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* pci-assign: do not include sys/io.hPaolo Bonzini2015-10-081-1/+0
| | | | | | | | | This file does not exist on bionic libc and the functions it defines are in fact not used by pci-assign.c. Remove it. Reported-by: Houcheng Lin <houcheng@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* block/ssh: remove dead codePaolo Bonzini2015-10-081-4/+1
| | | | | | | | | | The "err" label cannot be reached with qp != NULL. Remove the free-ing of qp and avoid future regressions by removing the initializer. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> ACKed-by: Richard W.M. Jones <rjones@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* imx_serial: Generate interrupt on tx empty if enabledGuenter Roeck2015-10-081-1/+3
| | | | | | | | | | | | | Generate an interrupt if the tx buffer is empty and the tx empty interrupt is enabled. This fixes a problem seen when running a Linux image since Linux commit 55c3cb1358e ("serial: imx: remove unneeded imx_transmit_buffer() from imx_start_tx()"). Linux now waits for the tx empty interrupt before starting to send data, causing transmit stalls until there is an interrupt for another reason. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* sdhci: Change debug prints to compile unconditionallySai Pavan Boddu2015-10-081-18/+18
| | | | | | | | | | Conditional compilation hides few type mismatch warnings, fix it to compile unconditionally. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Suggested-by: Eric Blake <eblake@redhat.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* sdhci: use PRIx64 for uint64_t typeSai Pavan Boddu2015-10-081-2/+5
| | | | | | | | | Fix compile time warnings, because of type mismatch for unsigned long long type. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Add .dir-locals.el file to configure emacs coding styleDaniel P. Berrange2015-10-081-0/+2
| | | | | | | | | | | | | Some default emacs setups indent by 2 spaces and uses tabs which is counter to the QEMU coding style rules. Adding a .dir-locals.el file in the top level of the GIT repo will inform emacs about the QEMU coding style, and so assist contributors in avoiding common style mistakes before they submit patches. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into stagingPeter Maydell2015-10-0845-1492/+964
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do away with TB retranslation # gpg: Signature made Wed 07 Oct 2015 10:42:08 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20151007: (26 commits) tcg: Adjust CODE_GEN_AVG_BLOCK_SIZE tcg: Check for overflow via highwater mark tcg: Allocate a guard page after code_gen_buffer tcg: Emit prologue to the beginning of code_gen_buffer tcg: Remove tcg_gen_code_search_pc tcg: Remove gen_intermediate_code_pc tcg: Save insn data and use it in cpu_restore_state_from_tb tcg: Pass data argument to restore_state_to_opc tcg: Add TCG_MAX_INSNS target-*: Drop cpu_gen_code define tcg: Merge cpu_gen_code into tb_gen_code target-sparc: Add npc state to insn_start target-sparc: Remove gen_opc_jump_pc target-sparc: Split out gen_branch_n target-sparc: Tidy gen_branch_a interface target-cris: Mirror gen_opc_pc into insn_start target-sh4: Add flags state to insn_start target-s390x: Add cc_op state to insn_start target-mips: Add delayed branch state to insn_start target-i386: Add cc_op state to insn_start ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tcg: Adjust CODE_GEN_AVG_BLOCK_SIZERichard Henderson2015-10-071-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | At present, the "average" guestimate of TB size is way too small, leading to many unused entries in the pre-allocated TB array. For a guest with 1GB ram, we're currently allocating 256MB for the array. Survey arm, alpha, aarch64, ppc, sparc, i686, x86_64 guests running on x86_64 and ppc64 hosts and select a new average. The size of the array drops to 81MB with no more flushing than before. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Check for overflow via highwater markRichard Henderson2015-10-074-16/+40
| | | | | | | | | | | | | | | | | | | | | | | | We currently pre-compute an worst case code size for any TB, which works out to be 122kB. Since the average TB size is near 1kB, this wastes quite a lot of storage. Instead, check for overflow in between generating code for each opcode. The overhead of the check isn't measurable and wastage is minimized. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Allocate a guard page after code_gen_bufferRichard Henderson2015-10-071-91/+119
| | | | | | | | | | | | | | | | | | This will catch any overflow of the buffer. Add a native win32 alternative for alloc_code_gen_buffer; remove the malloc alternative. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Emit prologue to the beginning of code_gen_bufferRichard Henderson2015-10-072-26/+37
| | | | | | | | | | | | | | | | | | | | By putting the prologue at the end, we risk overwriting the prologue should our estimate of maximum TB size. Given the two different placements of the call to tcg_prologue_init, move the high water mark computation into tcg_prologue_init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Remove tcg_gen_code_search_pcRichard Henderson2015-10-072-42/+19
| | | | | | | | | | | | | | | | It's no longer used, so tidy up everything reached by it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-0722-736/+90
| | | | | | | | | | | | | | | | | | | | It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Save insn data and use it in cpu_restore_state_from_tbRichard Henderson2015-10-074-55/+140
| | | | | | | | | | | | | | | | We can now restore state without retranslation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-0722-66/+79
| | | | | | | | | | | | | | | | | | | | The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-0720-17/+95
| | | | | | | | | | | | | | | | Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Drop cpu_gen_code defineRichard Henderson2015-10-0716-16/+0
| | | | | | | | | | | | | | | | This symbol no longer exists. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Merge cpu_gen_code into tb_gen_codeRichard Henderson2015-10-072-74/+59
| | | | | | | | | | | | | | | | As it's only caller, this tidies things a bit. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Add npc state to insn_startRichard Henderson2015-10-072-1/+7
| | | | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Remove gen_opc_jump_pcRichard Henderson2015-10-071-9/+10
| | | | | | | | | | | | | | | | | | | | Since jump_pc[1] is always npc + 4, we can infer after incrementing that jump_pc[1] == pc + 4. Because of that, we can encode the branch destination into a single word, and store that in npc. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Split out gen_branch_nRichard Henderson2015-10-071-27/+28
| | | | | | | | | | | | | | | | | | | | Unify three copies of this code from different branch types. Fix the case when npc == DYNAMIC_PC, i.e. a branch within a delay slot. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sparc: Tidy gen_branch_a interfaceRichard Henderson2015-10-071-11/+10
| | | | | | | | | | | | | | | | | | We always pass pc2 == dc->npc and r_cond == cpu_cond, and always set is_br afterward. Infer all of that. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-cris: Mirror gen_opc_pc into insn_startRichard Henderson2015-10-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This perhaps isn't ideal in terms of (ab)using the "pc" field to encode both pc and ppc + delay branch state, as one has to be aware of this when examining opcode dumps. But it preserves existing logic, which will be good for bisection, and it certainly does save storage space. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-sh4: Add flags state to insn_startRichard Henderson2015-10-072-1/+2
| | | | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-s390x: Add cc_op state to insn_startRichard Henderson2015-10-072-1/+2
| | | | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-mips: Add delayed branch state to insn_startRichard Henderson2015-10-072-1/+3
| | | | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-i386: Add cc_op state to insn_startRichard Henderson2015-10-072-1/+2
| | | | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-arm: Add condexec state to insn_startRichard Henderson2015-10-073-2/+4
| | | | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Allow extra data to be attached to insn_startRichard Henderson2015-10-074-16/+59
| | | | | | | | | | | | | | | | | | With an eye toward having this data replace the gen_opc_* arrays that each target collects in order to enable restore_state_from_tb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-0718-239/+160
| | | | | | | | | | | | | | | | | | | | | | | | Reduce the boilerplate required for each target. At the same time, move the test for breakpoint after calling tcg_gen_insn_start. Note that arm and aarch64 do not use cpu_breakpoint_test, but still move the inline test down after tcg_gen_insn_start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-0719-39/+41
| | | | | | | | | | | | | | | | This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-0720-81/+41
| | | | | | | | | | | | | | | | | | | | While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-0723-37/+28
| | | | | | | | | | | | | | | | With an eye toward making it mandatory. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | Merge remote-tracking branch 'remotes/rth/tags/pull-tile-20151007' into stagingPeter Maydell2015-10-0810-81/+799
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Collected patches # gpg: Signature made Wed 07 Oct 2015 10:30:17 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tile-20151007: target-tilegx: Support iret instruction and related special registers target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly target-tilegx: Implement v2mults instruction target-tilegx: Implement v?int_* instructions. target-tilegx: Implement v2sh* instructions target-tilegx: Handle nofault prefetch instructions target-tilegx: Fix a typo for mnemonic about "ld_add" target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV target-tilegx: Decode ill pseudo-instructions linux-user/tilegx: Implement tilegx signal features linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel target-tilegx: Let x1 pipe process bpt instruction only target-tilegx: Implement complex multiply instructions target-tilegx: Implement table index instructions target-tilegx: Implement crc instructions target-tilegx: Implement v1multu instruction target-tilegx: Implement v*add and v*sub instructions target-tilegx: Implement v*shl, v*shru, and v*shrs instructions target-tilegx: Tidy simd_helper.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-tilegx: Support iret instruction and related special registersChen Gang2015-10-074-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or it will cause target SIGILL (and the patch doesn't support system mode). Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and ↵Chen Gang2015-10-071-17/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly For some cases, they are for TILEGX_EXCP_OPCODE_UNKNOWN, not for TILEGX_EXCP_OPCODE_UNIMPLEMENTED. Also for some cases, they are for TILEGX_EXCP_OPCODE_UNIMPLEMENTED, not for TILEGX_EXCP_OPCODE_UNKNOWN. When analyzing issues, the correct printing information is necessary, e.g. grep UIMP in gcc testsuite output log for finding qemu tilegx umimplementation issues, grep UNKNOWN for finding unknown instructions. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-tilegx: Implement v2mults instructionChen Gang2015-10-073-0/+20
| | | | | | | | | | | | | | | | | | Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-3-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-tilegx: Implement v?int_* instructions.Chen Gang2015-10-073-0/+67
| | | | | | | | | | | | | | | | | | Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-2-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-tilegx: Implement v2sh* instructionsChen Gang2015-10-071-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | It is just according to v1sh* instructions implementation. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-tilegx: Handle nofault prefetch instructionsRichard Henderson2015-10-071-14/+26
| | | | | | | | | | | | | | | | | | | | | | | | These are mapped onto some of the normal load instructions, when the destination is the zero register. Other load insns do fault even when targeting the zero register. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-tilegx: Fix a typo for mnemonic about "ld_add"Chen Gang2015-10-071-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443562720-3008-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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