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* qcow2: Correct comment for realloc_refcount_block()Max Reitz2014-03-191-1/+1
| | | | | | | | | | | Contrary to the comment describing this function's behavior, it does not return 0 on success, but rather the offset of the newly allocated cluster. This patch adjusts the comment accordingly to reflect the actual behavior. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qemu-io: Extended "--cmd" description in usage textMaria Kustova2014-03-191-3/+6
| | | | | | | | | | | | | | It's not clear from the usage description that "--cmd" option accepts its argument as a string, so any special symbols have to be quoted from the shell. Updates in usage text: - Specified parameter format for "--cmd" option. - Added an instruction how to get help for "--cmd" option. Signed-off-by: Maria Kustova <maria.k@catit.be> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qemu-io-cmds: Fixed typo in example for writev.Maria Kustova2014-03-191-1/+1
| | | | | | Signed-off-by: Maria Kustova <maria.k@catit.be> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block: Add error handling to bdrv_invalidate_cache()Kevin Wolf2014-03-197-18/+76
| | | | | | | | | | If it returns an error, the migrated VM will not be started, but qemu exits with an error message. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Benoit Canet <benoit@irqsave.net>
* Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-2' into stagingPeter Maydell2014-03-182-4/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | vnc: fix vmware VGA incompatiblities # gpg: Signature made Tue 18 Mar 2014 07:23:10 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vnc-2: ui/vnc: fix vmware VGA incompatiblities Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * ui/vnc: fix vmware VGA incompatiblitiesPeter Lieven2014-03-182-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | this fixes invalid rectangle updates observed after commit 12b316d with the vmware VGA driver. The issues occured because the server and client surface update seems to be out of sync at some points and the max width of the surface is not dividable by VNC_DIRTY_BITS_PER_PIXEL (16). Reported-by: Serge Hallyn <serge.hallyn@ubuntu.com> Signed-off-by: Peter Lieven <pl@kamp.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2014-03-1815-263/+1855
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20140317' into staging target-arm queue: * more A64 Neon instructions * fixes to reset CBAR values for A9 and A15 boards * fix accesses to PMCR register in -icount mode # gpg: Signature made Mon 17 Mar 2014 22:04:52 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140317: (30 commits) scripts/qemu-binfmt-conf.sh: Add AArch64 registration target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) target-arm: A64: Implement FCVTXN target-arm: A64: Implement scalar saturating narrow ops target-arm: A64: Move handle_2misc_narrow function target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE softfloat: export squash_input_denormal functions target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder target-arm: A64: Implement FRINT* target-arm: A64: Implement SRI target-arm: A64: Add FRECPX (reciprocal exponent) target-arm: A64: List unsupported shift-imm opcodes target-arm: A64: Implement FCVTL target-arm: A64: Implement FCVTN target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions target-arm: A64: Implement SHLL, SHLL2 target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP target-arm: A64: Saturating and narrowing shift ops ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * scripts/qemu-binfmt-conf.sh: Add AArch64 registrationPeter Maydell2014-03-171-0/+3
| | | | | | | | | | | | | | | | | | Add the binfmt-misc magic needed to register QEMU for handling AArch64 ELF binaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-26-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée2014-03-174-37/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: A64: Implement FCVTXNPeter Maydell2014-03-173-1/+43
| | | | | | | | | | | | | | | | | | | | | | Implement the FCVTXN operation, which does a narrowing fp precision conversion using the "round to odd" (von Neumann) mode. This can conveniently be implemented as "do operation using round to zero; then set the LSB of the mantissa to 1 if the Inexact flag was set". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-24-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement scalar saturating narrow opsAlex Bennée2014-03-171-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Move handle_2misc_narrow functionAlex Bennée2014-03-171-90/+90
| | | | | | | | | | | | | | | | | | | | Move the handle_2misc_narrow() function up the file so that it can be called from disas_simd_scalar_two_reg_misc(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-22-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée2014-03-174-42/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
| * softfloat: export squash_input_denormal functionsAlex Bennée2014-03-172-2/+9
| | | | | | | | | | | | | | | | | | | | I need these available outside of softfloat for some of the reciprocal processing in aarch64 helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-20-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell2014-03-171-2/+78
| | | | | | | | | | | | | | | | | | Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-19-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell2014-03-171-0/+132
| | | | | | | | | | | | | | | | | | Implement the saturating left shift instructions SQSHL, SQSHLU and UQSHL for the scalar-shift-imm and shift-imm categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-18-git-send-email-peter.maydell@linaro.org
| * exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell2014-03-171-1/+1
| | | | | | | | | | | | | | | | | | | | The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement FRINT*Peter Maydell2014-03-171-3/+42
| | | | | | | | | | | | | | | | | | Implement the FRINT* round-to-integral operations from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-16-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement SRIPeter Maydell2014-03-171-8/+49
| | | | | | | | | | | | | | | | Implement SRI (shift right and insert). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-15-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée2014-03-173-1/+130
| | | | | | | | | | | | | | | | | | These are fairly simple exponent only estimation functions using helpers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-14-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: List unsupported shift-imm opcodesPeter Maydell2014-03-171-2/+11
| | | | | | | | | | | | | | | | | | | | Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement FCVTLPeter Maydell2014-03-171-0/+47
| | | | | | | | | | | | | | | | | | Implement FCVTL, the only instruction in the 2-reg-misc group which widens from size to 2*size elements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-12-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement FCVTNPeter Maydell2014-03-171-1/+23
| | | | | | | | | | | | | | | | | | Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-11-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell2014-03-171-19/+169
| | | | | | | | | | | | | | | | | | | | Implement the floating-point-to-integer conversion instructions FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-10-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement SHLL, SHLL2Peter Maydell2014-03-171-1/+31
| | | | | | | | | | | | | | | | | | Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-9-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell2014-03-173-1/+139
| | | | | | | | | | | | | | | | | | Implement the SADDLP, UADDLP, SADALP and UADALP instructions in the SIMD 2-reg misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-8-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Saturating and narrowing shift opsAlex Bennée2014-03-171-3/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are saturating and narrowing shift right operations. These are used in things like libav. Note signed shifts can have an "unsigned" saturating narrow operation which will floor negative values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394822294-14837-7-git-send-email-peter.maydell@linaro.org [PMM: Added the scalar encodings, style tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée2014-03-173-1/+41
| | | | | | | | | | | | | | | | | | Implement the CLS, CLZ operations in the 2-reg-misc category. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-6-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Add FSQRT to C3.6.17 (two misc)Alex Bennée2014-03-171-1/+12
| | | | | | | | | | | | | | | | | | | | Implement FSQRT in the two-reg-misc category. GCC uses this instruction form. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-5-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Add last AdvSIMD Integer to FP opsAlex Bennée2014-03-171-9/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds the remaining [US]CVTF operations to the SIMD shift-immediate, scalar-shift-immediate, two-reg-misc and scalar-two-reg-misc groups of opcodes. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394822294-14837-4-git-send-email-peter.maydell@linaro.org [PMM: added scalar 2-misc and scalar-shift-imm encodings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: A64: Fix bug in add_sub_ext handling of rnAlex Bennée2014-03-171-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | rn == 31 always means SP (not XZR) whether an add_sub_ext instruction is setting the flags or not; only rd has behaviour dependent on whether we are setting flags. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-3-git-send-email-peter.maydell@linaro.org
| * target-arm: A64: Implement PMULL instructionPeter Maydell2014-03-175-2/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the PMULL instruction; this is the last unimplemented insn in the three-reg-diff group. Note that PMULL with size 3 is considered part of the AES part of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition in the v8 ARM ARM), so it isn't necessary to burn an extra feature bit on it, even though we're using more feature bits than a single "crypto extension present/not present" toggle. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org
| * target-arm: Add ARM_CP_IO notation to PMCR reginfoPeter Maydell2014-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | Now that the PMCR writefn makes timer accesses, its reginfo needs the ARM_CP_IO flag, so that icount mode works correctly. (Fixes the bug accidentally introduced in commit 7c2cb42b). Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394908291-16546-1-git-send-email-peter.maydell@linaro.org
| * virt: Set reset-cbar on CPUsPeter Maydell2014-03-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | Set the reset-cbar property on CPUs used by the virt board, if they have it. This isn't necessary for correct functioning under Linux (since the A9 isn't a valid CPU for the virt board), but it is the correct behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-5-git-send-email-peter.maydell@linaro.org
| * exynos4210: Set reset-cbar property of Cortex-A9 CPUsPeter Maydell2014-03-171-3/+13
| | | | | | | | | | | | | | | | | | | | Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9 CPUs, so that Linux doesn't misrecognize them as a broken uniprocessor SoC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-4-git-send-email-peter.maydell@linaro.org
| * realview-pbx-a9: Set reset-cbar property for CPUsPeter Maydell2014-03-171-10/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If the CPU is a Cortex-A9 then we should set its reset-cbar property so that the guest can read the correct PERIPHBASE/CBAR register value; newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) will otherwise assume the CPU is a buggy single core A9 SoC. The realview-pbx-a9 is the only one of the cluster of boards in realview.c which works with the Cortex-A9 (ie which gets an a9mpcore_priv device); make sure it also has reset-cbar set correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-3-git-send-email-peter.maydell@linaro.org
| * vexpress: Set reset-cbar property for CPUsPeter Maydell2014-03-171-62/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) now assume that if the CPU is a Cortex-A9 and the reset value of the PERIPHBASE/CBAR register is zero then the CPU is a specific buggy single core A9 SoC, and will not try to start other cores. Since we now have a CPU property for the reset value of the CBAR, we can just fix the vexpress board model to correctly set CBAR so SMP works again. To avoid duplicate boilerplate code in both the A9 and A15 daughterboard init functions, we split out the CPU and private memory region init to its own function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-2-git-send-email-peter.maydell@linaro.org
* | Merge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140317' ↵Peter Maydell2014-03-174-51/+14
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging 4 small patches: - Fixing findings of valgrind regarding minor memory leaks: Currently we forget the pointer of qemu_allocate_irqs. Since we never free the irqs, this is not critical, but obviously not good programming style. While we are at it, we dont need the irq infrastructure for the sclp consoles. - Handle new ELF error codes for BIOS loading # gpg: Signature made Mon 17 Mar 2014 21:34:12 GMT using RSA key ID B5A61C7C # gpg: Can't check signature: public key not found * remotes/borntraeger/tags/kvm-s390-20140317: s390x/sclpconsole-lm: Fix and simplify irq setup s390x/sclpconsole: Fix and simplify interrupt injection s390x/cpu hotplug: Fix memory leak s390/ipl: Fix error path on BIOS loading Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | s390x/sclpconsole-lm: Fix and simplify irq setupChristian Borntraeger2014-03-171-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | valgrind complains about a memory leak in irq setup of sclpconsole: ==42117== 8 bytes in 1 blocks are definitely lost in loss record 89of 833 ==42117== at 0x4031AFE: malloc (vg_replace_malloc.c:292) ==42117== by 0x8022F855: malloc_and_trace (vl.c:2715) ==42117== by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2) ==42117== by 0x800F696D: qemu_extend_irqs (irq.c:51) ==42117== by 0x800F6AF7: qemu_allocate_irqs (irq.c:68) ==42117== by 0x800F5685: console_init (sclpconsole.c:235) ==42117== by 0x80297C79: event_realize (event-facility.c:386) ==42117== by 0x80105071: device_set_realized (qdev.c:693) ==42117== by 0x801CDC4B: property_set_bool (object.c:1337) ==42117== by 0x801CBD7F: object_property_set (object.c:819) [...] We dont need the indirection of an qemu irq to inject an slcp interrupt. Fixes a valgrind error and makes the code simpler. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
| * | s390x/sclpconsole: Fix and simplify interrupt injectionChristian Borntraeger2014-03-171-24/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | valgrind complains about a memory leak in irq setup of sclpconsole: ==42117== 8 bytes in 1 blocks are definitely lost in loss record 89 of 833 ==42117== at 0x4031AFE: malloc (vg_replace_malloc.c:292) ==42117== by 0x8022F855: malloc_and_trace (vl.c:2715) ==42117== by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2) ==42117== by 0x800F696D: qemu_extend_irqs (irq.c:51) ==42117== by 0x800F6AF7: qemu_allocate_irqs (irq.c:68) ==42117== by 0x800F5685: console_init (sclpconsole.c:235) ==42117== by 0x80297C79: event_realize (event-facility.c:386) ==42117== by 0x80105071: device_set_realized (qdev.c:693) ==42117== by 0x801CDC4B: property_set_bool (object.c:1337) ==42117== by 0x801CBD7F: object_property_set (object.c:819) [...] Turns out that we actually dont need the indirection, so trigger the sclp interrupt directly. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
| * | s390x/cpu hotplug: Fix memory leakChristian Borntraeger2014-03-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | valgrind complains about the following: ==42117== 8 bytes in 1 blocks are definitely lost in loss record 88 of 833 ==42117== at 0x4031AFE: malloc (vg_replace_malloc.c:292) ==42117== by 0x8022F855: malloc_and_trace (vl.c:2715) ==42117== by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2) ==42117== by 0x800F696D: qemu_extend_irqs (irq.c:51) ==42117== by 0x800F6AF7: qemu_allocate_irqs (irq.c:68) ==42117== by 0x8029FA4B: irq_cpu_hotplug_init (sclpcpu.c:84) ==42117== by 0x80297C79: event_realize (event-facility.c:386) ==42117== by 0x80105071: device_set_realized (qdev.c:693) [...] Right it is. Don't drop the pointer of the irq. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Jason J. Herne <jjherne@us.ibm.com>
| * | s390/ipl: Fix error path on BIOS loadingChristian Borntraeger2014-03-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 18674b26788a9e47f1157170234e32ece2044367 (elf-loader: add more return codes) enabled the elf loader to return other errors than -1. Lets also handle that case for our "BIOS" on s390. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> CC: Alexey Kardashevskiy <aik@ozlabs.ru> CC: Alexander Graf <agraf@suse.de>
* | | Merge remote-tracking branch 'remotes/rth/tcg-v8p-2' into stagingPeter Maydell2014-03-172-301/+304
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/rth/tcg-v8p-2: tcg-sparc: Convert to new ldst opcodes tcg-sparc: Convert to new ldst helpers tcg-sparc: Tidy tcg_out_tlb_load interface tcg-sparc: Use TCGMemOp within qemu_ldst routines tcg-sparc: Improve tcg_out_movi tcg-sparc: Dont handle constant arguments to ext32 ops tcg-sparc: Don't handle remainder tcg-sparc: Use intptr_t as appropriate tcg-sparc: Tidy call+jump patterns tcg-sparc: Fix tlb read tcg-sparc: Fix ld64 for 32-bit mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tcg-sparc: Convert to new ldst opcodesRichard Henderson2014-03-172-100/+53
| | | | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | tcg-sparc: Convert to new ldst helpersRichard Henderson2014-03-171-59/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All of the helpers with the explicit big/little endian option require the return address as a parameter. Acquire this via a trampoline. Move the load of areg0 into the trampoline. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | tcg-sparc: Tidy tcg_out_tlb_load interfaceRichard Henderson2014-03-171-40/+30
| | | | | | | | | | | | | | | | | | | | | Pass address registers explicitly, rather than as indicies of args[]. It's two argument registers either way. Use more TCGReg as appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | tcg-sparc: Use TCGMemOp within qemu_ldst routinesRichard Henderson2014-03-171-51/+65
| | | | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | tcg-sparc: Improve tcg_out_moviRichard Henderson2014-03-171-21/+31
| | | | | | | | | | | | | | | | | | If bits 31:13 are zero, reduce the insn count by one. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | tcg-sparc: Dont handle constant arguments to ext32 opsRichard Henderson2014-03-171-12/+4
| | | | | | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | tcg-sparc: Don't handle remainderRichard Henderson2014-03-172-23/+2
| | | | | | | | | | | | | | | | | | The generic fallback is exactly what we implemented. Signed-off-by: Richard Henderson <rth@twiddle.net>
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