diff options
Diffstat (limited to 'target-mips')
-rw-r--r-- | target-mips/cpu.h | 2 | ||||
-rw-r--r-- | target-mips/helper.h | 1 | ||||
-rw-r--r-- | target-mips/op_helper.c | 11 | ||||
-rw-r--r-- | target-mips/translate.c | 7 | ||||
-rw-r--r-- | target-mips/translate_init.c | 32 |
5 files changed, 49 insertions, 4 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 45f3987..5287e9a 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -376,6 +376,8 @@ struct CPUMIPSState { target_ulong llval; target_ulong llnewval; target_ulong llreg; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; target_ulong CP0_WatchLo[8]; int32_t CP0_WatchHi[8]; target_ulong CP0_XContext; diff --git a/target-mips/helper.h b/target-mips/helper.h index b8ec15e..4f1de51 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -122,6 +122,7 @@ DEF_HELPER_1(mtc0_cause, void, tl) DEF_HELPER_1(mtc0_ebase, void, tl) DEF_HELPER_1(mtc0_config0, void, tl) DEF_HELPER_1(mtc0_config2, void, tl) +DEF_HELPER_1(mtc0_lladdr, void, tl) DEF_HELPER_2(mtc0_watchlo, void, tl, i32) DEF_HELPER_2(mtc0_watchhi, void, tl, i32) DEF_HELPER_1(mtc0_xcontext, void, tl) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index d2a81f0..52d687d 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -730,7 +730,7 @@ target_ulong helper_mftc0_status(void) target_ulong helper_mfc0_lladdr (void) { - return (int32_t)env->lladdr >> 4; + return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); } target_ulong helper_mfc0_watchlo (uint32_t sel) @@ -795,7 +795,7 @@ target_ulong helper_dmfc0_tcschefback (void) target_ulong helper_dmfc0_lladdr (void) { - return env->lladdr >> 4; + return env->lladdr >> env->CP0_LLAddr_shift; } target_ulong helper_dmfc0_watchlo (uint32_t sel) @@ -1243,6 +1243,13 @@ void helper_mtc0_config2 (target_ulong arg1) env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); } +void helper_mtc0_lladdr (target_ulong arg1) +{ + target_long mask = env->CP0_LLAddr_rw_bitmask; + arg1 = arg1 << env->CP0_LLAddr_shift; + env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); +} + void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel) { /* Watch exceptions for instructions, data loads, data stores diff --git a/target-mips/translate.c b/target-mips/translate.c index 63737e2..e9d9224 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -3841,7 +3841,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s case 17: switch (sel) { case 0: - /* ignored */ + gen_helper_mtc0_lladdr(arg); rn = "LLAddr"; break; default: @@ -4998,7 +4998,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int case 17: switch (sel) { case 0: - /* ignored */ + gen_helper_mtc0_lladdr(arg); rn = "LLAddr"; break; default: @@ -8633,6 +8633,9 @@ void cpu_reset (CPUMIPSState *env) env->CP0_Config3 = env->cpu_model->CP0_Config3; env->CP0_Config6 = env->cpu_model->CP0_Config6; env->CP0_Config7 = env->cpu_model->CP0_Config7; + env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask + << env->cpu_model->CP0_LLAddr_shift; + env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; env->SYNCI_Step = env->cpu_model->SYNCI_Step; env->CCRes = env->cpu_model->CCRes; env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 088e2b4..c950eab 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -70,6 +70,8 @@ struct mips_def_t { int32_t CP0_Config3; int32_t CP0_Config6; int32_t CP0_Config7; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; int32_t SYNCI_Step; int32_t CCRes; int32_t CP0_Status_rw_bitmask; @@ -105,6 +107,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x1278FF17, @@ -124,6 +128,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x1258FF17, @@ -141,6 +147,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x1278FF17, @@ -158,6 +166,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x1258FF17, @@ -176,6 +186,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x1278FF17, @@ -194,6 +206,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x1258FF17, @@ -212,6 +226,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, /* No DSP implemented. */ @@ -231,6 +247,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, /* No DSP implemented. */ @@ -252,6 +270,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, .CCRes = 2, /* No DSP implemented. */ @@ -294,6 +314,8 @@ static const mips_def_t mips_defs[] = .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), /* Note: Config1 is only used internally, the R4000 has only Config0. */ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 16, .CCRes = 2, .CP0_Status_rw_bitmask = 0x3678FFFF, @@ -310,6 +332,8 @@ static const mips_def_t mips_defs[] = /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 16, .CCRes = 2, .CP0_Status_rw_bitmask = 0x3678FFFF, @@ -331,6 +355,8 @@ static const mips_def_t mips_defs[] = (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x32F8FFFF, @@ -350,6 +376,8 @@ static const mips_def_t mips_defs[] = (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x36F8FFFF, @@ -374,6 +402,8 @@ static const mips_def_t mips_defs[] = (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, .CCRes = 1, .CP0_Status_rw_bitmask = 0x36FBFFFF, @@ -399,6 +429,8 @@ static const mips_def_t mips_defs[] = (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x36FBFFFF, |