diff options
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu-qom.h | 2 | ||||
| -rw-r--r-- | target-arm/cpu.c | 5 | ||||
| -rw-r--r-- | target-arm/cpu.h | 14 | ||||
| -rw-r--r-- | target-arm/translate.c | 9 |
4 files changed, 6 insertions, 24 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index ef6261f..48ba605 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -127,7 +127,7 @@ typedef struct ARMCPU { static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) { - return ARM_CPU(container_of(env, ARMCPU, env)); + return container_of(env, ARMCPU, env); } #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1bc227e..be26acc 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -63,11 +63,6 @@ static void arm_cpu_reset(CPUState *s) ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); CPUARMState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); - } - acc->parent_reset(s); memset(env, 0, offsetof(CPUARMState, breakpoints)); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index abcc0b4..1369604 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -249,11 +249,6 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault -static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) -{ - env->cp15.c13_tls2 = newtls; -} - #define CPSR_M (0x1f) #define CPSR_T (1 << 5) #define CPSR_F (1 << 6) @@ -734,15 +729,6 @@ static inline int cpu_mmu_index (CPUARMState *env) return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; } -#if defined(CONFIG_USER_ONLY) -static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) -{ - if (newsp) - env->regs[13] = newsp; - env->regs[0] = 0; -} -#endif - #include "exec/cpu-all.h" /* Bit usage in the TB flags field: */ diff --git a/target-arm/translate.c b/target-arm/translate.c index af2aef2..9310c58 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9796,10 +9796,11 @@ undef: /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline void gen_intermediate_code_internal(CPUARMState *env, +static inline void gen_intermediate_code_internal(ARMCPU *cpu, TranslationBlock *tb, - int search_pc) + bool search_pc) { + CPUARMState *env = &cpu->env; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; uint16_t *gen_opc_end; @@ -10072,12 +10073,12 @@ done_generating: void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 0); + gen_intermediate_code_internal(arm_env_get_cpu(env), tb, false); } void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 1); + gen_intermediate_code_internal(arm_env_get_cpu(env), tb, true); } static const char *cpu_mode_names[16] = { |
