diff options
Diffstat (limited to 'hw')
-rw-r--r-- | hw/ide-mmio.c | 123 | ||||
-rw-r--r-- | hw/ide.c | 92 | ||||
-rw-r--r-- | hw/ide.h | 5 | ||||
-rw-r--r-- | hw/r2d.c | 1 | ||||
-rw-r--r-- | hw/sh.h | 4 |
5 files changed, 129 insertions, 96 deletions
diff --git a/hw/ide-mmio.c b/hw/ide-mmio.c new file mode 100644 index 0000000..07b1ccf --- /dev/null +++ b/hw/ide-mmio.c @@ -0,0 +1,123 @@ +/* + * QEMU IDE Emulation: mmio support (for embedded). + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2006 Openedhand Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "hw.h" +#include "block.h" +#include "block_int.h" +#include "sysemu.h" +#include "dma.h" +#include "ide-internal.h" + +/***********************************************************/ +/* MMIO based ide port + * This emulates IDE device connected directly to the CPU bus without + * dedicated ide controller, which is often seen on embedded boards. + */ + +typedef struct { + IDEBus *bus; + int shift; +} MMIOState; + +static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) +{ + MMIOState *s = (MMIOState*)opaque; + IDEBus *bus = s->bus; + addr >>= s->shift; + if (addr & 7) + return ide_ioport_read(bus, addr); + else + return ide_data_readw(bus, 0); +} + +static void mmio_ide_write (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + MMIOState *s = (MMIOState*)opaque; + IDEBus *bus = s->bus; + addr >>= s->shift; + if (addr & 7) + ide_ioport_write(bus, addr, val); + else + ide_data_writew(bus, 0, val); +} + +static CPUReadMemoryFunc * const mmio_ide_reads[] = { + mmio_ide_read, + mmio_ide_read, + mmio_ide_read, +}; + +static CPUWriteMemoryFunc * const mmio_ide_writes[] = { + mmio_ide_write, + mmio_ide_write, + mmio_ide_write, +}; + +static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) +{ + MMIOState *s= (MMIOState*)opaque; + IDEBus *bus = s->bus; + return ide_status_read(bus, 0); +} + +static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + MMIOState *s = (MMIOState*)opaque; + IDEBus *bus = s->bus; + ide_cmd_write(bus, 0, val); +} + +static CPUReadMemoryFunc * const mmio_ide_status[] = { + mmio_ide_status_read, + mmio_ide_status_read, + mmio_ide_status_read, +}; + +static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { + mmio_ide_cmd_write, + mmio_ide_cmd_write, + mmio_ide_cmd_write, +}; + +void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, + qemu_irq irq, int shift, + BlockDriverState *hd0, BlockDriverState *hd1) +{ + MMIOState *s = qemu_mallocz(sizeof(MMIOState)); + IDEBus *bus = qemu_mallocz(sizeof(*bus)); + int mem1, mem2; + + ide_init2(bus, hd0, hd1, irq); + + s->bus = bus; + s->shift = shift; + + mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); + mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); + cpu_register_physical_memory(membase, 16 << shift, mem1); + cpu_register_physical_memory(membase2, 2 << shift, mem2); +} + @@ -2700,98 +2700,6 @@ void ide_dma_cancel(BMDMAState *bm) } /***********************************************************/ -/* MMIO based ide port - * This emulates IDE device connected directly to the CPU bus without - * dedicated ide controller, which is often seen on embedded boards. - */ - -typedef struct { - IDEBus *bus; - int shift; -} MMIOState; - -static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) -{ - MMIOState *s = (MMIOState*)opaque; - IDEBus *bus = s->bus; - addr >>= s->shift; - if (addr & 7) - return ide_ioport_read(bus, addr); - else - return ide_data_readw(bus, 0); -} - -static void mmio_ide_write (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - MMIOState *s = (MMIOState*)opaque; - IDEBus *bus = s->bus; - addr >>= s->shift; - if (addr & 7) - ide_ioport_write(bus, addr, val); - else - ide_data_writew(bus, 0, val); -} - -static CPUReadMemoryFunc * const mmio_ide_reads[] = { - mmio_ide_read, - mmio_ide_read, - mmio_ide_read, -}; - -static CPUWriteMemoryFunc * const mmio_ide_writes[] = { - mmio_ide_write, - mmio_ide_write, - mmio_ide_write, -}; - -static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) -{ - MMIOState *s= (MMIOState*)opaque; - IDEBus *bus = s->bus; - return ide_status_read(bus, 0); -} - -static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - MMIOState *s = (MMIOState*)opaque; - IDEBus *bus = s->bus; - ide_cmd_write(bus, 0, val); -} - -static CPUReadMemoryFunc * const mmio_ide_status[] = { - mmio_ide_status_read, - mmio_ide_status_read, - mmio_ide_status_read, -}; - -static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { - mmio_ide_cmd_write, - mmio_ide_cmd_write, - mmio_ide_cmd_write, -}; - -void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, - qemu_irq irq, int shift, - BlockDriverState *hd0, BlockDriverState *hd1) -{ - MMIOState *s = qemu_mallocz(sizeof(MMIOState)); - IDEBus *bus = qemu_mallocz(sizeof(*bus)); - int mem1, mem2; - - ide_init2(bus, hd0, hd1, irq); - - s->bus = bus; - s->shift = shift; - - mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); - mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); - cpu_register_physical_memory(membase, 16 << shift, mem1); - cpu_register_physical_memory(membase2, 2 << shift, mem2); -} - -/***********************************************************/ /* CF-ATA Microdrive */ #define METADATA_SIZE 0x20 @@ -19,4 +19,9 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq, void *dbdma, int channel, qemu_irq dma_irq); +/* ide-mmio.c */ +void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, + qemu_irq irq, int shift, + BlockDriverState *hd0, BlockDriverState *hd1); + #endif /* HW_IDE_H */ @@ -31,6 +31,7 @@ #include "pci.h" #include "net.h" #include "sh7750_regs.h" +#include "ide.h" #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ #define SDRAM_SIZE 0x04000000 @@ -51,8 +51,4 @@ qemu_irq sh7750_irl(struct SH7750State *s); /* tc58128.c */ int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2); -/* ide.c */ -void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2, - qemu_irq irq, int shift, - BlockDriverState *hd0, BlockDriverState *hd1); #endif |