diff options
| -rw-r--r-- | hw/slavio_misc.c | 58 | ||||
| -rw-r--r-- | hw/sun4m.c | 55 | ||||
| -rw-r--r-- | qemu-doc.texi | 15 | ||||
| -rw-r--r-- | vl.c | 1 | ||||
| -rw-r--r-- | vl.h | 2 |
5 files changed, 122 insertions, 9 deletions
diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c index ebf1849..236c4a1 100644 --- a/hw/slavio_misc.c +++ b/hw/slavio_misc.c @@ -46,11 +46,14 @@ typedef struct MiscState { uint8_t aux1, aux2; uint8_t diag, mctrl; uint32_t sysctrl; + uint16_t leds; } MiscState; #define MISC_SIZE 1 #define SYSCTRL_MAXADDR 3 #define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1) +#define LED_MAXADDR 2 +#define LED_SIZE (LED_MAXADDR + 1) static void slavio_misc_update_irq(void *opaque) { @@ -223,6 +226,54 @@ static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = { slavio_sysctrl_mem_writel, }; +static uint32_t slavio_led_mem_reads(void *opaque, target_phys_addr_t addr) +{ + MiscState *s = opaque; + uint32_t ret = 0, saddr; + + saddr = addr & LED_MAXADDR; + switch (saddr) { + case 0: + ret = s->leds; + break; + default: + break; + } + MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr, + ret); + return ret; +} + +static void slavio_led_mem_writes(void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + MiscState *s = opaque; + uint32_t saddr; + + saddr = addr & LED_MAXADDR; + MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr, + val); + switch (saddr) { + case 0: + s->sysctrl = val; + break; + default: + break; + } +} + +static CPUReadMemoryFunc *slavio_led_mem_read[3] = { + slavio_led_mem_reads, + slavio_led_mem_reads, + slavio_led_mem_reads, +}; + +static CPUWriteMemoryFunc *slavio_led_mem_write[3] = { + slavio_led_mem_writes, + slavio_led_mem_writes, + slavio_led_mem_writes, +}; + static void slavio_misc_save(QEMUFile *f, void *opaque) { MiscState *s = opaque; @@ -291,6 +342,13 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, // Power management cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory); + /* 16 bit registers */ + slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read, + slavio_led_mem_write, s); + /* ss600mp diag LEDs */ + cpu_register_physical_memory(base + 0x1600000, MISC_SIZE, + slavio_misc_io_memory); + /* 32 bit registers */ slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read, slavio_sysctrl_mem_write, @@ -388,7 +388,8 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1], serial_hds[0]); - sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd_table); + if (hwdef->fd_base != (target_phys_addr_t)-1) + sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd_table); main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq, esp_reset); @@ -546,6 +547,39 @@ static const struct hwdef hwdefs[] = { 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, }, }, + /* SS-600MP */ + { + .iommu_base = 0xfe0000000ULL, + .tcx_base = 0xe20000000ULL, + .cs_base = -1, + .slavio_base = 0xff0000000ULL, + .ms_kb_base = 0xff1000000ULL, + .serial_base = 0xff1100000ULL, + .nvram_base = 0xff1200000ULL, + .fd_base = -1, + .counter_base = 0xff1300000ULL, + .intctl_base = 0xff1400000ULL, + .dma_base = 0xef0081000ULL, + .esp_base = 0xef0080000ULL, + .le_base = 0xef0060000ULL, + .power_base = 0xefa000000ULL, + .vram_size = 0x00100000, + .nvram_size = 0x2000, + .esp_irq = 18, + .le_irq = 16, + .clock_irq = 7, + .clock1_irq = 19, + .ms_kb_irq = 14, + .ser_irq = 15, + .fd_irq = 22, + .me_irq = 30, + .cs_irq = -1, + .machine_id = 0x71, + .intbit_to_level = { + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, + }, + }, }; static void sun4m_common_init(int RAM_size, const char *boot_device, DisplayState *ds, @@ -594,6 +628,19 @@ static void ss10_init(int RAM_size, int vga_ram_size, const char *boot_device, 1, 0xffffffff); // XXX actually first 62GB ok } +/* SPARCserver 600MP hardware initialisation */ +static void ss600mp_init(int RAM_size, int vga_ram_size, const char *boot_device, + DisplayState *ds, const char **fd_filename, int snapshot, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + if (cpu_model == NULL) + cpu_model = "TI SuperSparc II"; + sun4m_common_init(RAM_size, boot_device, ds, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model, + 2, 0xffffffff); // XXX actually first 62GB ok +} + QEMUMachine ss5_machine = { "SS-5", "Sun4m platform, SPARCstation 5", @@ -605,3 +652,9 @@ QEMUMachine ss10_machine = { "Sun4m platform, SPARCstation 10", ss10_init, }; + +QEMUMachine ss600mp_machine = { + "SS-600MP", + "Sun4m platform, SPARCserver 600MP", + ss600mp_init, +}; diff --git a/qemu-doc.texi b/qemu-doc.texi index 740d303..92dfd5c 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1949,10 +1949,10 @@ More information is available at @node Sparc32 System emulator @section Sparc32 System emulator -Use the executable @file{qemu-system-sparc} to simulate a SparcStation 5 -or SparcStation 10 (sun4m architecture). The emulation is somewhat complete. -SMP up to 16 CPUs is supported, but Linux limits the number of usable CPUs -to 4. +Use the executable @file{qemu-system-sparc} to simulate a SPARCstation +5, SPARCstation 10, or SPARCserver 600MP (sun4m architecture). The +emulation is somewhat complete. SMP up to 16 CPUs is supported, but +Linux limits the number of usable CPUs to 4. QEMU emulates the following sun4m peripherals: @@ -1971,13 +1971,14 @@ and power/reset logic @item ESP SCSI controller with hard disk and CD-ROM support @item -Floppy drive +Floppy drive (not on SS-600MP) @item CS4231 sound device (only on SS-5, not working yet) @end itemize -The number of peripherals is fixed in the architecture. Maximum memory size -depends on the machine type, for SS-5 it is 256MB and for SS-10 2047MB. +The number of peripherals is fixed in the architecture. Maximum +memory size depends on the machine type, for SS-5 it is 256MB and for +SS-10 and SS-600MP 2047MB. Since version 0.8.2, QEMU uses OpenBIOS @url{http://www.openbios.org/}. OpenBIOS is a free (GPL v2) portable @@ -7421,6 +7421,7 @@ void register_machines(void) #else qemu_register_machine(&ss5_machine); qemu_register_machine(&ss10_machine); + qemu_register_machine(&ss600mp_machine); #endif #elif defined(TARGET_ARM) qemu_register_machine(&integratorcp_machine); @@ -1048,7 +1048,7 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); #endif /* sun4m.c */ -extern QEMUMachine ss5_machine, ss10_machine; +extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine; /* iommu.c */ void *iommu_init(target_phys_addr_t addr); |
