summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--target-arm/helper.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ce1b59e..1c07d81 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -784,6 +784,15 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "AIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* Auxiliary fault status registers: these also are IMPDEF, and we
+ * choose to RAZ/WI for all cores.
+ */
+ { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
/* MAIR can just read-as-written because we don't implement caches
* and so don't need to care about memory attributes.
*/
OpenPOWER on IntegriCloud