diff options
| -rw-r--r-- | target-mips/cpu.h | 3 | ||||
| -rw-r--r-- | target-mips/translate.c | 44 |
2 files changed, 47 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 26e7894..91e781e 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -136,6 +136,7 @@ typedef struct mips_def_t mips_def_t; #define MIPS_TC_MAX 5 #define MIPS_FPU_MAX 1 #define MIPS_DSP_ACC 4 +#define MIPS_KSCRATCH_NUM 6 typedef struct TCState TCState; struct TCState { @@ -229,6 +230,7 @@ struct CPUMIPSState { target_ulong CP0_EntryLo0; target_ulong CP0_EntryLo1; target_ulong CP0_Context; + target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; int32_t CP0_PageMask; int32_t CP0_PageGrain; int32_t CP0_Wired; @@ -375,6 +377,7 @@ struct CPUMIPSState { uint32_t CP0_Config4; uint32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 +#define CP0C4_KScrExist 16 uint32_t CP0_Config5; uint32_t CP0_Config5_rw_bitmask; #define CP0C5_M 31 diff --git a/target-mips/translate.c b/target-mips/translate.c index 446eb8a..167f9bc 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1170,6 +1170,7 @@ typedef struct DisasContext { int bstate; target_ulong btarget; bool ulri; + int kscrexist; } DisasContext; enum { @@ -4567,6 +4568,15 @@ static inline void gen_mtc0_store64 (TCGv arg, target_ulong off) tcg_gen_st_tl(arg, cpu_env, off); } +static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) +{ + if (ctx->insn_flags & ISA_MIPS32R6) { + tcg_gen_movi_tl(arg, 0); + } else { + tcg_gen_movi_tl(arg, ~0); + } +} + static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; @@ -5149,6 +5159,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; + case 2 ... 7: + if (ctx->kscrexist & (1 << sel)) { + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + tcg_gen_ext32s_tl(arg, arg); + rn = "KScratch"; + } else { + gen_mfc0_unimplemented(ctx, arg); + } + break; default: goto die; } @@ -5757,6 +5777,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; + case 2 ... 7: + if (ctx->kscrexist & (1 << sel)) { + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + rn = "KScratch"; + } + break; default: goto die; } @@ -6344,6 +6371,15 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; + case 2 ... 7: + if (ctx->kscrexist & (1 << sel)) { + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + rn = "KScratch"; + } else { + gen_mfc0_unimplemented(ctx, arg); + } + break; default: goto die; } @@ -6943,6 +6979,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; + case 2 ... 7: + if (ctx->kscrexist & (1 << sel)) { + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + rn = "KScratch"; + } + break; default: goto die; } @@ -17414,6 +17457,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, ctx.CP0_Config1 = env->CP0_Config1; ctx.tb = tb; ctx.bstate = BS_NONE; + ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; /* Restore delay slot state from the tb context. */ ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */ ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI); |
