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-rw-r--r--hw/pflash_cfi02.c22
-rw-r--r--hw/ppc.c15
-rw-r--r--hw/ppc_chrp.c6
-rw-r--r--linux-user/main.c6
-rw-r--r--target-alpha/cpu.h7
-rw-r--r--target-alpha/translate.c3
-rw-r--r--target-ppc/cpu.h8
-rw-r--r--target-ppc/helper.c10
8 files changed, 46 insertions, 31 deletions
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index 0db8b56..fc38cd6 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -91,7 +91,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
uint32_t ret;
uint8_t *p;
- DPRINTF("%s: offset %08x\n", __func__, offset);
+ DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
ret = -1;
offset -= pfl->base;
boff = offset & 0xFF;
@@ -161,7 +161,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
default:
goto flash_read;
}
- DPRINTF("%s: ID %d %x\n", __func__, boff, ret);
+ DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
break;
case 0xA0:
case 0x10:
@@ -214,7 +214,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
offset -= pfl->base;
cmd = value;
- DPRINTF("%s: offset %08x %08x %d\n", __func__, offset, value, width);
+ DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
+ offset, value, width);
if (pfl->cmd != 0xA0 && cmd == 0xF0) {
DPRINTF("%s: flash reset asked (%02x %02x)\n",
__func__, pfl->cmd, cmd);
@@ -239,7 +240,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
return;
}
if (boff != 0x555 || cmd != 0xAA) {
- DPRINTF("%s: unlock0 failed %04x %02x %04x\n",
+ DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
__func__, boff, cmd, 0x555);
goto reset_flash;
}
@@ -249,7 +250,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
/* We started an unlock sequence */
check_unlock1:
if (boff != 0x2AA || cmd != 0x55) {
- DPRINTF("%s: unlock1 failed %04x %02x\n", __func__, boff, cmd);
+ DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
+ boff, cmd);
goto reset_flash;
}
DPRINTF("%s: unlock sequence done\n", __func__);
@@ -257,7 +259,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
case 2:
/* We finished an unlock sequence */
if (!pfl->bypass && boff != 0x555) {
- DPRINTF("%s: command failed %04x %02x\n", __func__, boff, cmd);
+ DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
+ boff, cmd);
goto reset_flash;
}
switch (cmd) {
@@ -281,7 +284,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
/* We need another unlock sequence */
goto check_unlock0;
case 0xA0:
- DPRINTF("%s: write data offset %08x %08x %d\n",
+ DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
__func__, offset, value, width);
p = pfl->storage;
switch (width) {
@@ -352,7 +355,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
switch (cmd) {
case 0x10:
if (boff != 0x555) {
- DPRINTF("%s: chip erase: invalid address %04x\n",
+ DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
__func__, offset);
goto reset_flash;
}
@@ -369,7 +372,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
/* Sector erase */
p = pfl->storage;
offset &= ~(pfl->sector_len - 1);
- DPRINTF("%s: start sector erase at %08x\n", __func__, offset);
+ DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
+ offset);
memset(p + offset, 0xFF, pfl->sector_len);
pflash_update(pfl, offset, pfl->sector_len);
pfl->status = 0x00;
diff --git a/hw/ppc.c b/hw/ppc.c
index 8438bc6..4cd0c66 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -464,8 +464,8 @@ static void cpu_4xx_fit_cb (void *opaque)
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
if (loglevel) {
- fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
- (env->spr[SPR_40x_TCR] >> 23) & 0x1,
+ fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
+ (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
}
@@ -495,9 +495,10 @@ static void cpu_4xx_pit_cb (void *opaque)
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
if (loglevel) {
- fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
- (env->spr[SPR_40x_TCR] >> 22) & 0x1,
- (env->spr[SPR_40x_TCR] >> 26) & 0x1,
+ fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
+ "%016" PRIx64 "\n", __func__,
+ (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
+ (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
ppcemb_timer->pit_reload);
}
@@ -536,7 +537,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
if (next == now)
next++;
if (loglevel) {
- fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
+ fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
@@ -587,7 +588,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
qemu_del_timer(tb_env->decr_timer);
} else {
if (loglevel)
- fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
+ fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val);
now = qemu_get_clock(vm_clock);
next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
if (next == now)
diff --git a/hw/ppc_chrp.c b/hw/ppc_chrp.c
index 70571fd..9a7538c 100644
--- a/hw/ppc_chrp.c
+++ b/hw/ppc_chrp.c
@@ -48,7 +48,7 @@ static int macio_nvram_mem_index = -1;
static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
+ printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
}
static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
@@ -61,7 +61,7 @@ static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
{
- printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
+ printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
return 0;
}
@@ -261,7 +261,7 @@ static int vga_osi_call(CPUState *env)
/* R6 = x, R7 = y, R8 = visible, R9 = data */
break;
default:
- fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
+ fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
break;
}
return 1; /* osi_call handled */
diff --git a/linux-user/main.c b/linux-user/main.c
index 277f194..d14b499 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -755,10 +755,10 @@ void cpu_loop(CPUPPCState *env)
info._sifields._sigfault._addr = env->nip - 4;
queue_signal(info.si_signo, &info);
case EXCP_DSI:
- fprintf(stderr, "Invalid data memory access: 0x%08x\n",
+ fprintf(stderr, "Invalid data memory access: 0x" ADDRX "\n",
env->spr[SPR_DAR]);
if (loglevel) {
- fprintf(logfile, "Invalid data memory access: 0x%08x\n",
+ fprintf(logfile, "Invalid data memory access: 0x" ADDRX "\n",
env->spr[SPR_DAR]);
}
switch (env->error_code & 0xFF000000) {
@@ -1549,7 +1549,7 @@ void cpu_loop(CPUM68KState *env)
#ifdef TARGET_ALPHA
void cpu_loop (CPUState *env)
{
- int trapnr, ret;
+ int trapnr;
target_siginfo_t info;
while (1) {
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index a77af17..729d587 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -382,6 +382,13 @@ enum {
IR_ZERO = 31,
};
+CPUAlphaState * cpu_alpha_init (void);
+int cpu_alpha_exec(CPUAlphaState *s);
+/* you can call this signal handler from your SIGBUS and SIGSEGV
+ signal handlers to inform the virtual CPU of exceptions. non zero
+ is returned if the signal was handled by the virtual CPU. */
+int cpu_alpha_signal_handler(int host_signum, void *pinfo,
+ void *puc);
int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
void cpu_loop_exit (void);
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 0afd896..08e0624 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2004,7 +2004,8 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
#if defined ALPHA_DEBUG_DISAS
insn_count++;
if (logfile != NULL) {
- fprintf(logfile, "pc %016lx mem_idx\n", ctx.pc, ctx.mem_idx);
+ fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
+ ctx.pc, ctx.mem_idx);
}
#endif
insn = ldl_code(ctx.pc);
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 4b67f1a..740bc1b 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -35,24 +35,26 @@ typedef uint64_t ppc_gpr_t;
#define TARGET_LONG_BITS 64
#define TARGET_GPR_BITS 64
#define REGX "%016" PRIx64
-#define ADDRX "%016" PRIx64
#elif defined(TARGET_PPCSPE)
+/* e500v2 have 36 bits physical address space */
+#define TARGET_PHYS_ADDR_BITS 64
/* GPR are 64 bits: used by vector extension */
typedef uint64_t ppc_gpr_t;
#define TARGET_LONG_BITS 32
#define TARGET_GPR_BITS 64
#define REGX "%016" PRIx64
-#define ADDRX "%08" PRIx32
#else
typedef uint32_t ppc_gpr_t;
#define TARGET_LONG_BITS 32
#define TARGET_GPR_BITS 32
#define REGX "%08" PRIx32
-#define ADDRX "%08" PRIx32
#endif
#include "cpu-defs.h"
+#define ADDRX TARGET_FMT_lx
+#define PADDRX TARGET_FMT_plx
+
#include <setjmp.h>
#include "softfloat.h"
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index b9a55b1..a7d0391 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -38,7 +38,7 @@
/* PowerPC MMU emulation */
#if defined(CONFIG_USER_ONLY)
-int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
+int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu)
{
int exception, error_code;
@@ -631,7 +631,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
}
int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
- uint32_t address, int rw, int access_type)
+ target_ulong address, int rw, int access_type)
{
ppcemb_tlb_t *tlb;
target_phys_addr_t raddr;
@@ -649,8 +649,8 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
}
mask = ~(tlb->size - 1);
if (loglevel) {
- fprintf(logfile, "%s: TLB %d address %08x PID %04x <=> "
- "%08x %08x %04x\n",
+ fprintf(logfile, "%s: TLB %d address " ADDRX " PID " ADDRX " <=> "
+ ADDRX " " ADDRX " " ADDRX "\n",
__func__, i, address, env->spr[SPR_40x_PID],
tlb->EPN, mask, tlb->PID);
}
@@ -832,7 +832,7 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
}
/* Perform address translation */
-int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
+int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu)
{
mmu_ctx_t ctx;
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