diff options
| -rw-r--r-- | hw/openpic.c | 11 | ||||
| -rw-r--r-- | hw/ppc.c | 11 | ||||
| -rw-r--r-- | hw/ppc.h | 2 |
3 files changed, 18 insertions, 6 deletions
diff --git a/hw/openpic.c b/hw/openpic.c index bcafe0a..cc8ec35 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -40,6 +40,7 @@ #include "sysbus.h" #include "pci/msi.h" #include "qemu/bitops.h" +#include "ppc.h" //#define DEBUG_OPENPIC @@ -646,8 +647,7 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) static void openpic_gcr_write(OpenPICState *opp, uint64_t val) { - CPUArchState *env; - int mpic_proxy = 0; + bool mpic_proxy = false; if (val & GCR_RESET) { openpic_reset(&opp->busdev.qdev); @@ -659,11 +659,10 @@ static void openpic_gcr_write(OpenPICState *opp, uint64_t val) /* Set external proxy mode */ if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { - mpic_proxy = 1; - } - for (env = first_cpu; env != NULL; env = env->next_cpu) { - env->mpic_proxy = mpic_proxy; + mpic_proxy = true; } + + ppce500_set_mpic_proxy(mpic_proxy); } static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, @@ -428,6 +428,17 @@ void ppce500_irq_init(CPUPPCState *env) env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, cpu, PPCE500_INPUT_NB); } + +/* Enable or Disable the E500 EPR capability */ +void ppce500_set_mpic_proxy(bool enabled) +{ + CPUPPCState *env; + + for (env = first_cpu; env != NULL; env = env->next_cpu) { + env->mpic_proxy = enabled; + } +} + /*****************************************************************************/ /* PowerPC time base and decrementer emulation */ @@ -73,6 +73,8 @@ void ppc6xx_irq_init (CPUPPCState *env); void ppc970_irq_init (CPUPPCState *env); void ppcPOWER7_irq_init (CPUPPCState *env); +void ppce500_set_mpic_proxy(bool enabled); + /* PPC machines for OpenBIOS */ enum { ARCH_PREP = 0, |
