diff options
411 files changed, 10525 insertions, 6023 deletions
@@ -21,6 +21,7 @@ libdis* libuser /linux-headers/asm +/qga/qapi-generated /qapi-generated /qapi-types.[ch] /qapi-visit.[ch] diff --git a/.gitmodules b/.gitmodules index 45e51e7..444c24a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,6 +13,9 @@ [submodule "roms/openbios"] path = roms/openbios url = git://git.qemu-project.org/openbios.git +[submodule "roms/openhackware"] + path = roms/openhackware + url = git://git.qemu-project.org/openhackware.git [submodule "roms/qemu-palcode"] path = roms/qemu-palcode url = git://github.com/rth7680/qemu-palcode.git diff --git a/.travis.yml b/.travis.yml index c7ff4da..04da973 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,6 +4,12 @@ python: compiler: - gcc - clang +notifications: + irc: + channels: + - "irc.oftc.net#qemu" + on_success: change + on_failure: always env: global: - TEST_CMD="make check" @@ -14,23 +20,23 @@ env: - GUI_PKGS="libgtk-3-dev libvte-2.90-dev libsdl1.2-dev libpng12-dev libpixman-1-dev" - EXTRA_PKGS="" matrix: - - TARGETS=alpha-softmmu,alpha-linux-user - - TARGETS=arm-softmmu,arm-linux-user - - TARGETS=aarch64-softmmu,aarch64-linux-user - - TARGETS=cris-softmmu - - TARGETS=i386-softmmu,x86_64-softmmu - - TARGETS=lm32-softmmu - - TARGETS=m68k-softmmu - - TARGETS=microblaze-softmmu,microblazeel-softmmu - - TARGETS=mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu - - TARGETS=moxie-softmmu - - TARGETS=or32-softmmu, - - TARGETS=ppc-softmmu,ppc64-softmmu,ppcemb-softmmu - - TARGETS=s390x-softmmu - - TARGETS=sh4-softmmu,sh4eb-softmmu - - TARGETS=sparc-softmmu,sparc64-softmmu - - TARGETS=unicore32-softmmu - - TARGETS=xtensa-softmmu,xtensaeb-softmmu + - TARGETS=alpha-softmmu,alpha-linux-user + - TARGETS=arm-softmmu,arm-linux-user + - TARGETS=aarch64-softmmu,aarch64-linux-user + - TARGETS=cris-softmmu + - TARGETS=i386-softmmu,x86_64-softmmu + - TARGETS=lm32-softmmu + - TARGETS=m68k-softmmu + - TARGETS=microblaze-softmmu,microblazeel-softmmu + - TARGETS=mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu + - TARGETS=moxie-softmmu + - TARGETS=or32-softmmu, + - TARGETS=ppc-softmmu,ppc64-softmmu,ppcemb-softmmu + - TARGETS=s390x-softmmu + - TARGETS=sh4-softmmu,sh4eb-softmmu + - TARGETS=sparc-softmmu,sparc64-softmmu + - TARGETS=unicore32-softmmu + - TARGETS=xtensa-softmmu,xtensaeb-softmmu before_install: - git submodule update --init --recursive - sudo apt-get update -qq @@ -46,6 +52,10 @@ matrix: - env: TARGETS=i386-softmmu,x86_64-softmmu EXTRA_CONFIG="--enable-debug --enable-tcg-interpreter" compiler: gcc + # All the extra -dev packages + - env: TARGETS=i386-softmmu,x86_64-softmmu + EXTRA_PKGS="libaio-dev libcap-ng-dev libattr1-dev libbrlapi-dev uuid-dev libusb-1.0.0-dev" + compiler: gcc # Currently configure doesn't force --disable-pie - env: TARGETS=i386-softmmu,x86_64-softmmu EXTRA_CONFIG="--enable-gprof --enable-gcov --disable-pie" @@ -65,8 +75,7 @@ matrix: EXTRA_CONFIG="--enable-trace-backend=ftrace" TEST_CMD="" compiler: gcc - # This disabled make check for the ftrace backend which needs more setting up - # Currently broken on 12.04 due to mis-packaged liburcu and changed API, will be pulled. - #- env: TARGETS=i386-softmmu,x86_64-softmmu - # EXTRA_PKGS="liblttng-ust-dev liburcu-dev" - # EXTRA_CONFIG="--enable-trace-backend=ust" + - env: TARGETS=i386-softmmu,x86_64-softmmu + EXTRA_PKGS="liblttng-ust-dev liburcu-dev" + EXTRA_CONFIG="--enable-trace-backend=ust" + compiler: gcc diff --git a/MAINTAINERS b/MAINTAINERS index 62e7683..7d17f83 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -175,9 +175,12 @@ S: Maintained F: target-ppc/kvm.c S390 +M: Christian Borntraeger <borntraeger@de.ibm.com> +M: Cornelia Huck <cornelia.huck@de.ibm.com> M: Alexander Graf <agraf@suse.de> S: Maintained F: target-s390x/kvm.c +F: hw/intc/s390_flic.[hc] X86 M: Marcelo Tosatti <mtosatti@redhat.com> @@ -493,10 +496,13 @@ F: hw/s390x/s390-*.c S390 Virtio-ccw M: Cornelia Huck <cornelia.huck@de.ibm.com> +M: Christian Borntraeger <borntraeger@de.ibm.com> M: Alexander Graf <agraf@suse.de> S: Supported F: hw/s390x/s390-virtio-ccw.c F: hw/s390x/css.[hc] +F: hw/s390x/sclp*.[hc] +F: hw/s390x/ipl*.[hc] T: git git://github.com/cohuck/qemu virtio-ccw-upstr UniCore32 Machines @@ -627,6 +633,7 @@ F: hw/block/virtio-blk.c virtio-ccw M: Cornelia Huck <cornelia.huck@de.ibm.com> +M: Christian Borntraeger <borntraeger@de.ibm.com> S: Supported F: hw/s390x/virtio-ccw.[hc] T: git git://github.com/cohuck/qemu virtio-ccw-upstr @@ -265,10 +265,7 @@ clean: # avoid old build problems by removing potentially incorrect old files rm -f config.mak op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h rm -f qemu-options.def - find . -name '*.[oda]' -type f -exec rm -f {} + - find . -name '*.l[oa]' -type f -exec rm -f {} + - find . -name '*$(DSOSUF)' -type f -exec rm -f {} + - find . -name '*.mo' -type f -exec rm -f {} + + find . \( -name '*.l[oa]' -o -name '*.so' -o -name '*.dll' -o -name '*.mo' -o -name '*.[oda]' \) -type f -exec rm {} + rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) qemu-ga TAGS cscope.* *.pod *~ */*~ rm -f fsdev/*.pod rm -rf .libs */.libs diff --git a/Makefile.objs b/Makefile.objs index 5cd3d81..a6e0e2a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -39,6 +39,7 @@ libcacard-y += libcacard/vcardt.o ifeq ($(CONFIG_SOFTMMU),y) common-obj-y = blockdev.o blockdev-nbd.o block/ +common-obj-y += iothread.o common-obj-y += net/ common-obj-y += qdev-monitor.o device-hotplug.o common-obj-$(CONFIG_WIN32) += os-win32.o @@ -1 +1 @@ -1.7.50 +1.7.90 diff --git a/arch_init.c b/arch_init.c index fe17279..60c975d 100644 --- a/arch_init.c +++ b/arch_init.c @@ -164,8 +164,9 @@ static struct { uint8_t *encoded_buf; /* buffer for storing page content */ uint8_t *current_buf; - /* Cache for XBZRLE */ + /* Cache for XBZRLE, Protected by lock. */ PageCache *cache; + QemuMutex lock; } XBZRLE = { .encoded_buf = NULL, .current_buf = NULL, @@ -174,16 +175,52 @@ static struct { /* buffer used for XBZRLE decoding */ static uint8_t *xbzrle_decoded_buf; +static void XBZRLE_cache_lock(void) +{ + if (migrate_use_xbzrle()) + qemu_mutex_lock(&XBZRLE.lock); +} + +static void XBZRLE_cache_unlock(void) +{ + if (migrate_use_xbzrle()) + qemu_mutex_unlock(&XBZRLE.lock); +} + int64_t xbzrle_cache_resize(int64_t new_size) { + PageCache *new_cache, *cache_to_free; + if (new_size < TARGET_PAGE_SIZE) { return -1; } + /* no need to lock, the current thread holds qemu big lock */ if (XBZRLE.cache != NULL) { - return cache_resize(XBZRLE.cache, new_size / TARGET_PAGE_SIZE) * - TARGET_PAGE_SIZE; + /* check XBZRLE.cache again later */ + if (pow2floor(new_size) == migrate_xbzrle_cache_size()) { + return pow2floor(new_size); + } + new_cache = cache_init(new_size / TARGET_PAGE_SIZE, + TARGET_PAGE_SIZE); + if (!new_cache) { + DPRINTF("Error creating cache\n"); + return -1; + } + + XBZRLE_cache_lock(); + /* the XBZRLE.cache may have be destroyed, check it again */ + if (XBZRLE.cache != NULL) { + cache_to_free = XBZRLE.cache; + XBZRLE.cache = new_cache; + } else { + cache_to_free = new_cache; + } + XBZRLE_cache_unlock(); + + cache_fini(cache_to_free); } + return pow2floor(new_size); } @@ -539,6 +576,8 @@ static int ram_save_block(QEMUFile *f, bool last_stage) ret = ram_control_save_page(f, block->offset, offset, TARGET_PAGE_SIZE, &bytes_sent); + XBZRLE_cache_lock(); + current_addr = block->offset + offset; if (ret != RAM_SAVE_CONTROL_NOT_SUPP) { if (ret != RAM_SAVE_CONTROL_DELAYED) { @@ -587,6 +626,7 @@ static int ram_save_block(QEMUFile *f, bool last_stage) acct_info.norm_pages++; } + XBZRLE_cache_unlock(); /* if page is unmodified, continue to the next */ if (bytes_sent > 0) { last_sent_block = block; @@ -654,6 +694,7 @@ static void migration_end(void) migration_bitmap = NULL; } + XBZRLE_cache_lock(); if (XBZRLE.cache) { cache_fini(XBZRLE.cache); g_free(XBZRLE.cache); @@ -663,6 +704,7 @@ static void migration_end(void) XBZRLE.encoded_buf = NULL; XBZRLE.current_buf = NULL; } + XBZRLE_cache_unlock(); } static void ram_migration_cancel(void *opaque) @@ -693,13 +735,17 @@ static int ram_save_setup(QEMUFile *f, void *opaque) dirty_rate_high_cnt = 0; if (migrate_use_xbzrle()) { + qemu_mutex_lock_iothread(); XBZRLE.cache = cache_init(migrate_xbzrle_cache_size() / TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); if (!XBZRLE.cache) { + qemu_mutex_unlock_iothread(); DPRINTF("Error creating cache\n"); return -1; } + qemu_mutex_init(&XBZRLE.lock); + qemu_mutex_unlock_iothread(); /* We prefer not to abort if there is no memory */ XBZRLE.encoded_buf = g_try_malloc0(TARGET_PAGE_SIZE); @@ -214,6 +214,7 @@ aio_ctx_finalize(GSource *source) thread_pool_free(ctx->thread_pool); aio_set_event_notifier(ctx, &ctx->notifier, NULL); event_notifier_cleanup(&ctx->notifier); + rfifolock_destroy(&ctx->lock); qemu_mutex_destroy(&ctx->bh_lock); g_array_free(ctx->pollfds, TRUE); timerlistgroup_deinit(&ctx->tlg); @@ -250,6 +251,12 @@ static void aio_timerlist_notify(void *opaque) aio_notify(opaque); } +static void aio_rfifolock_cb(void *opaque) +{ + /* Kick owner thread in case they are blocked in aio_poll() */ + aio_notify(opaque); +} + AioContext *aio_context_new(void) { AioContext *ctx; @@ -257,6 +264,7 @@ AioContext *aio_context_new(void) ctx->pollfds = g_array_new(FALSE, FALSE, sizeof(GPollFD)); ctx->thread_pool = NULL; qemu_mutex_init(&ctx->bh_lock); + rfifolock_init(&ctx->lock, aio_rfifolock_cb, ctx); event_notifier_init(&ctx->notifier, false); aio_set_event_notifier(ctx, &ctx->notifier, (EventNotifierHandler *) @@ -275,3 +283,13 @@ void aio_context_unref(AioContext *ctx) { g_source_unref(&ctx->source); } + +void aio_context_acquire(AioContext *ctx) +{ + rfifolock_lock(&ctx->lock); +} + +void aio_context_release(AioContext *ctx) +{ + rfifolock_unlock(&ctx->lock); +} diff --git a/backends/baum.c b/backends/baum.c index 665107f..759003f 100644 --- a/backends/baum.c +++ b/backends/baum.c @@ -566,9 +566,11 @@ CharDriverState *chr_baum_init(void) BaumDriverState *baum; CharDriverState *chr; brlapi_handle_t *handle; -#if defined(CONFIG_SDL) && SDL_COMPILEDVERSION < SDL_VERSIONNUM(2, 0, 0) +#if defined(CONFIG_SDL) +#if SDL_COMPILEDVERSION < SDL_VERSIONNUM(2, 0, 0) SDL_SysWMinfo info; #endif +#endif int tty; baum = g_malloc0(sizeof(BaumDriverState)); @@ -595,13 +597,15 @@ CharDriverState *chr_baum_init(void) goto fail; } -#if defined(CONFIG_SDL) && SDL_COMPILEDVERSION < SDL_VERSIONNUM(2, 0, 0) +#if defined(CONFIG_SDL) +#if SDL_COMPILEDVERSION < SDL_VERSIONNUM(2, 0, 0) memset(&info, 0, sizeof(info)); SDL_VERSION(&info.version); if (SDL_GetWMInfo(&info)) tty = info.info.x11.wmwindow; else #endif +#endif tty = BRLAPI_TTY_DEFAULT; if (brlapi__enterTtyMode(handle, tty, NULL) == -1) { @@ -1321,7 +1321,7 @@ int bdrv_open(BlockDriverState **pbs, const char *filename, bdrv_open_flags(bs, flags | BDRV_O_UNMAP) | BDRV_O_PROTOCOL, true, &local_err); if (ret < 0) { - goto fail; + goto unlink_and_fail; } /* Find the right image format driver */ @@ -1388,12 +1388,19 @@ done: ret = -EINVAL; goto close_and_fail; } - QDECREF(options); if (!bdrv_key_required(bs)) { bdrv_dev_change_media_cb(bs, true); + } else if (!runstate_check(RUN_STATE_PRELAUNCH) + && !runstate_check(RUN_STATE_INMIGRATE) + && !runstate_check(RUN_STATE_PAUSED)) { /* HACK */ + error_setg(errp, + "Guest must be stopped for opening of encrypted image"); + ret = -EBUSY; + goto close_and_fail; } + QDECREF(options); *pbs = bs; return 0; @@ -4055,7 +4062,7 @@ int bdrv_debug_remove_breakpoint(BlockDriverState *bs, const char *tag) int bdrv_debug_resume(BlockDriverState *bs, const char *tag) { - while (bs && bs->drv && !bs->drv->bdrv_debug_resume) { + while (bs && (!bs->drv || !bs->drv->bdrv_debug_resume)) { bs = bs->file; } @@ -4774,19 +4781,43 @@ flush_parent: return bdrv_co_flush(bs->file); } -void bdrv_invalidate_cache(BlockDriverState *bs) +void bdrv_invalidate_cache(BlockDriverState *bs, Error **errp) { - if (bs->drv && bs->drv->bdrv_invalidate_cache) { - bs->drv->bdrv_invalidate_cache(bs); + Error *local_err = NULL; + int ret; + + if (!bs->drv) { + return; + } + + if (bs->drv->bdrv_invalidate_cache) { + bs->drv->bdrv_invalidate_cache(bs, &local_err); + } else if (bs->file) { + bdrv_invalidate_cache(bs->file, &local_err); + } + if (local_err) { + error_propagate(errp, local_err); + return; + } + + ret = refresh_total_sectors(bs, bs->total_sectors); + if (ret < 0) { + error_setg_errno(errp, -ret, "Could not refresh total sector count"); + return; } } -void bdrv_invalidate_cache_all(void) +void bdrv_invalidate_cache_all(Error **errp) { BlockDriverState *bs; + Error *local_err = NULL; QTAILQ_FOREACH(bs, &bdrv_states, device_list) { - bdrv_invalidate_cache(bs); + bdrv_invalidate_cache(bs, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } } } @@ -5390,43 +5421,37 @@ int bdrv_amend_options(BlockDriverState *bs, QEMUOptionParameter *options) return bs->drv->bdrv_amend_options(bs, options); } -/* Used to recurse on single child block filters. - * Single child block filter will store their child in bs->file. +/* This function will be called by the bdrv_recurse_is_first_non_filter method + * of block filter and by bdrv_is_first_non_filter. + * It is used to test if the given bs is the candidate or recurse more in the + * node graph. */ -bool bdrv_generic_is_first_non_filter(BlockDriverState *bs, +bool bdrv_recurse_is_first_non_filter(BlockDriverState *bs, BlockDriverState *candidate) { - if (!bs->drv) { - return false; - } - - if (!bs->drv->authorizations[BS_IS_A_FILTER]) { - if (bs == candidate) { - return true; - } else { - return false; - } - } - - if (!bs->drv->authorizations[BS_FILTER_PASS_DOWN]) { + /* return false if basic checks fails */ + if (!bs || !bs->drv) { return false; } - if (!bs->file) { - return false; + /* the code reached a non block filter driver -> check if the bs is + * the same as the candidate. It's the recursion termination condition. + */ + if (!bs->drv->is_filter) { + return bs == candidate; } + /* Down this path the driver is a block filter driver */ - return bdrv_recurse_is_first_non_filter(bs->file, candidate); -} - -bool bdrv_recurse_is_first_non_filter(BlockDriverState *bs, - BlockDriverState *candidate) -{ - if (bs->drv && bs->drv->bdrv_recurse_is_first_non_filter) { + /* If the block filter recursion method is defined use it to recurse down + * the node graph. + */ + if (bs->drv->bdrv_recurse_is_first_non_filter) { return bs->drv->bdrv_recurse_is_first_non_filter(bs, candidate); } - return bdrv_generic_is_first_non_filter(bs, candidate); + /* the driver is a block filter but don't allow to recurse -> return false + */ + return false; } /* This function checks if the candidate is the first non filter bs down it's @@ -5441,6 +5466,7 @@ bool bdrv_is_first_non_filter(BlockDriverState *candidate) QTAILQ_FOREACH(bs, &bdrv_states, device_list) { bool perm; + /* try to recurse in this top level bs */ perm = bdrv_recurse_is_first_non_filter(bs, candidate); /* candidate is the first non filter */ diff --git a/block/blkverify.c b/block/blkverify.c index b98b08b..e1c3117 100644 --- a/block/blkverify.c +++ b/block/blkverify.c @@ -288,6 +288,20 @@ static BlockDriverAIOCB *blkverify_aio_flush(BlockDriverState *bs, return bdrv_aio_flush(s->test_file, cb, opaque); } +static bool blkverify_recurse_is_first_non_filter(BlockDriverState *bs, + BlockDriverState *candidate) +{ + BDRVBlkverifyState *s = bs->opaque; + + bool perm = bdrv_recurse_is_first_non_filter(bs->file, candidate); + + if (perm) { + return true; + } + + return bdrv_recurse_is_first_non_filter(s->test_file, candidate); +} + static BlockDriver bdrv_blkverify = { .format_name = "blkverify", .protocol_name = "blkverify", @@ -302,7 +316,8 @@ static BlockDriver bdrv_blkverify = { .bdrv_aio_writev = blkverify_aio_writev, .bdrv_aio_flush = blkverify_aio_flush, - .authorizations = { true, false }, + .is_filter = true, + .bdrv_recurse_is_first_non_filter = blkverify_recurse_is_first_non_filter, }; static void bdrv_blkverify_init(void) diff --git a/block/nbd-client.c b/block/nbd-client.c index 0922b78..7d698cb 100644 --- a/block/nbd-client.c +++ b/block/nbd-client.c @@ -43,6 +43,17 @@ static void nbd_recv_coroutines_enter_all(NbdClientSession *s) } } +static void nbd_teardown_connection(NbdClientSession *client) +{ + /* finish any pending coroutines */ + shutdown(client->sock, 2); + nbd_recv_coroutines_enter_all(client); + + qemu_aio_set_fd_handler(client->sock, NULL, NULL, NULL); + closesocket(client->sock); + client->sock = -1; +} + static void nbd_reply_ready(void *opaque) { NbdClientSession *s = opaque; @@ -78,7 +89,7 @@ static void nbd_reply_ready(void *opaque) } fail: - nbd_recv_coroutines_enter_all(s); + nbd_teardown_connection(s); } static void nbd_restart_write(void *opaque) @@ -324,7 +335,7 @@ int nbd_client_session_co_discard(NbdClientSession *client, int64_t sector_num, } -static void nbd_teardown_connection(NbdClientSession *client) +void nbd_client_session_close(NbdClientSession *client) { struct nbd_request request = { .type = NBD_CMD_DISC, @@ -332,22 +343,14 @@ static void nbd_teardown_connection(NbdClientSession *client) .len = 0 }; - nbd_send_request(client->sock, &request); - - /* finish any pending coroutines */ - shutdown(client->sock, 2); - nbd_recv_coroutines_enter_all(client); - - qemu_aio_set_fd_handler(client->sock, NULL, NULL, NULL); - closesocket(client->sock); - client->sock = -1; -} - -void nbd_client_session_close(NbdClientSession *client) -{ if (!client->bs) { return; } + if (client->sock == -1) { + return; + } + + nbd_send_request(client->sock, &request); nbd_teardown_connection(client); client->bs = NULL; diff --git a/block/nfs.c b/block/nfs.c index ef731f0..98aa363 100644 --- a/block/nfs.c +++ b/block/nfs.c @@ -112,6 +112,9 @@ nfs_co_generic_cb(int ret, struct nfs_context *nfs, void *data, if (task->ret == 0 && task->st) { memcpy(task->st, data, sizeof(struct stat)); } + if (task->ret < 0) { + error_report("NFS Error: %s", nfs_get_error(nfs)); + } if (task->co) { task->bh = qemu_bh_new(nfs_co_generic_bh_cb, task); qemu_bh_schedule(task->bh); diff --git a/block/qcow2-cluster.c b/block/qcow2-cluster.c index 36c1bed..9499df9 100644 --- a/block/qcow2-cluster.c +++ b/block/qcow2-cluster.c @@ -380,6 +380,10 @@ static int coroutine_fn copy_sectors(BlockDriverState *bs, BLKDBG_EVENT(bs->file, BLKDBG_COW_READ); + if (!bs->drv) { + return -ENOMEDIUM; + } + /* Call .bdrv_co_readv() directly instead of using the public block-layer * interface. This avoids double I/O throttling and request tracking, * which can lead to deadlock when block layer copy-on-read is enabled. diff --git a/block/qcow2-refcount.c b/block/qcow2-refcount.c index 8712d8b..4a2df5f 100644 --- a/block/qcow2-refcount.c +++ b/block/qcow2-refcount.c @@ -96,7 +96,8 @@ static int get_refcount(BlockDriverState *bs, int64_t cluster_index) refcount_table_index = cluster_index >> (s->cluster_bits - REFCOUNT_SHIFT); if (refcount_table_index >= s->refcount_table_size) return 0; - refcount_block_offset = s->refcount_table[refcount_table_index]; + refcount_block_offset = + s->refcount_table[refcount_table_index] & REFT_OFFSET_MASK; if (!refcount_block_offset) return 0; @@ -1382,7 +1383,7 @@ static int write_reftable_entry(BlockDriverState *bs, int rt_index) * does _not_ decrement the reference count for the currently occupied cluster. * * This function prints an informative message to stderr on error (and returns - * -errno); on success, 0 is returned. + * -errno); on success, the offset of the newly allocated cluster is returned. */ static int64_t realloc_refcount_block(BlockDriverState *bs, int reftable_index, uint64_t offset) @@ -1398,14 +1399,14 @@ static int64_t realloc_refcount_block(BlockDriverState *bs, int reftable_index, fprintf(stderr, "Could not allocate new cluster: %s\n", strerror(-new_offset)); ret = new_offset; - goto fail; + goto done; } /* fetch current refcount block content */ ret = qcow2_cache_get(bs, s->refcount_block_cache, offset, &refcount_block); if (ret < 0) { fprintf(stderr, "Could not fetch refcount block: %s\n", strerror(-ret)); - goto fail; + goto fail_free_cluster; } /* new block has not yet been entered into refcount table, therefore it is @@ -1416,8 +1417,7 @@ static int64_t realloc_refcount_block(BlockDriverState *bs, int reftable_index, "check failed: %s\n", strerror(-ret)); /* the image will be marked corrupt, so don't even attempt on freeing * the cluster */ - new_offset = 0; - goto fail; + goto done; } /* write to new block */ @@ -1425,7 +1425,7 @@ static int64_t realloc_refcount_block(BlockDriverState *bs, int reftable_index, s->cluster_sectors); if (ret < 0) { fprintf(stderr, "Could not write refcount block: %s\n", strerror(-ret)); - goto fail; + goto fail_free_cluster; } /* update refcount table */ @@ -1435,24 +1435,27 @@ static int64_t realloc_refcount_block(BlockDriverState *bs, int reftable_index, if (ret < 0) { fprintf(stderr, "Could not update refcount table: %s\n", strerror(-ret)); - goto fail; + goto fail_free_cluster; } -fail: - if (new_offset && (ret < 0)) { - qcow2_free_clusters(bs, new_offset, s->cluster_size, - QCOW2_DISCARD_ALWAYS); - } + goto done; + +fail_free_cluster: + qcow2_free_clusters(bs, new_offset, s->cluster_size, QCOW2_DISCARD_OTHER); + +done: if (refcount_block) { - if (ret < 0) { - qcow2_cache_put(bs, s->refcount_block_cache, &refcount_block); - } else { - ret = qcow2_cache_put(bs, s->refcount_block_cache, &refcount_block); - } + /* This should never fail, as it would only do so if the given refcount + * block cannot be found in the cache. As this is impossible as long as + * there are no bugs, assert the success. */ + int tmp = qcow2_cache_put(bs, s->refcount_block_cache, &refcount_block); + assert(tmp == 0); } + if (ret < 0) { return ret; } + return new_offset; } diff --git a/block/qcow2.c b/block/qcow2.c index cfe80be..b9dc960 100644 --- a/block/qcow2.c +++ b/block/qcow2.c @@ -644,7 +644,7 @@ static int qcow2_open(BlockDriverState *bs, QDict *options, int flags, } /* Clear unknown autoclear feature bits */ - if (!bs->read_only && s->autoclear_features != 0) { + if (!bs->read_only && !(flags & BDRV_O_INCOMING) && s->autoclear_features) { s->autoclear_features = 0; ret = qcow2_update_header(bs); if (ret < 0) { @@ -657,7 +657,7 @@ static int qcow2_open(BlockDriverState *bs, QDict *options, int flags, qemu_co_mutex_init(&s->lock); /* Repair image if dirty */ - if (!(flags & BDRV_O_CHECK) && !bs->read_only && + if (!(flags & (BDRV_O_CHECK | BDRV_O_INCOMING)) && !bs->read_only && (s->incompatible_features & QCOW2_INCOMPAT_DIRTY)) { BdrvCheckResult result = {0}; @@ -1137,10 +1137,12 @@ static void qcow2_close(BlockDriverState *bs) /* else pre-write overlap checks in cache_destroy may crash */ s->l1_table = NULL; - qcow2_cache_flush(bs, s->l2_table_cache); - qcow2_cache_flush(bs, s->refcount_block_cache); + if (!(bs->open_flags & BDRV_O_INCOMING)) { + qcow2_cache_flush(bs, s->l2_table_cache); + qcow2_cache_flush(bs, s->refcount_block_cache); - qcow2_mark_clean(bs); + qcow2_mark_clean(bs); + } qcow2_cache_destroy(bs, s->l2_table_cache); qcow2_cache_destroy(bs, s->refcount_block_cache); @@ -1154,7 +1156,7 @@ static void qcow2_close(BlockDriverState *bs) qcow2_free_snapshots(bs); } -static void qcow2_invalidate_cache(BlockDriverState *bs) +static void qcow2_invalidate_cache(BlockDriverState *bs, Error **errp) { BDRVQcowState *s = bs->opaque; int flags = s->flags; @@ -1162,6 +1164,8 @@ static void qcow2_invalidate_cache(BlockDriverState *bs) AES_KEY aes_decrypt_key; uint32_t crypt_method = 0; QDict *options; + Error *local_err = NULL; + int ret; /* * Backing files are read-only which makes all of their metadata immutable, @@ -1176,12 +1180,25 @@ static void qcow2_invalidate_cache(BlockDriverState *bs) qcow2_close(bs); - options = qdict_new(); - qdict_put(options, QCOW2_OPT_LAZY_REFCOUNTS, - qbool_from_int(s->use_lazy_refcounts)); + bdrv_invalidate_cache(bs->file, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } memset(s, 0, sizeof(BDRVQcowState)); - qcow2_open(bs, options, flags, NULL); + options = qdict_clone_shallow(bs->options); + + ret = qcow2_open(bs, options, flags, &local_err); + if (local_err) { + error_setg(errp, "Could not reopen qcow2 layer: %s", + error_get_pretty(local_err)); + error_free(local_err); + return; + } else if (ret < 0) { + error_setg_errno(errp, -ret, "Could not reopen qcow2 layer"); + return; + } QDECREF(options); diff --git a/block/qed.c b/block/qed.c index 8802ad3..3bd9db9 100644 --- a/block/qed.c +++ b/block/qed.c @@ -1558,13 +1558,31 @@ static int bdrv_qed_change_backing_file(BlockDriverState *bs, return ret; } -static void bdrv_qed_invalidate_cache(BlockDriverState *bs) +static void bdrv_qed_invalidate_cache(BlockDriverState *bs, Error **errp) { BDRVQEDState *s = bs->opaque; + Error *local_err = NULL; + int ret; bdrv_qed_close(bs); + + bdrv_invalidate_cache(bs->file, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + memset(s, 0, sizeof(BDRVQEDState)); - bdrv_qed_open(bs, NULL, bs->open_flags, NULL); + ret = bdrv_qed_open(bs, NULL, bs->open_flags, &local_err); + if (local_err) { + error_setg(errp, "Could not reopen qed layer: %s", + error_get_pretty(local_err)); + error_free(local_err); + return; + } else if (ret < 0) { + error_setg_errno(errp, -ret, "Could not reopen qed layer"); + return; + } } static int bdrv_qed_check(BlockDriverState *bs, BdrvCheckResult *result, diff --git a/block/quorum.c b/block/quorum.c index bd997b7..7f580a8 100644 --- a/block/quorum.c +++ b/block/quorum.c @@ -625,13 +625,18 @@ static int64_t quorum_getlength(BlockDriverState *bs) return result; } -static void quorum_invalidate_cache(BlockDriverState *bs) +static void quorum_invalidate_cache(BlockDriverState *bs, Error **errp) { BDRVQuorumState *s = bs->opaque; + Error *local_err = NULL; int i; for (i = 0; i < s->num_children; i++) { - bdrv_invalidate_cache(s->bs[i]); + bdrv_invalidate_cache(s->bs[i], &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } } } @@ -852,8 +857,6 @@ static BlockDriver bdrv_quorum = { .bdrv_file_open = quorum_open, .bdrv_close = quorum_close, - .authorizations = { true, true }, - .bdrv_co_flush_to_disk = quorum_co_flush, .bdrv_getlength = quorum_getlength, @@ -862,6 +865,7 @@ static BlockDriver bdrv_quorum = { .bdrv_aio_writev = quorum_aio_writev, .bdrv_invalidate_cache = quorum_invalidate_cache, + .is_filter = true, .bdrv_recurse_is_first_non_filter = quorum_recurse_is_first_non_filter, }; diff --git a/block/raw-posix.c b/block/raw-posix.c index e6b4c1f..1688e16 100644 --- a/block/raw-posix.c +++ b/block/raw-posix.c @@ -1561,6 +1561,15 @@ static int check_hdev_writable(BDRVRawState *s) return 0; } +static void hdev_parse_filename(const char *filename, QDict *options, + Error **errp) +{ + /* The prefix is optional, just as for "file". */ + strstart(filename, "host_device:", &filename); + + qdict_put_obj(options, "filename", QOBJECT(qstring_from_str(filename))); +} + static int hdev_open(BlockDriverState *bs, QDict *options, int flags, Error **errp) { @@ -1767,6 +1776,18 @@ static int hdev_create(const char *filename, QEMUOptionParameter *options, int ret = 0; struct stat stat_buf; int64_t total_size = 0; + bool has_prefix; + + /* This function is used by all three protocol block drivers and therefore + * any of these three prefixes may be given. + * The return value has to be stored somewhere, otherwise this is an error + * due to -Werror=unused-value. */ + has_prefix = + strstart(filename, "host_device:", &filename) || + strstart(filename, "host_cdrom:" , &filename) || + strstart(filename, "host_floppy:", &filename); + + (void)has_prefix; /* Read out options */ while (options && options->name) { @@ -1805,6 +1826,7 @@ static BlockDriver bdrv_host_device = { .instance_size = sizeof(BDRVRawState), .bdrv_needs_filename = true, .bdrv_probe_device = hdev_probe_device, + .bdrv_parse_filename = hdev_parse_filename, .bdrv_file_open = hdev_open, .bdrv_close = raw_close, .bdrv_reopen_prepare = raw_reopen_prepare, @@ -1834,6 +1856,15 @@ static BlockDriver bdrv_host_device = { }; #ifdef __linux__ +static void floppy_parse_filename(const char *filename, QDict *options, + Error **errp) +{ + /* The prefix is optional, just as for "file". */ + strstart(filename, "host_floppy:", &filename); + + qdict_put_obj(options, "filename", QOBJECT(qstring_from_str(filename))); +} + static int floppy_open(BlockDriverState *bs, QDict *options, int flags, Error **errp) { @@ -1939,6 +1970,7 @@ static BlockDriver bdrv_host_floppy = { .instance_size = sizeof(BDRVRawState), .bdrv_needs_filename = true, .bdrv_probe_device = floppy_probe_device, + .bdrv_parse_filename = floppy_parse_filename, .bdrv_file_open = floppy_open, .bdrv_close = raw_close, .bdrv_reopen_prepare = raw_reopen_prepare, @@ -1963,7 +1995,20 @@ static BlockDriver bdrv_host_floppy = { .bdrv_media_changed = floppy_media_changed, .bdrv_eject = floppy_eject, }; +#endif + +#if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) +static void cdrom_parse_filename(const char *filename, QDict *options, + Error **errp) +{ + /* The prefix is optional, just as for "file". */ + strstart(filename, "host_cdrom:", &filename); + qdict_put_obj(options, "filename", QOBJECT(qstring_from_str(filename))); +} +#endif + +#ifdef __linux__ static int cdrom_open(BlockDriverState *bs, QDict *options, int flags, Error **errp) { @@ -2050,6 +2095,7 @@ static BlockDriver bdrv_host_cdrom = { .instance_size = sizeof(BDRVRawState), .bdrv_needs_filename = true, .bdrv_probe_device = cdrom_probe_device, + .bdrv_parse_filename = cdrom_parse_filename, .bdrv_file_open = cdrom_open, .bdrv_close = raw_close, .bdrv_reopen_prepare = raw_reopen_prepare, @@ -2180,6 +2226,7 @@ static BlockDriver bdrv_host_cdrom = { .instance_size = sizeof(BDRVRawState), .bdrv_needs_filename = true, .bdrv_probe_device = cdrom_probe_device, + .bdrv_parse_filename = cdrom_parse_filename, .bdrv_file_open = cdrom_open, .bdrv_close = raw_close, .bdrv_reopen_prepare = raw_reopen_prepare, diff --git a/block/raw-win32.c b/block/raw-win32.c index 9954748..48cb2c2 100644 --- a/block/raw-win32.c +++ b/block/raw-win32.c @@ -593,6 +593,15 @@ static int hdev_probe_device(const char *filename) return 0; } +static void hdev_parse_filename(const char *filename, QDict *options, + Error **errp) +{ + /* The prefix is optional, just as for "file". */ + strstart(filename, "host_device:", &filename); + + qdict_put_obj(options, "filename", QOBJECT(qstring_from_str(filename))); +} + static int hdev_open(BlockDriverState *bs, QDict *options, int flags, Error **errp) { @@ -663,6 +672,7 @@ static BlockDriver bdrv_host_device = { .protocol_name = "host_device", .instance_size = sizeof(BDRVRawState), .bdrv_needs_filename = true, + .bdrv_parse_filename = hdev_parse_filename, .bdrv_probe_device = hdev_probe_device, .bdrv_file_open = hdev_open, .bdrv_close = raw_close, diff --git a/block/vhdx.h b/block/vhdx.h index 2acd7c2..8103d4c 100644 --- a/block/vhdx.h +++ b/block/vhdx.h @@ -61,7 +61,7 @@ /* These structures are ones that are defined in the VHDX specification * document */ -#define VHDX_FILE_SIGNATURE 0x656C696678646876 /* "vhdxfile" in ASCII */ +#define VHDX_FILE_SIGNATURE 0x656C696678646876ULL /* "vhdxfile" in ASCII */ typedef struct VHDXFileIdentifier { uint64_t signature; /* "vhdxfile" in ASCII */ uint16_t creator[256]; /* optional; utf-16 string to identify @@ -238,7 +238,7 @@ typedef struct QEMU_PACKED VHDXLogDataSector { /* upper 44 bits are the file offset in 1MB units lower 3 bits are the state other bits are reserved */ #define VHDX_BAT_STATE_BIT_MASK 0x07 -#define VHDX_BAT_FILE_OFF_MASK 0xFFFFFFFFFFF00000 /* upper 44 bits */ +#define VHDX_BAT_FILE_OFF_MASK 0xFFFFFFFFFFF00000ULL /* upper 44 bits */ typedef uint64_t VHDXBatEntry; /* ---- METADATA REGION STRUCTURES ---- */ @@ -247,7 +247,7 @@ typedef uint64_t VHDXBatEntry; #define VHDX_METADATA_MAX_ENTRIES 2047 /* not including the header */ #define VHDX_METADATA_TABLE_MAX_SIZE \ (VHDX_METADATA_ENTRY_SIZE * (VHDX_METADATA_MAX_ENTRIES+1)) -#define VHDX_METADATA_SIGNATURE 0x617461646174656D /* "metadata" in ASCII */ +#define VHDX_METADATA_SIGNATURE 0x617461646174656DULL /* "metadata" in ASCII */ typedef struct QEMU_PACKED VHDXMetadataTableHeader { uint64_t signature; /* "metadata" in ASCII */ uint16_t reserved; diff --git a/bsd-user/main.c b/bsd-user/main.c index f9246aa..f81ba55 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -1000,7 +1000,7 @@ int main(int argc, char **argv) memset(ts, 0, sizeof(TaskState)); init_task_state(ts); ts->info = info; - env->opaque = ts; + cpu->opaque = ts; #if defined(TARGET_I386) cpu_x86_set_cpl(env, 3); @@ -3822,6 +3822,11 @@ fi int128=no cat > $TMPC << EOF +#if defined(__clang_major__) && defined(__clang_minor__) +# if ((__clang_major__ < 3) || (__clang_major__ == 3) && (__clang_minor__ < 2)) +# error __int128_t does not work in CLANG before 3.2 +# endif +#endif __int128_t a; __uint128_t b; int main (void) { @@ -3863,7 +3868,7 @@ fi ########################################## # Do we have libnfs if test "$libnfs" != "no" ; then - if $pkg_config --atleast-version=1.9.2 libnfs; then + if $pkg_config --atleast-version=1.9.3 libnfs; then libnfs="yes" libnfs_libs=$($pkg_config --libs libnfs) LIBS="$LIBS $libnfs_libs" @@ -4094,7 +4099,11 @@ echo "vhost-net support $vhost_net" echo "vhost-scsi support $vhost_scsi" echo "Trace backend $trace_backend" echo "Trace output file $trace_file-<pid>" +if test "$spice" = "yes"; then echo "spice support $spice ($spice_protocol_version/$spice_server_version)" +else +echo "spice support $spice" +fi echo "rbd support $rbd" echo "xfsctl support $xfs" echo "nss used $smartcard_nss" @@ -4955,6 +4964,12 @@ for i in $ARCH $TARGET_BASE_ARCH ; do echo "CONFIG_ALPHA_DIS=y" >> $config_target_mak echo "CONFIG_ALPHA_DIS=y" >> config-all-disas.mak ;; + aarch64) + if test -n "${cxx}"; then + echo "CONFIG_ARM_A64_DIS=y" >> $config_target_mak + echo "CONFIG_ARM_A64_DIS=y" >> config-all-disas.mak + fi + ;; arm) echo "CONFIG_ARM_DIS=y" >> $config_target_mak echo "CONFIG_ARM_DIS=y" >> config-all-disas.mak @@ -23,29 +23,22 @@ #include "qemu/atomic.h" #include "sysemu/qtest.h" -bool qemu_cpu_has_work(CPUState *cpu) +void cpu_loop_exit(CPUState *cpu) { - return cpu_has_work(cpu); -} - -void cpu_loop_exit(CPUArchState *env) -{ - CPUState *cpu = ENV_GET_CPU(env); - cpu->current_tb = NULL; - siglongjmp(env->jmp_env, 1); + siglongjmp(cpu->jmp_env, 1); } /* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ #if defined(CONFIG_SOFTMMU) -void cpu_resume_from_signal(CPUArchState *env, void *puc) +void cpu_resume_from_signal(CPUState *cpu, void *puc) { /* XXX: restore cpu registers saved in host registers */ - env->exception_index = -1; - siglongjmp(env->jmp_env, 1); + cpu->exception_index = -1; + siglongjmp(cpu->jmp_env, 1); } #endif @@ -108,7 +101,7 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, if (max_cycles > CF_COUNT_MASK) max_cycles = CF_COUNT_MASK; - tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, + tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, max_cycles); cpu->current_tb = tb; /* execute the generated code */ @@ -123,6 +116,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, target_ulong cs_base, uint64_t flags) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb, **ptb1; unsigned int h; tb_page_addr_t phys_pc, phys_page1; @@ -160,7 +154,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, } not_found: /* if no translated code available, then translate it now */ - tb = tb_gen_code(env, pc, cs_base, flags, 0); + tb = tb_gen_code(cpu, pc, cs_base, flags, 0); found: /* Move the last found TB to the head of the list */ @@ -170,12 +164,13 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, tcg_ctx.tb_ctx.tb_phys_hash[h] = tb; } /* we add the TB in the virtual pc hash table */ - env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; + cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; return tb; } static inline TranslationBlock *tb_find_fast(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; int flags; @@ -184,7 +179,7 @@ static inline TranslationBlock *tb_find_fast(CPUArchState *env) always be the same before a given translated block is executed. */ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; + tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || tb->flags != flags)) { tb = tb_find_slow(env, pc, cs_base, flags); @@ -201,10 +196,11 @@ void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) static void cpu_handle_debug_exception(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp; - if (!env->watchpoint_hit) { - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + if (!cpu->watchpoint_hit) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { wp->flags &= ~BP_WATCHPOINT_HIT; } } @@ -283,16 +279,16 @@ int cpu_exec(CPUArchState *env) #else #error unsupported target CPU #endif - env->exception_index = -1; + cpu->exception_index = -1; /* prepare setjmp context for exception handling */ for(;;) { - if (sigsetjmp(env->jmp_env, 0) == 0) { + if (sigsetjmp(cpu->jmp_env, 0) == 0) { /* if an exception is pending, we execute it here */ - if (env->exception_index >= 0) { - if (env->exception_index >= EXCP_INTERRUPT) { + if (cpu->exception_index >= 0) { + if (cpu->exception_index >= EXCP_INTERRUPT) { /* exit request from the cpu execution loop */ - ret = env->exception_index; + ret = cpu->exception_index; if (ret == EXCP_DEBUG) { cpu_handle_debug_exception(env); } @@ -305,11 +301,11 @@ int cpu_exec(CPUArchState *env) #if defined(TARGET_I386) cc->do_interrupt(cpu); #endif - ret = env->exception_index; + ret = cpu->exception_index; break; #else cc->do_interrupt(cpu); - env->exception_index = -1; + cpu->exception_index = -1; #endif } } @@ -324,8 +320,8 @@ int cpu_exec(CPUArchState *env) } if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; - env->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu->exception_index = EXCP_DEBUG; + cpu_loop_exit(cpu); } #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ @@ -333,8 +329,8 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HALT) { cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; - env->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu->exception_index = EXCP_HLT; + cpu_loop_exit(cpu); } #endif #if defined(TARGET_I386) @@ -348,8 +344,8 @@ int cpu_exec(CPUArchState *env) cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); do_cpu_init(x86_cpu); - env->exception_index = EXCP_HALTED; - cpu_loop_exit(env); + cpu->exception_index = EXCP_HALTED; + cpu_loop_exit(cpu); } else if (interrupt_request & CPU_INTERRUPT_SIPI) { do_cpu_sipi(x86_cpu); } else if (env->hflags2 & HF2_GIF_MASK) { @@ -420,7 +416,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_LM32) if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -429,7 +425,7 @@ int cpu_exec(CPUArchState *env) && (env->sregs[SR_MSR] & MSR_IE) && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) && !(env->iflags & (D_FLAG | IMM_FLAG))) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -437,7 +433,7 @@ int cpu_exec(CPUArchState *env) if ((interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { /* Raise it */ - env->exception_index = EXCP_EXT_INTERRUPT; + cpu->exception_index = EXCP_EXT_INTERRUPT; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; @@ -454,7 +450,7 @@ int cpu_exec(CPUArchState *env) idx = EXCP_TICK; } if (idx >= 0) { - env->exception_index = idx; + cpu->exception_index = idx; cc->do_interrupt(cpu); next_tb = 0; } @@ -469,7 +465,7 @@ int cpu_exec(CPUArchState *env) if (((type == TT_EXTINT) && cpu_pil_allowed(env, pil)) || type != TT_EXTINT) { - env->exception_index = env->interrupt_index; + cpu->exception_index = env->interrupt_index; cc->do_interrupt(cpu); next_tb = 0; } @@ -478,7 +474,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ && !(env->daif & PSTATE_F)) { - env->exception_index = EXCP_FIQ; + cpu->exception_index = EXCP_FIQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -494,14 +490,14 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HARD && ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->daif & PSTATE_I))) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } #elif defined(TARGET_UNICORE32) if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_asr & ASR_I)) { - env->exception_index = UC32_EXCP_INTR; + cpu->exception_index = UC32_EXCP_INTR; cc->do_interrupt(cpu); next_tb = 0; } @@ -536,7 +532,7 @@ int cpu_exec(CPUArchState *env) } } if (idx >= 0) { - env->exception_index = idx; + cpu->exception_index = idx; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; @@ -546,7 +542,7 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HARD && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -558,7 +554,7 @@ int cpu_exec(CPUArchState *env) m_flag_archval = M_FLAG_V32; } if ((env->pregs[PR_CCS] & m_flag_archval)) { - env->exception_index = EXCP_NMI; + cpu->exception_index = EXCP_NMI; cc->do_interrupt(cpu); next_tb = 0; } @@ -572,7 +568,7 @@ int cpu_exec(CPUArchState *env) hardware doesn't rely on this, so we provide/save the vector when the interrupt is first signalled. */ - env->exception_index = env->pending_vector; + cpu->exception_index = env->pending_vector; do_interrupt_m68k_hardirq(env); next_tb = 0; } @@ -584,7 +580,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_XTENSA) if (interrupt_request & CPU_INTERRUPT_HARD) { - env->exception_index = EXC_IRQ; + cpu->exception_index = EXC_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -600,8 +596,8 @@ int cpu_exec(CPUArchState *env) } if (unlikely(cpu->exit_request)) { cpu->exit_request = 0; - env->exception_index = EXCP_INTERRUPT; - cpu_loop_exit(env); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit(cpu); } spin_lock(&tcg_ctx.tb_ctx.tb_lock); tb = tb_find_fast(env); @@ -654,25 +650,25 @@ int cpu_exec(CPUArchState *env) /* Instruction counter expired. */ int insns_left; tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); - insns_left = env->icount_decr.u32; - if (env->icount_extra && insns_left >= 0) { + insns_left = cpu->icount_decr.u32; + if (cpu->icount_extra && insns_left >= 0) { /* Refill decrementer and continue execution. */ - env->icount_extra += insns_left; - if (env->icount_extra > 0xffff) { + cpu->icount_extra += insns_left; + if (cpu->icount_extra > 0xffff) { insns_left = 0xffff; } else { - insns_left = env->icount_extra; + insns_left = cpu->icount_extra; } - env->icount_extra -= insns_left; - env->icount_decr.u16.low = insns_left; + cpu->icount_extra -= insns_left; + cpu->icount_decr.u16.low = insns_left; } else { if (insns_left > 0) { /* Execute remaining instructions. */ cpu_exec_nocache(env, insns_left, tb); } - env->exception_index = EXCP_INTERRUPT; + cpu->exception_index = EXCP_INTERRUPT; next_tb = 0; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } break; } @@ -76,7 +76,7 @@ static bool cpu_thread_is_idle(CPUState *cpu) if (cpu_is_stopped(cpu)) { return true; } - if (!cpu->halted || qemu_cpu_has_work(cpu) || + if (!cpu->halted || cpu_has_work(cpu) || kvm_halt_in_kernel()) { return false; } @@ -139,11 +139,10 @@ static int64_t cpu_get_icount_locked(void) icount = qemu_icount; if (cpu) { - CPUArchState *env = cpu->env_ptr; - if (!can_do_io(env)) { + if (!cpu_can_do_io(cpu)) { fprintf(stderr, "Bad clock read\n"); } - icount -= (env->icount_decr.u16.low + env->icount_extra); + icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); } return qemu_icount_bias + (icount << icount_time_shift); } @@ -1236,6 +1235,7 @@ int vm_stop_force_state(RunState state) static int tcg_cpu_exec(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); int ret; #ifdef CONFIG_PROFILER int64_t ti; @@ -1248,9 +1248,9 @@ static int tcg_cpu_exec(CPUArchState *env) int64_t count; int64_t deadline; int decr; - qemu_icount -= (env->icount_decr.u16.low + env->icount_extra); - env->icount_decr.u16.low = 0; - env->icount_extra = 0; + qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); + cpu->icount_decr.u16.low = 0; + cpu->icount_extra = 0; deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL); /* Maintain prior (possibly buggy) behaviour where if no deadline @@ -1266,8 +1266,8 @@ static int tcg_cpu_exec(CPUArchState *env) qemu_icount += count; decr = (count > 0xffff) ? 0xffff : count; count -= decr; - env->icount_decr.u16.low = decr; - env->icount_extra = count; + cpu->icount_decr.u16.low = decr; + cpu->icount_extra = count; } ret = cpu_exec(env); #ifdef CONFIG_PROFILER @@ -1276,10 +1276,9 @@ static int tcg_cpu_exec(CPUArchState *env) if (use_icount) { /* Fold pending instructions back into the instruction counter, and clear the interrupt flag. */ - qemu_icount -= (env->icount_decr.u16.low - + env->icount_extra); - env->icount_decr.u32 = 0; - env->icount_extra = 0; + qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); + cpu->icount_decr.u32 = 0; + cpu->icount_extra = 0; } return ret; } @@ -46,9 +46,9 @@ int tlb_flush_count; * entries from the TLB at any time, so flushing more entries than * required is only an efficiency issue, not a correctness issue. */ -void tlb_flush(CPUArchState *env, int flush_global) +void tlb_flush(CPUState *cpu, int flush_global) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; #if defined(DEBUG_TLB) printf("tlb_flush:\n"); @@ -58,7 +58,7 @@ void tlb_flush(CPUArchState *env, int flush_global) cpu->current_tb = NULL; memset(env->tlb_table, -1, sizeof(env->tlb_table)); - memset(env->tb_jmp_cache, 0, sizeof(env->tb_jmp_cache)); + memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; @@ -77,9 +77,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) } } -void tlb_flush_page(CPUArchState *env, target_ulong addr) +void tlb_flush_page(CPUState *cpu, target_ulong addr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; int i; int mmu_idx; @@ -93,7 +93,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr) TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", env->tlb_flush_addr, env->tlb_flush_mask); #endif - tlb_flush(env, 1); + tlb_flush(cpu, 1); return; } /* must reset current TB so that interrupts cannot modify the @@ -106,7 +106,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr) tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); } - tb_flush_jmp_cache(env, addr); + tb_flush_jmp_cache(cpu, addr); } /* update the TLBs so that writes to code in the virtual page 'addr' @@ -119,7 +119,7 @@ void tlb_protect_code(ram_addr_t ram_addr) /* update the TLB so that writes in physical page 'phys_addr' are no longer tested for self modifying code */ -void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, +void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr) { cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE); @@ -221,10 +221,11 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, /* Add a new TLB entry. At most one entry for a given virtual address is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the supplied size is only used by tlb_flush_page. */ -void tlb_set_page(CPUArchState *env, target_ulong vaddr, +void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) { + CPUArchState *env = cpu->env_ptr; MemoryRegionSection *section; unsigned int index; target_ulong address; @@ -232,7 +233,6 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, uintptr_t addend; CPUTLBEntry *te; hwaddr iotlb, xlat, sz; - CPUState *cpu = ENV_GET_CPU(env); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { @@ -261,7 +261,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, } code_address = address; - iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat, + iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat, prot, &address); index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); @@ -322,7 +322,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) if (cc->do_unassigned_access) { cc->do_unassigned_access(cpu, addr, false, true, 0, 4); } else { - cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" + cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); } } diff --git a/device-hotplug.c b/device-hotplug.c index 103d34a..ebfa6b1 100644 --- a/device-hotplug.c +++ b/device-hotplug.c @@ -33,12 +33,14 @@ DriveInfo *add_init_drive(const char *optstr) { DriveInfo *dinfo; QemuOpts *opts; + MachineClass *mc; opts = drive_def(optstr); if (!opts) return NULL; - dinfo = drive_init(opts, current_machine->block_default_type); + mc = MACHINE_GET_CLASS(current_machine); + dinfo = drive_init(opts, mc->qemu_machine->block_default_type); if (!dinfo) { qemu_opts_del(opts); return NULL; diff --git a/disas/libvixl/a64/disasm-a64.cc b/disas/libvixl/a64/disasm-a64.cc index 5c6b898..5f172da 100644 --- a/disas/libvixl/a64/disasm-a64.cc +++ b/disas/libvixl/a64/disasm-a64.cc @@ -1342,7 +1342,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, ASSERT(format[5] == 'L'); AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide()); if (instr->ShiftMoveWide() > 0) { - AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide()); + AppendToOutput(", lsl #%" PRId64, 16 * instr->ShiftMoveWide()); } } return 8; @@ -1391,7 +1391,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, } case 'F': { // IFPSingle, IFPDouble or IFPFBits. if (format[3] == 'F') { // IFPFbits. - AppendToOutput("#%d", 64 - instr->FPScale()); + AppendToOutput("#%" PRId64, 64 - instr->FPScale()); return 8; } else { AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(), @@ -1412,23 +1412,23 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, return 5; } case 'P': { // IP - Conditional compare. - AppendToOutput("#%d", instr->ImmCondCmp()); + AppendToOutput("#%" PRId64, instr->ImmCondCmp()); return 2; } case 'B': { // Bitfields. return SubstituteBitfieldImmediateField(instr, format); } case 'E': { // IExtract. - AppendToOutput("#%d", instr->ImmS()); + AppendToOutput("#%" PRId64, instr->ImmS()); return 8; } case 'S': { // IS - Test and branch bit. - AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) | - instr->ImmTestBranchBit40()); + AppendToOutput("#%" PRId64, (instr->ImmTestBranchBit5() << 5) | + instr->ImmTestBranchBit40()); return 2; } case 'D': { // IDebug - HLT and BRK instructions. - AppendToOutput("#0x%x", instr->ImmException()); + AppendToOutput("#0x%" PRIx64, instr->ImmException()); return 6; } default: { @@ -1598,12 +1598,12 @@ int Disassembler::SubstituteExtendField(Instruction* instr, (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || (instr->ExtendMode() == UXTX))) { if (instr->ImmExtendShift() > 0) { - AppendToOutput(", lsl #%d", instr->ImmExtendShift()); + AppendToOutput(", lsl #%" PRId64, instr->ImmExtendShift()); } } else { AppendToOutput(", %s", extend_mode[instr->ExtendMode()]); if (instr->ImmExtendShift() > 0) { - AppendToOutput(" #%d", instr->ImmExtendShift()); + AppendToOutput(" #%" PRId64, instr->ImmExtendShift()); } } return 3; @@ -1632,7 +1632,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr, if (!((ext == UXTX) && (shift == 0))) { AppendToOutput(", %s", extend_mode[ext]); if (shift != 0) { - AppendToOutput(" #%d", instr->SizeLS()); + AppendToOutput(" #%" PRId64, instr->SizeLS()); } } return 9; diff --git a/docs/qapi-code-gen.txt b/docs/qapi-code-gen.txt index 0728f36..d78921f 100644 --- a/docs/qapi-code-gen.txt +++ b/docs/qapi-code-gen.txt @@ -123,11 +123,12 @@ And it looks like this on the wire: Flat union types avoid the nesting on the wire. They are used whenever a specific field of the base type is declared as the discriminator ('type' is -then no longer generated). The discriminator must always be a string field. +then no longer generated). The discriminator must be of enumeration type. The above example can then be modified as follows: + { 'enum': 'BlockdevDriver', 'data': [ 'raw', 'qcow2' ] } { 'type': 'BlockdevCommonOptions', - 'data': { 'driver': 'str', 'readonly': 'bool' } } + 'data': { 'driver': 'BlockdevDriver', 'readonly': 'bool' } } { 'union': 'BlockdevOptions', 'base': 'BlockdevCommonOptions', 'discriminator': 'driver', diff --git a/docs/qemupciserial.inf b/docs/qemupciserial.inf index 3474310..6f7eef4 100644 --- a/docs/qemupciserial.inf +++ b/docs/qemupciserial.inf @@ -11,99 +11,92 @@ ; (Com+Lpt)" from the list. Click "Have a disk". Select this file. ; Procedure may vary a bit depending on the windows version. -; FIXME: This file covers the single port version only. +; This file covers all options: pci-serial, pci-serial-2x, pci-serial-4x +; for both 32 and 64 bit platforms. [Version] -Signature="$CHICAGO$" -Class=Ports -ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} +Signature="$Windows NT$" +Class=MultiFunction +ClassGUID={4d36e971-e325-11ce-bfc1-08002be10318} Provider=%QEMU% -DriverVer=09/24/2012,1.3.0 - -[SourceDisksNames] -3426=windows cd - -[SourceDisksFiles] -serial.sys = 3426 -serenum.sys = 3426 - -[DestinationDirs] -DefaultDestDir = 11 ;LDID_SYS -ComPort.NT.Copy = 12 ;DIRID_DRIVERS -SerialEnumerator.NT.Copy=12 ;DIRID_DRIVERS - -; Drivers -;---------------------------------------------------------- +DriverVer=12/29/2013,1.3.0 +[ControlFlags] +ExcludeFromSelect=* [Manufacturer] -%QEMU%=QEMU,NTx86 +%QEMU%=QEMU,NTx86,NTAMD64 [QEMU.NTx86] -%QEMU-PCI_SERIAL.DeviceDesc% = ComPort, "PCI\VEN_1b36&DEV_0002&CC_0700" - -; COM sections -;---------------------------------------------------------- -[ComPort.AddReg] -HKR,,PortSubClass,1,01 - -[ComPort.NT] -AddReg=ComPort.AddReg, ComPort.NT.AddReg -LogConfig=caa -SyssetupPnPFlags = 1 - -[ComPort.NT.HW] -AddReg=ComPort.NT.HW.AddReg - -[ComPort.NT.AddReg] -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[ComPort.NT.HW.AddReg] -HKR,,"UpperFilters",0x00010000,"serenum" - -;-------------- Service installation -; Port Driver (function driver for this device) -[ComPort.NT.Services] -AddService = Serial, 0x00000002, Serial_Service_Inst, Serial_EventLog_Inst -AddService = Serenum,,Serenum_Service_Inst - -; -------------- Serial Port Driver install sections -[Serial_Service_Inst] -DisplayName = %Serial.SVCDESC% -ServiceType = 1 ; SERVICE_KERNEL_DRIVER -StartType = 1 ; SERVICE_SYSTEM_START (this driver may do detection) -ErrorControl = 0 ; SERVICE_ERROR_IGNORE -ServiceBinary = %12%\serial.sys -LoadOrderGroup = Extended base - -; -------------- Serenum Driver install section -[Serenum_Service_Inst] -DisplayName = %Serenum.SVCDESC% -ServiceType = 1 ; SERVICE_KERNEL_DRIVER -StartType = 3 ; SERVICE_DEMAND_START -ErrorControl = 1 ; SERVICE_ERROR_NORMAL -ServiceBinary = %12%\serenum.sys -LoadOrderGroup = PNP Filter - -[Serial_EventLog_Inst] -AddReg = Serial_EventLog_AddReg - -[Serial_EventLog_AddReg] -HKR,,EventMessageFile,0x00020000,"%%SystemRoot%%\System32\IoLogMsg.dll;%%SystemRoot%%\System32\drivers\serial.sys" -HKR,,TypesSupported,0x00010001,7 - -; The following sections are COM port resource configs. -; Section name format means: -; Char 1 = c (COM port) -; Char 2 = I/O config: 1 (3f8), 2 (2f8), 3 (3e8), 4 (2e8), a (any) -; Char 3 = IRQ config: #, a (any) - -[caa] ; Any base, any IRQ -ConfigPriority=HARDRECONFIG -IOConfig=8@100-ffff%fff8(3ff::) -IRQConfig=S:3,4,5,7,9,10,11,12,14,15 +%QEMU-PCI_SERIAL_1_PORT%=ComPort_inst1, PCI\VEN_1B36&DEV_0002 +%QEMU-PCI_SERIAL_2_PORT%=ComPort_inst2, PCI\VEN_1B36&DEV_0003 +%QEMU-PCI_SERIAL_4_PORT%=ComPort_inst4, PCI\VEN_1B36&DEV_0004 + +[QEMU.NTAMD64] +%QEMU-PCI_SERIAL_1_PORT%=ComPort_inst1, PCI\VEN_1B36&DEV_0002 +%QEMU-PCI_SERIAL_2_PORT%=ComPort_inst2, PCI\VEN_1B36&DEV_0003 +%QEMU-PCI_SERIAL_4_PORT%=ComPort_inst4, PCI\VEN_1B36&DEV_0004 + +[ComPort_inst1] +Include=mf.inf +Needs=MFINSTALL.mf + +[ComPort_inst2] +Include=mf.inf +Needs=MFINSTALL.mf + +[ComPort_inst4] +Include=mf.inf +Needs=MFINSTALL.mf + +[ComPort_inst1.HW] +AddReg=ComPort_inst1.RegHW + +[ComPort_inst2.HW] +AddReg=ComPort_inst2.RegHW + +[ComPort_inst4.HW] +AddReg=ComPort_inst4.RegHW + +[ComPort_inst1.Services] +Include=mf.inf +Needs=MFINSTALL.mf.Services + +[ComPort_inst2.Services] +Include=mf.inf +Needs=MFINSTALL.mf.Services + +[ComPort_inst4.Services] +Include=mf.inf +Needs=MFINSTALL.mf.Services + +[ComPort_inst1.RegHW] +HKR,Child0000,HardwareID,,*PNP0501 +HKR,Child0000,VaryingResourceMap,1,00, 00,00,00,00, 08,00,00,00 +HKR,Child0000,ResourceMap,1,02 + +[ComPort_inst2.RegHW] +HKR,Child0000,HardwareID,,*PNP0501 +HKR,Child0000,VaryingResourceMap,1,00, 00,00,00,00, 08,00,00,00 +HKR,Child0000,ResourceMap,1,02 +HKR,Child0001,HardwareID,,*PNP0501 +HKR,Child0001,VaryingResourceMap,1,00, 08,00,00,00, 08,00,00,00 +HKR,Child0001,ResourceMap,1,02 + +[ComPort_inst4.RegHW] +HKR,Child0000,HardwareID,,*PNP0501 +HKR,Child0000,VaryingResourceMap,1,00, 00,00,00,00, 08,00,00,00 +HKR,Child0000,ResourceMap,1,02 +HKR,Child0001,HardwareID,,*PNP0501 +HKR,Child0001,VaryingResourceMap,1,00, 08,00,00,00, 08,00,00,00 +HKR,Child0001,ResourceMap,1,02 +HKR,Child0002,HardwareID,,*PNP0501 +HKR,Child0002,VaryingResourceMap,1,00, 10,00,00,00, 08,00,00,00 +HKR,Child0002,ResourceMap,1,02 +HKR,Child0003,HardwareID,,*PNP0501 +HKR,Child0003,VaryingResourceMap,1,00, 18,00,00,00, 08,00,00,00 +HKR,Child0003,ResourceMap,1,02 [Strings] QEMU="QEMU" -QEMU-PCI_SERIAL.DeviceDesc="QEMU Serial PCI Card" - -Serial.SVCDESC = "Serial port driver" -Serenum.SVCDESC = "Serenum Filter Driver" +QEMU-PCI_SERIAL_1_PORT="1x QEMU PCI Serial Card" +QEMU-PCI_SERIAL_2_PORT="2x QEMU PCI Serial Card" +QEMU-PCI_SERIAL_4_PORT="4x QEMU PCI Serial Card" @@ -33,6 +33,7 @@ #include "hw/xen/xen.h" #include "qemu/timer.h" #include "qemu/config-file.h" +#include "qemu/error-report.h" #include "exec/memory.h" #include "sysemu/dma.h" #include "exec/address-spaces.h" @@ -419,7 +420,7 @@ static int cpu_common_post_load(void *opaque, int version_id) /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the version_id is increased. */ cpu->interrupt_request &= ~0x01; - tlb_flush(cpu->env_ptr, 1); + tlb_flush(cpu, 1); return 0; } @@ -484,8 +485,8 @@ void cpu_exec_init(CPUArchState *env) } cpu->cpu_index = cpu_index; cpu->numa_node = 0; - QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->breakpoints); + QTAILQ_INIT(&cpu->watchpoints); #ifndef CONFIG_USER_ONLY cpu->as = &address_space_memory; cpu->thread_id = qemu_get_thread_id(); @@ -527,29 +528,29 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) #endif /* TARGET_HAS_ICE */ #if defined(CONFIG_USER_ONLY) -void cpu_watchpoint_remove_all(CPUArchState *env, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { } -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { return -ENOSYS; } #else /* Add a watchpoint. */ -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { - target_ulong len_mask = ~(len - 1); + vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ if ((len & (len - 1)) || (addr & ~len_mask) || len == 0 || len > TARGET_PAGE_SIZE) { - fprintf(stderr, "qemu: tried to set invalid watchpoint at " - TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); + error_report("tried to set invalid watchpoint at %" + VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); return -EINVAL; } wp = g_malloc(sizeof(*wp)); @@ -559,12 +560,13 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len wp->flags = flags; /* keep all GDB-injected watchpoints in front */ - if (flags & BP_GDB) - QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); - else - QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); + if (flags & BP_GDB) { + QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); + } else { + QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); + } - tlb_flush_page(env, addr); + tlb_flush_page(cpu, addr); if (watchpoint) *watchpoint = wp; @@ -572,16 +574,16 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len } /* Remove a specific watchpoint. */ -int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags) { - target_ulong len_mask = ~(len - 1); + vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (addr == wp->vaddr && len_mask == wp->len_mask && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { - cpu_watchpoint_remove_by_ref(env, wp); + cpu_watchpoint_remove_by_ref(cpu, wp); return 0; } } @@ -589,29 +591,30 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len } /* Remove a specific watchpoint by reference. */ -void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) { - QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); + QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); - tlb_flush_page(env, watchpoint->vaddr); + tlb_flush_page(cpu, watchpoint->vaddr); g_free(watchpoint); } /* Remove all matching watchpoints. */ -void cpu_watchpoint_remove_all(CPUArchState *env, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { CPUWatchpoint *wp, *next; - QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { - if (wp->flags & mask) - cpu_watchpoint_remove_by_ref(env, wp); + QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { + if (wp->flags & mask) { + cpu_watchpoint_remove_by_ref(cpu, wp); + } } } #endif /* Add a breakpoint. */ -int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint) { #if defined(TARGET_HAS_ICE) @@ -624,12 +627,12 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, /* keep all GDB-injected breakpoints in front */ if (flags & BP_GDB) { - QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); + QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); } else { - QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); + QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } - breakpoint_invalidate(ENV_GET_CPU(env), pc); + breakpoint_invalidate(cpu, pc); if (breakpoint) { *breakpoint = bp; @@ -641,14 +644,14 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, } /* Remove a specific breakpoint. */ -int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) { #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == pc && bp->flags == flags) { - cpu_breakpoint_remove_by_ref(env, bp); + cpu_breakpoint_remove_by_ref(cpu, bp); return 0; } } @@ -659,26 +662,27 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) } /* Remove a specific breakpoint by reference. */ -void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) { #if defined(TARGET_HAS_ICE) - QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); + QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); - breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc); + breakpoint_invalidate(cpu, breakpoint->pc); g_free(breakpoint); #endif } /* Remove all matching breakpoints. */ -void cpu_breakpoint_remove_all(CPUArchState *env, int mask) +void cpu_breakpoint_remove_all(CPUState *cpu, int mask) { #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp, *next; - QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { - if (bp->flags & mask) - cpu_breakpoint_remove_by_ref(env, bp); + QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { + if (bp->flags & mask) { + cpu_breakpoint_remove_by_ref(cpu, bp); + } } #endif } @@ -702,9 +706,8 @@ void cpu_single_step(CPUState *cpu, int enabled) #endif } -void cpu_abort(CPUArchState *env, const char *fmt, ...) +void cpu_abort(CPUState *cpu, const char *fmt, ...) { - CPUState *cpu = ENV_GET_CPU(env); va_list ap; va_list ap2; @@ -792,7 +795,7 @@ static void cpu_physical_memory_set_dirty_tracking(bool enable) in_migration = enable; } -hwaddr memory_region_section_get_iotlb(CPUArchState *env, +hwaddr memory_region_section_get_iotlb(CPUState *cpu, MemoryRegionSection *section, target_ulong vaddr, hwaddr paddr, hwaddr xlat, @@ -818,7 +821,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env, /* Make accesses to pages with watchpoints go via the watchpoint trap routines. */ - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { /* Avoid trapping reads of pages with a write breakpoint. */ if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { @@ -1029,7 +1032,7 @@ static void *file_ram_alloc(RAMBlock *block, hpagesize = gethugepagesize(path); if (!hpagesize) { - return NULL; + goto error; } if (memory < hpagesize) { @@ -1038,7 +1041,7 @@ static void *file_ram_alloc(RAMBlock *block, if (kvm_enabled() && !kvm_has_sync_mmu()) { fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); - return NULL; + goto error; } /* Make name safe to use with mkstemp by replacing '/' with '_'. */ @@ -1056,7 +1059,7 @@ static void *file_ram_alloc(RAMBlock *block, if (fd < 0) { perror("unable to create backing store for hugepages"); g_free(filename); - return NULL; + goto error; } unlink(filename); g_free(filename); @@ -1076,7 +1079,7 @@ static void *file_ram_alloc(RAMBlock *block, if (area == MAP_FAILED) { perror("file_ram_alloc: can't mmap RAM pages"); close(fd); - return (NULL); + goto error; } if (mem_prealloc) { @@ -1120,6 +1123,12 @@ static void *file_ram_alloc(RAMBlock *block, block->fd = fd; return area; + +error: + if (mem_prealloc) { + exit(1); + } + return NULL; } #else static void *file_ram_alloc(RAMBlock *block, @@ -1547,7 +1556,7 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr, flushed */ if (!cpu_physical_memory_is_clean(ram_addr)) { CPUArchState *env = current_cpu->env_ptr; - tlb_set_dirty(env, env->mem_io_vaddr); + tlb_set_dirty(env, current_cpu->mem_io_vaddr); } } @@ -1566,34 +1575,35 @@ static const MemoryRegionOps notdirty_mem_ops = { /* Generate a debug exception if a watchpoint has been hit. */ static void check_watchpoint(int offset, int len_mask, int flags) { - CPUArchState *env = current_cpu->env_ptr; + CPUState *cpu = current_cpu; + CPUArchState *env = cpu->env_ptr; target_ulong pc, cs_base; target_ulong vaddr; CPUWatchpoint *wp; int cpu_flags; - if (env->watchpoint_hit) { + if (cpu->watchpoint_hit) { /* We re-entered the check after replacing the TB. Now raise * the debug interrupt so that is will trigger after the * current instruction. */ - cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG); + cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); return; } - vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if ((vaddr == (wp->vaddr & len_mask) || (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { wp->flags |= BP_WATCHPOINT_HIT; - if (!env->watchpoint_hit) { - env->watchpoint_hit = wp; - tb_check_watchpoint(env); + if (!cpu->watchpoint_hit) { + cpu->watchpoint_hit = wp; + tb_check_watchpoint(cpu); if (wp->flags & BP_STOP_BEFORE_ACCESS) { - env->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu->exception_index = EXCP_DEBUG; + cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); - tb_gen_code(env, pc, cs_base, cpu_flags, 1); - cpu_resume_from_signal(env, NULL); + tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); + cpu_resume_from_signal(cpu, NULL); } } } else { @@ -1824,14 +1834,12 @@ static void tcg_commit(MemoryListener *listener) reset the modified entries */ /* XXX: slow ! */ CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - /* FIXME: Disentangle the cpu.h circular files deps so we can directly get the right CPU from listener. */ if (cpu->tcg_as_listener != listener) { continue; } - tlb_flush(env, 1); + tlb_flush(cpu, 1); } } diff --git a/fpu/softfloat.c b/fpu/softfloat.c index fc0b179..5f02c16 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -288,7 +288,7 @@ INLINE flag extractFloat32Sign( float32 a ) | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the value. *----------------------------------------------------------------------------*/ -static float32 float32_squash_input_denormal(float32 a STATUS_PARAM) +float32 float32_squash_input_denormal(float32 a STATUS_PARAM) { if (STATUS(flush_inputs_to_zero)) { if (extractFloat32Exp(a) == 0 && extractFloat32Frac(a) != 0) { @@ -473,7 +473,7 @@ INLINE flag extractFloat64Sign( float64 a ) | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the value. *----------------------------------------------------------------------------*/ -static float64 float64_squash_input_denormal(float64 a STATUS_PARAM) +float64 float64_squash_input_denormal(float64 a STATUS_PARAM) { if (STATUS(flush_inputs_to_zero)) { if (extractFloat64Exp(a) == 0 && extractFloat64Frac(a) != 0) { @@ -635,7 +635,6 @@ static const int xlat_gdb_type[] = { static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) { CPUState *cpu; - CPUArchState *env; int err = 0; if (kvm_enabled()) { @@ -646,10 +645,10 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL); - if (err) + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { break; + } } return err; #ifndef CONFIG_USER_ONLY @@ -657,8 +656,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type], + err = cpu_watchpoint_insert(cpu, addr, len, xlat_gdb_type[type], NULL); if (err) break; @@ -673,7 +671,6 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) { CPUState *cpu; - CPUArchState *env; int err = 0; if (kvm_enabled()) { @@ -684,10 +681,10 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_breakpoint_remove(env, addr, BP_GDB); - if (err) + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { break; + } } return err; #ifndef CONFIG_USER_ONLY @@ -695,8 +692,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]); + err = cpu_watchpoint_remove(cpu, addr, len, xlat_gdb_type[type]); if (err) break; } @@ -710,7 +706,6 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) static void gdb_breakpoint_remove_all(void) { CPUState *cpu; - CPUArchState *env; if (kvm_enabled()) { kvm_remove_all_breakpoints(gdbserver_state->c_cpu); @@ -718,10 +713,9 @@ static void gdb_breakpoint_remove_all(void) } CPU_FOREACH(cpu) { - env = cpu->env_ptr; - cpu_breakpoint_remove_all(env, BP_GDB); + cpu_breakpoint_remove_all(cpu, BP_GDB); #ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(env, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); #endif } } @@ -1086,8 +1080,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) } #ifdef CONFIG_USER_ONLY else if (strncmp(p, "Offsets", 7) == 0) { - CPUArchState *env = s->c_cpu->env_ptr; - TaskState *ts = env->opaque; + TaskState *ts = s->c_cpu->opaque; snprintf(buf, sizeof(buf), "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx @@ -1205,8 +1198,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) } switch (state) { case RUN_STATE_DEBUG: - if (env->watchpoint_hit) { - switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) { + if (cpu->watchpoint_hit) { + switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) { case BP_MEM_READ: type = "r"; break; @@ -1220,8 +1213,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) snprintf(buf, sizeof(buf), "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", GDB_SIGNAL_TRAP, cpu_index(cpu), type, - env->watchpoint_hit->vaddr); - env->watchpoint_hit = NULL; + (target_ulong)cpu->watchpoint_hit->vaddr); + cpu->watchpoint_hit = NULL; goto send_packet; } tb_flush(env); @@ -1594,13 +1587,16 @@ int gdbserver_start(int port) /* Disable gdb stub for child processes. */ void gdbserver_fork(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); GDBState *s = gdbserver_state; - if (gdbserver_fd < 0 || s->fd < 0) - return; + + if (gdbserver_fd < 0 || s->fd < 0) { + return; + } close(s->fd); s->fd = -1; - cpu_breakpoint_remove_all(env, BP_GDB); - cpu_watchpoint_remove_all(env, BP_GDB); + cpu_breakpoint_remove_all(cpu, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); } #else static int gdb_chr_can_receive(void *opaque) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 9f137e9..6426d16 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -143,11 +143,21 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, unsigned long mem_size; DeviceState *dev; SysBusDevice *busdev; + ObjectClass *cpu_oc; + + cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); + assert(cpu_oc); for (n = 0; n < EXYNOS4210_NCPUS; n++) { - s->cpu[n] = cpu_arm_init("cortex-a9"); - if (!s->cpu[n]) { - fprintf(stderr, "Unable to find CPU %d definition\n", n); + Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Error *err = NULL; + + s->cpu[n] = ARM_CPU(cpuobj); + object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, + "reset-cbar", &error_abort); + object_property_set_bool(cpuobj, true, "realized", &err); + if (err) { + error_report("%s", error_get_pretty(err)); exit(1); } } diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index d10b5db..de54201 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -110,10 +110,10 @@ #define MP_PHY_88E3015 0x01410E20 /* TX descriptor status */ -#define MP_ETH_TX_OWN (1 << 31) +#define MP_ETH_TX_OWN (1U << 31) /* RX descriptor status */ -#define MP_ETH_RX_OWN (1 << 31) +#define MP_ETH_RX_OWN (1U << 31) /* Interrupt cause/mask bits */ #define MP_ETH_IRQ_RX_BIT 0 diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 47511d2..b433748 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -809,22 +809,26 @@ static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, uint32_t diff, uint32_t value) { if (s->compat1509) { - if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ - omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), - (value >> 31) & 1); - if (diff & (1 << 1)) /* CLK32K */ - omap_clk_onoff(omap_findclk(s, "clk32k_out"), - (~value >> 1) & 1); + if (diff & (1U << 31)) { + /* MCBSP3_CLK_HIZ_DI */ + omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); + } + if (diff & (1 << 1)) { + /* CLK32K */ + omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); + } } } static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, uint32_t diff, uint32_t value) { - if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ - omap_clk_reparent(omap_findclk(s, "uart3_ck"), - omap_findclk(s, ((value >> 31) & 1) ? - "ck_48m" : "armper_ck")); + if (diff & (1U << 31)) { + /* CONF_MOD_UART3_CLK_MODE_R */ + omap_clk_reparent(omap_findclk(s, "uart3_ck"), + omap_findclk(s, ((value >> 31) & 1) ? + "ck_48m" : "armper_ck")); + } if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ omap_clk_reparent(omap_findclk(s, "uart2_ck"), omap_findclk(s, ((value >> 30) & 1) ? diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 904277a..0429148 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -259,7 +259,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, case 1: /* Idle */ - if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ + if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); break; } @@ -496,7 +496,7 @@ typedef struct { #define SSCR0_SSE (1 << 7) #define SSCR0_RIM (1 << 22) #define SSCR0_TIM (1 << 23) -#define SSCR0_MOD (1 << 31) +#define SSCR0_MOD (1U << 31) #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) #define SSCR1_RIE (1 << 0) #define SSCR1_TIE (1 << 1) @@ -1006,7 +1006,7 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr, switch (addr) { case RTTR: - if (!(s->rttr & (1 << 31))) { + if (!(s->rttr & (1U << 31))) { pxa2xx_rtc_hzupdate(s); s->rttr = value; pxa2xx_rtc_alarm_update(s, s->rtsr); diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c index ca77f56..0727428 100644 --- a/hw/arm/pxa2xx_gpio.c +++ b/hw/arm/pxa2xx_gpio.c @@ -110,7 +110,7 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level) } bank = line >> 5; - mask = 1 << (line & 31); + mask = 1U << (line & 31); if (level) { s->status[bank] |= s->rising[bank] & mask & diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 345fa4a..d37fb54 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -105,7 +105,7 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) { irq = s->priority[i] & 0x3f; - if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) { + if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) { /* Source peripheral ID is valid. */ bit = 1 << (irq & 31); int_set = (irq >= 32); @@ -119,7 +119,7 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { if (mask[int_set] & bit & ~s->is_fiq[int_set]) { /* IRQ asserted */ ichp &= 0x0000ffff; - ichp |= (1 << 31) | (irq << 16); + ichp |= (1U << 31) | (irq << 16); } } } diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 6ef7646..7e04e50 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -18,6 +18,7 @@ #include "hw/i2c/i2c.h" #include "sysemu/blockdev.h" #include "exec/address-spaces.h" +#include "qemu/error-report.h" #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 @@ -49,6 +50,7 @@ static void realview_init(QEMUMachineInitArgs *args, { ARMCPU *cpu = NULL; CPUARMState *env; + ObjectClass *cpu_oc; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram_lo = g_new(MemoryRegion, 1); MemoryRegion *ram_hi = g_new(MemoryRegion, 1); @@ -70,12 +72,14 @@ static void realview_init(QEMUMachineInitArgs *args, uint32_t sys_id; ram_addr_t low_ram_size; ram_addr_t ram_size = args->ram_size; + hwaddr periphbase = 0; switch (board_type) { case BOARD_EB: break; case BOARD_EB_MPCORE: is_mpcore = 1; + periphbase = 0x10100000; break; case BOARD_PB_A8: is_pb = 1; @@ -83,16 +87,37 @@ static void realview_init(QEMUMachineInitArgs *args, case BOARD_PBX_A9: is_mpcore = 1; is_pb = 1; + periphbase = 0x1f000000; break; } + + cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, args->cpu_model); + if (!cpu_oc) { + fprintf(stderr, "Unable to find CPU definition\n"); + exit(1); + } + for (n = 0; n < smp_cpus; n++) { - cpu = cpu_arm_init(args->cpu_model); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); + Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Error *err = NULL; + + if (is_pb && is_mpcore) { + object_property_set_int(cpuobj, periphbase, "reset-cbar", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + } + + object_property_set_bool(cpuobj, true, "realized", &err); + if (err) { + error_report("%s", error_get_pretty(err)); exit(1); } - cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); + + cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); } + cpu = ARM_CPU(first_cpu); env = &cpu->env; if (arm_feature(env, ARM_FEATURE_V7)) { if (is_mpcore) { @@ -141,16 +166,10 @@ static void realview_init(QEMUMachineInitArgs *args, sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); if (is_mpcore) { - hwaddr periphbase; dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); - if (is_pb) { - periphbase = 0x1f000000; - } else { - periphbase = 0x10100000; - } sysbus_mmio_map(busdev, 0, periphbase); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 2decff1..392ca84 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -658,14 +658,15 @@ static void spitz_adc_temp_on(void *opaque, int line, int level) max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); } -static int corgi_ssp_init(SSISlave *dev) +static int corgi_ssp_init(SSISlave *d) { - CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); + DeviceState *dev = DEVICE(d); + CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d); - qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3); - s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0"); - s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1"); - s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2"); + qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3); + s->bus[0] = ssi_create_bus(dev, "ssi0"); + s->bus[1] = ssi_create_bus(dev, "ssi1"); + s->bus[2] = ssi_create_bus(dev, "ssi2"); return 0; } diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index ef1707a..67628af 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -32,6 +32,7 @@ #include "sysemu/blockdev.h" #include "hw/block/flash.h" #include "sysemu/device_tree.h" +#include "qemu/error-report.h" #include <libfdt.h> #define VEXPRESS_BOARD_ID 0x8e0 @@ -173,6 +174,64 @@ struct VEDBoardInfo { DBoardInitFn *init; }; +static void init_cpus(const char *cpu_model, const char *privdev, + hwaddr periphbase, qemu_irq *pic) +{ + ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); + DeviceState *dev; + SysBusDevice *busdev; + int n; + + if (!cpu_oc) { + fprintf(stderr, "Unable to find CPU definition\n"); + exit(1); + } + + /* Create the actual CPUs */ + for (n = 0; n < smp_cpus; n++) { + Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Error *err = NULL; + + object_property_set_int(cpuobj, periphbase, "reset-cbar", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + object_property_set_bool(cpuobj, true, "realized", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + } + + /* Create the private peripheral devices (including the GIC); + * this must happen after the CPUs are created because a15mpcore_priv + * wires itself up to the CPU's generic_timer gpio out lines. + */ + dev = qdev_create(NULL, privdev); + qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_init_nofail(dev); + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, periphbase); + + /* Interrupts [42:0] are from the motherboard; + * [47:43] are reserved; [63:48] are daughterboard + * peripherals. Note that some documentation numbers + * external interrupts starting from 32 (because there + * are internal interrupts 0..31). + */ + for (n = 0; n < 64; n++) { + pic[n] = qdev_get_gpio_in(dev, n); + } + + /* Connect the CPUs to the GIC */ + for (n = 0; n < smp_cpus; n++) { + DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); + + sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + } +} + static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, ram_addr_t ram_size, const char *cpu_model, @@ -181,25 +240,12 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *lowram = g_new(MemoryRegion, 1); - DeviceState *dev; - SysBusDevice *busdev; - int n; - qemu_irq cpu_irq[4]; ram_addr_t low_ram_size; if (!cpu_model) { cpu_model = "cortex-a9"; } - for (n = 0; n < smp_cpus; n++) { - ARMCPU *cpu = cpu_arm_init(cpu_model); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } - cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); - } - if (ram_size > 0x40000000) { /* 1GB is the maximum the address space permits */ fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); @@ -221,23 +267,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, memory_region_add_subregion(sysmem, 0x60000000, ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ - dev = qdev_create(NULL, "a9mpcore_priv"); - qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); - qdev_init_nofail(dev); - busdev = SYS_BUS_DEVICE(dev); - sysbus_mmio_map(busdev, 0, 0x1e000000); - for (n = 0; n < smp_cpus; n++) { - sysbus_connect_irq(busdev, n, cpu_irq[n]); - } - /* Interrupts [42:0] are from the motherboard; - * [47:43] are reserved; [63:48] are daughterboard - * peripherals. Note that some documentation numbers - * external interrupts starting from 32 (because the - * A9MP has internal interrupts 0..31). - */ - for (n = 0; n < 64; n++) { - pic[n] = qdev_get_gpio_in(dev, n); - } + init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ @@ -296,29 +326,14 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, const char *cpu_model, qemu_irq *pic) { - int n; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); - qemu_irq cpu_irq[4]; - DeviceState *dev; - SysBusDevice *busdev; if (!cpu_model) { cpu_model = "cortex-a15"; } - for (n = 0; n < smp_cpus; n++) { - ARMCPU *cpu; - - cpu = cpu_arm_init(cpu_model); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } - cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); - } - { /* We have to use a separate 64 bit variable here to avoid the gcc * "comparison is always false due to limited range of data type" @@ -337,23 +352,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, memory_region_add_subregion(sysmem, 0x80000000, ram); /* 0x2c000000 A15MPCore private memory region (GIC) */ - dev = qdev_create(NULL, "a15mpcore_priv"); - qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); - qdev_init_nofail(dev); - busdev = SYS_BUS_DEVICE(dev); - sysbus_mmio_map(busdev, 0, 0x2c000000); - for (n = 0; n < smp_cpus; n++) { - sysbus_connect_irq(busdev, n, cpu_irq[n]); - } - /* Interrupts [42:0] are from the motherboard; - * [47:43] are reserved; [63:48] are daughterboard - * peripherals. Note that some documentation numbers - * external interrupts starting from 32 (because there - * are internal interrupts 0..31). - */ - for (n = 0; n < 64; n++) { - pic[n] = qdev_get_gpio_in(dev, n); - } + init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); /* A15 daughterboard peripherals: */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 517f2fe..2bbc931 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -390,6 +390,12 @@ static void machvirt_init(QEMUMachineInitArgs *args) if (n > 0) { object_property_set_bool(cpuobj, true, "start-powered-off", NULL); } + + if (object_property_find(cpuobj, "reset-cbar", NULL)) { + object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, + "reset-cbar", &error_abort); + } + object_property_set_bool(cpuobj, true, "realized", NULL); } fdt_add_cpu_nodes(vbi); diff --git a/hw/audio/fmopl.c b/hw/audio/fmopl.c index f0a0234..290a224 100644 --- a/hw/audio/fmopl.c +++ b/hw/audio/fmopl.c @@ -223,13 +223,13 @@ static void *cur_chip = NULL; /* current chip point */ /* static OPLSAMPLE *bufL,*bufR; */ static OPL_CH *S_CH; static OPL_CH *E_CH; -OPL_SLOT *SLOT7_1,*SLOT7_2,*SLOT8_1,*SLOT8_2; +static OPL_SLOT *SLOT7_1, *SLOT7_2, *SLOT8_1, *SLOT8_2; static INT32 outd[1]; static INT32 ams; static INT32 vib; -INT32 *ams_table; -INT32 *vib_table; +static INT32 *ams_table; +static INT32 *vib_table; static INT32 amsIncr; static INT32 vibIncr; static INT32 feedback2; /* connect for SLOT 2 */ diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c index d1c7ad4..f558b45 100644 --- a/hw/block/dataplane/virtio-blk.c +++ b/hw/block/dataplane/virtio-blk.c @@ -23,6 +23,7 @@ #include "virtio-blk.h" #include "block/aio.h" #include "hw/virtio/virtio-bus.h" +#include "monitor/monitor.h" /* for object_add() */ enum { SEG_MAX = 126, /* maximum number of I/O segments */ @@ -44,8 +45,6 @@ struct VirtIOBlockDataPlane { bool started; bool starting; bool stopping; - QEMUBH *start_bh; - QemuThread thread; VirtIOBlkConf *blk; int fd; /* image file descriptor */ @@ -59,12 +58,14 @@ struct VirtIOBlockDataPlane { * (because you don't own the file descriptor or handle; you just * use it). */ + IOThread *iothread; + bool internal_iothread; AioContext *ctx; EventNotifier io_notifier; /* Linux AIO completion */ EventNotifier host_notifier; /* doorbell */ IOQueue ioqueue; /* Linux AIO queue (should really be per - dataplane thread) */ + IOThread) */ VirtIOBlockRequest requests[REQ_MAX]; /* pool of requests, managed by the queue */ @@ -342,26 +343,7 @@ static void handle_io(EventNotifier *e) } } -static void *data_plane_thread(void *opaque) -{ - VirtIOBlockDataPlane *s = opaque; - - while (!s->stopping || s->num_reqs > 0) { - aio_poll(s->ctx, true); - } - return NULL; -} - -static void start_data_plane_bh(void *opaque) -{ - VirtIOBlockDataPlane *s = opaque; - - qemu_bh_delete(s->start_bh); - s->start_bh = NULL; - qemu_thread_create(&s->thread, "data_plane", data_plane_thread, - s, QEMU_THREAD_JOINABLE); -} - +/* Context: QEMU global mutex held */ void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *blk, VirtIOBlockDataPlane **dataplane, Error **errp) @@ -408,12 +390,33 @@ void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *blk, s->fd = fd; s->blk = blk; + if (blk->iothread) { + s->internal_iothread = false; + s->iothread = blk->iothread; + } else { + /* Create per-device IOThread if none specified */ + Error *local_err = NULL; + + s->internal_iothread = true; + object_add(TYPE_IOTHREAD, vdev->name, NULL, NULL, &local_err); + if (error_is_set(&local_err)) { + error_propagate(errp, local_err); + g_free(s); + return; + } + s->iothread = iothread_find(vdev->name); + assert(s->iothread); + } + object_ref(OBJECT(s->iothread)); + s->ctx = iothread_get_aio_context(s->iothread); + /* Prevent block operations that conflict with data plane thread */ bdrv_set_in_use(blk->conf.bs, 1); *dataplane = s; } +/* Context: QEMU global mutex held */ void virtio_blk_data_plane_destroy(VirtIOBlockDataPlane *s) { if (!s) { @@ -422,9 +425,14 @@ void virtio_blk_data_plane_destroy(VirtIOBlockDataPlane *s) virtio_blk_data_plane_stop(s); bdrv_set_in_use(s->blk->conf.bs, 0); + object_unref(OBJECT(s->iothread)); + if (s->internal_iothread) { + object_unparent(OBJECT(s->iothread)); + } g_free(s); } +/* Context: QEMU global mutex held */ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s) { BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(s->vdev))); @@ -448,8 +456,6 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s) return; } - s->ctx = aio_context_new(); - /* Set up guest notifier (irq) */ if (k->set_guest_notifiers(qbus->parent, 1, true) != 0) { fprintf(stderr, "virtio-blk failed to set guest notifier, " @@ -464,7 +470,6 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s) exit(1); } s->host_notifier = *virtio_queue_get_host_notifier(vq); - aio_set_event_notifier(s->ctx, &s->host_notifier, handle_notify); /* Set up ioqueue */ ioq_init(&s->ioqueue, s->fd, REQ_MAX); @@ -472,7 +477,6 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s) ioq_put_iocb(&s->ioqueue, &s->requests[i].iocb); } s->io_notifier = *ioq_get_notifier(&s->ioqueue); - aio_set_event_notifier(s->ctx, &s->io_notifier, handle_io); s->starting = false; s->started = true; @@ -481,11 +485,14 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s) /* Kick right away to begin processing requests already in vring */ event_notifier_set(virtio_queue_get_host_notifier(vq)); - /* Spawn thread in BH so it inherits iothread cpusets */ - s->start_bh = qemu_bh_new(start_data_plane_bh, s); - qemu_bh_schedule(s->start_bh); + /* Get this show started by hooking up our callbacks */ + aio_context_acquire(s->ctx); + aio_set_event_notifier(s->ctx, &s->host_notifier, handle_notify); + aio_set_event_notifier(s->ctx, &s->io_notifier, handle_io); + aio_context_release(s->ctx); } +/* Context: QEMU global mutex held */ void virtio_blk_data_plane_stop(VirtIOBlockDataPlane *s) { BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(s->vdev))); @@ -496,27 +503,32 @@ void virtio_blk_data_plane_stop(VirtIOBlockDataPlane *s) s->stopping = true; trace_virtio_blk_data_plane_stop(s); - /* Stop thread or cancel pending thread creation BH */ - if (s->start_bh) { - qemu_bh_delete(s->start_bh); - s->start_bh = NULL; - } else { - aio_notify(s->ctx); - qemu_thread_join(&s->thread); + aio_context_acquire(s->ctx); + + /* Stop notifications for new requests from guest */ + aio_set_event_notifier(s->ctx, &s->host_notifier, NULL); + + /* Complete pending requests */ + while (s->num_reqs > 0) { + aio_poll(s->ctx, true); } + /* Stop ioq callbacks (there are no pending requests left) */ aio_set_event_notifier(s->ctx, &s->io_notifier, NULL); - ioq_cleanup(&s->ioqueue); - aio_set_event_notifier(s->ctx, &s->host_notifier, NULL); - k->set_host_notifier(qbus->parent, 0, false); + aio_context_release(s->ctx); - aio_context_unref(s->ctx); + /* Sync vring state back to virtqueue so that non-dataplane request + * processing can continue when we disable the host notifier below. + */ + vring_teardown(&s->vring, s->vdev, 0); + + ioq_cleanup(&s->ioqueue); + k->set_host_notifier(qbus->parent, 0, false); /* Clean up guest notifier (irq) */ k->set_guest_notifiers(qbus->parent, 1, false); - vring_teardown(&s->vring, s->vdev, 0); s->started = false; s->stopping = false; } diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 02a1544..e29a738 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -241,7 +241,8 @@ typedef enum { } CMDState; typedef struct Flash { - SSISlave ssidev; + SSISlave parent_obj; + uint32_t r; BlockDriverState *bdrv; @@ -545,7 +546,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) static int m25p80_cs(SSISlave *ss, bool select) { - Flash *s = FROM_SSI_SLAVE(Flash, ss); + Flash *s = M25P80(ss); if (select) { s->len = 0; @@ -561,7 +562,7 @@ static int m25p80_cs(SSISlave *ss, bool select) static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) { - Flash *s = FROM_SSI_SLAVE(Flash, ss); + Flash *s = M25P80(ss); uint32_t r = 0; switch (s->state) { @@ -610,7 +611,7 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) static int m25p80_init(SSISlave *ss) { DriveInfo *dinfo; - Flash *s = FROM_SSI_SLAVE(Flash, ss); + Flash *s = M25P80(ss); M25P80Class *mc = M25P80_GET_CLASS(s); s->pi = mc->pi; diff --git a/hw/char/pl011.c b/hw/char/pl011.c index a8ae6f4..644aad7 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -20,6 +20,7 @@ typedef struct PL011State { uint32_t readbuff; uint32_t flags; uint32_t lcr; + uint32_t rsr; uint32_t cr; uint32_t dmacr; uint32_t int_enabled; @@ -81,13 +82,14 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, } if (s->read_count == s->read_trigger - 1) s->int_level &= ~ PL011_INT_RX; + s->rsr = c >> 8; pl011_update(s); if (s->chr) { qemu_chr_accept_input(s->chr); } return c; - case 1: /* UARTCR */ - return 0; + case 1: /* UARTRSR */ + return s->rsr; case 6: /* UARTFR */ return s->flags; case 8: /* UARTILPR */ @@ -146,8 +148,8 @@ static void pl011_write(void *opaque, hwaddr offset, s->int_level |= PL011_INT_TX; pl011_update(s); break; - case 1: /* UARTCR */ - s->cr = value; + case 1: /* UARTRSR/UARTECR */ + s->rsr = 0; break; case 6: /* UARTFR */ /* Writes to Flag register are ignored. */ @@ -162,6 +164,11 @@ static void pl011_write(void *opaque, hwaddr offset, s->fbrd = value; break; case 11: /* UARTLCR_H */ + /* Reset the FIFO state on FIFO enable or disable */ + if ((s->lcr ^ value) & 0x10) { + s->read_count = 0; + s->read_pos = 0; + } s->lcr = value; pl011_set_read_trigger(s); break; @@ -214,7 +221,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->read_fifo[slot] = value; s->read_count++; s->flags &= ~PL011_FLAG_RXFE; - if (s->cr & 0x10 || s->read_count == 16) { + if (!(s->lcr & 0x10) || s->read_count == 16) { s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) { @@ -242,13 +249,14 @@ static const MemoryRegionOps pl011_ops = { static const VMStateDescription vmstate_pl011 = { .name = "pl011", - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, + .version_id = 2, + .minimum_version_id = 2, + .minimum_version_id_old = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(readbuff, PL011State), VMSTATE_UINT32(flags, PL011State), VMSTATE_UINT32(lcr, PL011State), + VMSTATE_UINT32(rsr, PL011State), VMSTATE_UINT32(cr, PL011State), VMSTATE_UINT32(dmacr, PL011State), VMSTATE_UINT32(int_enabled, PL011State), diff --git a/hw/char/sclpconsole-lm.c b/hw/char/sclpconsole-lm.c index 9339067..a2dc1c6 100644 --- a/hw/char/sclpconsole-lm.c +++ b/hw/char/sclpconsole-lm.c @@ -41,7 +41,6 @@ typedef struct SCLPConsoleLM { uint32_t write_errors; /* errors writing to char layer */ uint32_t length; /* length of byte stream in buffer */ uint8_t buf[SIZE_CONSOLE_BUFFER]; - qemu_irq irq_console_read; } SCLPConsoleLM; /* @@ -68,13 +67,15 @@ static int chr_can_read(void *opaque) return 0; } -static void receive_from_chr_layer(SCLPConsoleLM *scon, const uint8_t *buf, - int size) +static void chr_read(void *opaque, const uint8_t *buf, int size) { + SCLPConsoleLM *scon = opaque; + assert(size == 1); if (*buf == '\r' || *buf == '\n') { scon->event.event_pending = true; + sclp_service_interrupt(0); return; } scon->buf[scon->length] = *buf; @@ -84,20 +85,6 @@ static void receive_from_chr_layer(SCLPConsoleLM *scon, const uint8_t *buf, } } -/* - * Send data from a char device over to the guest - */ -static void chr_read(void *opaque, const uint8_t *buf, int size) -{ - SCLPConsoleLM *scon = opaque; - - receive_from_chr_layer(scon, buf, size); - if (scon->event.event_pending) { - /* trigger SCLP read operation */ - qemu_irq_raise(scon->irq_console_read); - } -} - /* functions to be called by event facility */ static bool can_handle_event(uint8_t type) @@ -298,11 +285,6 @@ static int write_event_data(SCLPEvent *event, EventBufferHeader *ebh) return SCLP_RC_NORMAL_COMPLETION; } -static void trigger_console_data(void *opaque, int n, int level) -{ - sclp_service_interrupt(0); -} - /* functions for live migration */ static const VMStateDescription vmstate_sclplmconsole = { @@ -338,7 +320,6 @@ static int console_init(SCLPEvent *event) if (scon->chr) { qemu_chr_add_handlers(scon->chr, chr_can_read, chr_read, NULL, scon); } - scon->irq_console_read = *qemu_allocate_irqs(trigger_console_data, NULL, 1); return 0; } diff --git a/hw/char/sclpconsole.c b/hw/char/sclpconsole.c index 16d77c5..ce40673 100644 --- a/hw/char/sclpconsole.c +++ b/hw/char/sclpconsole.c @@ -36,7 +36,6 @@ typedef struct SCLPConsole { uint32_t iov_bs; /* offset in buf for char layer read operation */ uint32_t iov_data_len; /* length of byte stream in buffer */ uint32_t iov_sclp_rest; /* length of byte stream not read via SCLP */ - qemu_irq irq_read_vt220; } SCLPConsole; /* character layer call-back functions */ @@ -49,11 +48,12 @@ static int chr_can_read(void *opaque) return SIZE_BUFFER_VT220 - scon->iov_data_len; } -/* Receive n bytes from character layer, save in iov buffer, - * and set event pending */ -static void receive_from_chr_layer(SCLPConsole *scon, const uint8_t *buf, - int size) +/* Send data from a char device over to the guest */ +static void chr_read(void *opaque, const uint8_t *buf, int size) { + SCLPConsole *scon = opaque; + + assert(scon); /* read data must fit into current buffer */ assert(size <= SIZE_BUFFER_VT220 - scon->iov_data_len); @@ -63,18 +63,7 @@ static void receive_from_chr_layer(SCLPConsole *scon, const uint8_t *buf, scon->iov_sclp_rest += size; scon->iov_bs += size; scon->event.event_pending = true; -} - -/* Send data from a char device over to the guest */ -static void chr_read(void *opaque, const uint8_t *buf, int size) -{ - SCLPConsole *scon = opaque; - - assert(scon); - - receive_from_chr_layer(scon, buf, size); - /* trigger SCLP read operation */ - qemu_irq_raise(scon->irq_read_vt220); + sclp_service_interrupt(0); } /* functions to be called by event facility */ @@ -192,11 +181,6 @@ static int write_event_data(SCLPEvent *event, EventBufferHeader *evt_buf_hdr) return rc; } -static void trigger_ascii_console_data(void *opaque, int n, int level) -{ - sclp_service_interrupt(0); -} - static const VMStateDescription vmstate_sclpconsole = { .name = "sclpconsole", .version_id = 0, @@ -232,8 +216,6 @@ static int console_init(SCLPEvent *event) qemu_chr_add_handlers(scon->chr, chr_can_read, chr_read, NULL, scon); } - scon->irq_read_vt220 = *qemu_allocate_irqs(trigger_ascii_console_data, - NULL, 1); return 0; } diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index 2e00ad2..6c8be0f 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -15,8 +15,13 @@ #include "trace.h" #include "hw/virtio/virtio-serial.h" +#define TYPE_VIRTIO_CONSOLE_SERIAL_PORT "virtserialport" +#define VIRTIO_CONSOLE(obj) \ + OBJECT_CHECK(VirtConsole, (obj), TYPE_VIRTIO_CONSOLE_SERIAL_PORT) + typedef struct VirtConsole { - VirtIOSerialPort port; + VirtIOSerialPort parent_obj; + CharDriverState *chr; guint watch; } VirtConsole; @@ -31,7 +36,7 @@ static gboolean chr_write_unblocked(GIOChannel *chan, GIOCondition cond, VirtConsole *vcon = opaque; vcon->watch = 0; - virtio_serial_throttle_port(&vcon->port, false); + virtio_serial_throttle_port(VIRTIO_SERIAL_PORT(vcon), false); return FALSE; } @@ -39,7 +44,7 @@ static gboolean chr_write_unblocked(GIOChannel *chan, GIOCondition cond, static ssize_t flush_buf(VirtIOSerialPort *port, const uint8_t *buf, ssize_t len) { - VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); + VirtConsole *vcon = VIRTIO_CONSOLE(port); ssize_t ret; if (!vcon->chr) { @@ -75,7 +80,7 @@ static ssize_t flush_buf(VirtIOSerialPort *port, /* Callback function that's called when the guest opens/closes the port */ static void set_guest_connected(VirtIOSerialPort *port, int guest_connected) { - VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); + VirtConsole *vcon = VIRTIO_CONSOLE(port); if (!vcon->chr) { return; @@ -88,45 +93,49 @@ static int chr_can_read(void *opaque) { VirtConsole *vcon = opaque; - return virtio_serial_guest_ready(&vcon->port); + return virtio_serial_guest_ready(VIRTIO_SERIAL_PORT(vcon)); } /* Send data from a char device over to the guest */ static void chr_read(void *opaque, const uint8_t *buf, int size) { VirtConsole *vcon = opaque; + VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(vcon); - trace_virtio_console_chr_read(vcon->port.id, size); - virtio_serial_write(&vcon->port, buf, size); + trace_virtio_console_chr_read(port->id, size); + virtio_serial_write(port, buf, size); } static void chr_event(void *opaque, int event) { VirtConsole *vcon = opaque; + VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(vcon); - trace_virtio_console_chr_event(vcon->port.id, event); + trace_virtio_console_chr_event(port->id, event); switch (event) { case CHR_EVENT_OPENED: - virtio_serial_open(&vcon->port); + virtio_serial_open(port); break; case CHR_EVENT_CLOSED: if (vcon->watch) { g_source_remove(vcon->watch); vcon->watch = 0; } - virtio_serial_close(&vcon->port); + virtio_serial_close(port); break; } } -static int virtconsole_initfn(VirtIOSerialPort *port) +static void virtconsole_realize(DeviceState *dev, Error **errp) { - VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); - VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_GET_CLASS(port); + VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(dev); + VirtConsole *vcon = VIRTIO_CONSOLE(dev); + VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_GET_CLASS(dev); if (port->id == 0 && !k->is_console) { - error_report("Port number 0 on virtio-serial devices reserved for virtconsole devices for backward compatibility."); - return -1; + error_setg(errp, "Port number 0 on virtio-serial devices reserved " + "for virtconsole devices for backward compatibility."); + return; } if (vcon->chr) { @@ -134,43 +143,27 @@ static int virtconsole_initfn(VirtIOSerialPort *port) qemu_chr_add_handlers(vcon->chr, chr_can_read, chr_read, chr_event, vcon); } - - return 0; } -static int virtconsole_exitfn(VirtIOSerialPort *port) +static void virtconsole_unrealize(DeviceState *dev, Error **errp) { - VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); + VirtConsole *vcon = VIRTIO_CONSOLE(dev); if (vcon->watch) { g_source_remove(vcon->watch); } - - return 0; } -static Property virtconsole_properties[] = { - DEFINE_PROP_CHR("chardev", VirtConsole, chr), - DEFINE_PROP_END_OF_LIST(), -}; - static void virtconsole_class_init(ObjectClass *klass, void *data) { - DeviceClass *dc = DEVICE_CLASS(klass); VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_CLASS(klass); k->is_console = true; - k->init = virtconsole_initfn; - k->exit = virtconsole_exitfn; - k->have_data = flush_buf; - k->set_guest_connected = set_guest_connected; - dc->props = virtconsole_properties; } static const TypeInfo virtconsole_info = { .name = "virtconsole", - .parent = TYPE_VIRTIO_SERIAL_PORT, - .instance_size = sizeof(VirtConsole), + .parent = TYPE_VIRTIO_CONSOLE_SERIAL_PORT, .class_init = virtconsole_class_init, }; @@ -184,15 +177,15 @@ static void virtserialport_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_CLASS(klass); - k->init = virtconsole_initfn; - k->exit = virtconsole_exitfn; + k->realize = virtconsole_realize; + k->unrealize = virtconsole_unrealize; k->have_data = flush_buf; k->set_guest_connected = set_guest_connected; dc->props = virtserialport_properties; } static const TypeInfo virtserialport_info = { - .name = "virtserialport", + .name = TYPE_VIRTIO_CONSOLE_SERIAL_PORT, .parent = TYPE_VIRTIO_SERIAL_PORT, .instance_size = sizeof(VirtConsole), .class_init = virtserialport_class_init, @@ -200,8 +193,8 @@ static const TypeInfo virtserialport_info = { static void virtconsole_register_types(void) { - type_register_static(&virtconsole_info); type_register_static(&virtserialport_info); + type_register_static(&virtconsole_info); } type_init(virtconsole_register_types) diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index 226e9f9..2b647b6 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -808,13 +808,14 @@ static void remove_port(VirtIOSerial *vser, uint32_t port_id) send_control_event(vser, port->id, VIRTIO_CONSOLE_PORT_REMOVE, 1); } -static int virtser_port_qdev_init(DeviceState *qdev) +static void virtser_port_device_realize(DeviceState *dev, Error **errp) { - VirtIOSerialPort *port = DO_UPCAST(VirtIOSerialPort, dev, qdev); + VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(dev); VirtIOSerialPortClass *vsc = VIRTIO_SERIAL_PORT_GET_CLASS(port); - VirtIOSerialBus *bus = DO_UPCAST(VirtIOSerialBus, qbus, qdev->parent_bus); - int ret, max_nr_ports; + VirtIOSerialBus *bus = VIRTIO_SERIAL_BUS(qdev_get_parent_bus(dev)); + int max_nr_ports; bool plugging_port0; + Error *err = NULL; port->vser = bus->vser; port->bh = qemu_bh_new(flush_queued_data_bh, port); @@ -829,9 +830,9 @@ static int virtser_port_qdev_init(DeviceState *qdev) plugging_port0 = vsc->is_console && !find_port_by_id(port->vser, 0); if (find_port_by_id(port->vser, port->id)) { - error_report("virtio-serial-bus: A port already exists at id %u", - port->id); - return -1; + error_setg(errp, "virtio-serial-bus: A port already exists at id %u", + port->id); + return; } if (port->id == VIRTIO_CONSOLE_BAD_ID) { @@ -840,22 +841,24 @@ static int virtser_port_qdev_init(DeviceState *qdev) } else { port->id = find_free_port_id(port->vser); if (port->id == VIRTIO_CONSOLE_BAD_ID) { - error_report("virtio-serial-bus: Maximum port limit for this device reached"); - return -1; + error_setg(errp, "virtio-serial-bus: Maximum port limit for " + "this device reached"); + return; } } } max_nr_ports = tswap32(port->vser->config.max_nr_ports); if (port->id >= max_nr_ports) { - error_report("virtio-serial-bus: Out-of-range port id specified, max. allowed: %u", - max_nr_ports - 1); - return -1; + error_setg(errp, "virtio-serial-bus: Out-of-range port id specified, " + "max. allowed: %u", max_nr_ports - 1); + return; } - ret = vsc->init(port); - if (ret) { - return ret; + vsc->realize(dev, &err); + if (err != NULL) { + error_propagate(errp, err); + return; } port->elem.out_num = 0; @@ -868,14 +871,12 @@ static int virtser_port_qdev_init(DeviceState *qdev) /* Send an update to the guest about this new port added */ virtio_notify_config(VIRTIO_DEVICE(port->vser)); - - return ret; } -static int virtser_port_qdev_exit(DeviceState *qdev) +static void virtser_port_device_unrealize(DeviceState *dev, Error **errp) { - VirtIOSerialPort *port = DO_UPCAST(VirtIOSerialPort, dev, qdev); - VirtIOSerialPortClass *vsc = VIRTIO_SERIAL_PORT_GET_CLASS(port); + VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(dev); + VirtIOSerialPortClass *vsc = VIRTIO_SERIAL_PORT_GET_CLASS(dev); VirtIOSerial *vser = port->vser; qemu_bh_delete(port->bh); @@ -883,10 +884,9 @@ static int virtser_port_qdev_exit(DeviceState *qdev) QTAILQ_REMOVE(&vser->ports, port, next); - if (vsc->exit) { - vsc->exit(port); + if (vsc->unrealize) { + vsc->unrealize(dev, errp); } - return 0; } static void virtio_serial_device_realize(DeviceState *dev, Error **errp) @@ -971,10 +971,11 @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp) static void virtio_serial_port_class_init(ObjectClass *klass, void *data) { DeviceClass *k = DEVICE_CLASS(klass); - k->init = virtser_port_qdev_init; + set_bit(DEVICE_CATEGORY_INPUT, k->categories); k->bus_type = TYPE_VIRTIO_SERIAL_BUS; - k->exit = virtser_port_qdev_exit; + k->realize = virtser_port_device_realize; + k->unrealize = virtser_port_device_unrealize; k->unplug = qdev_simple_unplug_cb; k->props = virtser_props; } diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 9e324be..5377d05 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -1,5 +1,6 @@ # core qdev-related obj files, also used by *-user: common-obj-y += qdev.o qdev-properties.o +common-obj-y += fw-path-provider.o # irq.o needed for qdev GPIO handling: common-obj-y += irq.o common-obj-y += hotplug.o @@ -8,7 +9,7 @@ common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o common-obj-$(CONFIG_XILINX_AXI) += stream.o common-obj-$(CONFIG_PTIMER) += ptimer.o common-obj-$(CONFIG_SOFTMMU) += sysbus.o +common-obj-$(CONFIG_SOFTMMU) += machine.o common-obj-$(CONFIG_SOFTMMU) += null-machine.o common-obj-$(CONFIG_SOFTMMU) += loader.o common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o - diff --git a/hw/core/fw-path-provider.c b/hw/core/fw-path-provider.c new file mode 100644 index 0000000..b117157 --- /dev/null +++ b/hw/core/fw-path-provider.c @@ -0,0 +1,51 @@ +/* + * Firmware patch provider class and helpers. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; under version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "hw/fw-path-provider.h" + +char *fw_path_provider_get_dev_path(FWPathProvider *p, BusState *bus, + DeviceState *dev) +{ + FWPathProviderClass *k = FW_PATH_PROVIDER_GET_CLASS(p); + + return k->get_dev_path(p, bus, dev); +} + +char *fw_path_provider_try_get_dev_path(Object *o, BusState *bus, + DeviceState *dev) +{ + FWPathProvider *p = (FWPathProvider *) + object_dynamic_cast(o, TYPE_FW_PATH_PROVIDER); + + if (p) { + return fw_path_provider_get_dev_path(p, bus, dev); + } + + return NULL; +} + +static const TypeInfo fw_path_provider_info = { + .name = TYPE_FW_PATH_PROVIDER, + .parent = TYPE_INTERFACE, + .class_size = sizeof(FWPathProviderClass), +}; + +static void fw_path_provider_register_types(void) +{ + type_register_static(&fw_path_provider_info); +} + +type_init(fw_path_provider_register_types) diff --git a/hw/core/machine.c b/hw/core/machine.c new file mode 100644 index 0000000..d3ffef7 --- /dev/null +++ b/hw/core/machine.c @@ -0,0 +1,28 @@ +/* + * QEMU Machine + * + * Copyright (C) 2014 Red Hat Inc + * + * Authors: + * Marcel Apfelbaum <marcel.a@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "hw/boards.h" + +static const TypeInfo machine_info = { + .name = TYPE_MACHINE, + .parent = TYPE_OBJECT, + .abstract = true, + .class_size = sizeof(MachineClass), + .instance_size = sizeof(MachineState), +}; + +static void machine_register_types(void) +{ + type_register_static(&machine_info); +} + +type_init(machine_register_types) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c index 5f5957e..de83561 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -18,17 +18,19 @@ #include "net/hub.h" #include "qapi/visitor.h" #include "sysemu/char.h" +#include "sysemu/iothread.h" static void get_pointer(Object *obj, Visitor *v, Property *prop, - const char *(*print)(void *ptr), + char *(*print)(void *ptr), const char *name, Error **errp) { DeviceState *dev = DEVICE(obj); void **ptr = qdev_get_prop_ptr(dev, prop); char *p; - p = (char *) (*ptr ? print(*ptr) : ""); + p = *ptr ? print(*ptr) : g_strdup(""); visit_type_str(v, &p, name, errp); + g_free(p); } static void set_pointer(Object *obj, Visitor *v, Property *prop, @@ -91,9 +93,9 @@ static void release_drive(Object *obj, const char *name, void *opaque) } } -static const char *print_drive(void *ptr) +static char *print_drive(void *ptr) { - return bdrv_get_device_name(ptr); + return g_strdup(bdrv_get_device_name(ptr)); } static void get_drive(Object *obj, Visitor *v, void *opaque, @@ -145,11 +147,12 @@ static void release_chr(Object *obj, const char *name, void *opaque) } -static const char *print_chr(void *ptr) +static char *print_chr(void *ptr) { CharDriverState *chr = ptr; + const char *val = chr->label ? chr->label : ""; - return chr->label ? chr->label : ""; + return g_strdup(val); } static void get_chr(Object *obj, Visitor *v, void *opaque, @@ -224,11 +227,12 @@ err: return ret; } -static const char *print_netdev(void *ptr) +static char *print_netdev(void *ptr) { NetClientState *netdev = ptr; + const char *val = netdev->name ? netdev->name : ""; - return netdev->name ? netdev->name : ""; + return g_strdup(val); } static void get_netdev(Object *obj, Visitor *v, void *opaque, @@ -382,6 +386,56 @@ void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd) nd->instantiated = 1; } +/* --- iothread --- */ + +static char *print_iothread(void *ptr) +{ + return iothread_get_id(ptr); +} + +static int parse_iothread(DeviceState *dev, const char *str, void **ptr) +{ + IOThread *iothread; + + iothread = iothread_find(str); + if (!iothread) { + return -ENOENT; + } + object_ref(OBJECT(iothread)); + *ptr = iothread; + return 0; +} + +static void get_iothread(Object *obj, struct Visitor *v, void *opaque, + const char *name, Error **errp) +{ + get_pointer(obj, v, opaque, print_iothread, name, errp); +} + +static void set_iothread(Object *obj, struct Visitor *v, void *opaque, + const char *name, Error **errp) +{ + set_pointer(obj, v, opaque, parse_iothread, name, errp); +} + +static void release_iothread(Object *obj, const char *name, void *opaque) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + IOThread **ptr = qdev_get_prop_ptr(dev, prop); + + if (*ptr) { + object_unref(OBJECT(*ptr)); + } +} + +PropertyInfo qdev_prop_iothread = { + .name = "iothread", + .get = get_iothread, + .set = set_iothread, + .release = release_iothread, +}; + static int qdev_add_one_global(QemuOpts *opts, void *opaque) { GlobalProperty *g; diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 77d0c66..c67acf5 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -21,6 +21,18 @@ void qdev_prop_set_after_realize(DeviceState *dev, const char *name, } } +void qdev_prop_allow_set_link_before_realize(Object *obj, const char *name, + Object *val, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + + if (dev->realized) { + error_setg(errp, "Attempt to set link property '%s' on device '%s' " + "(type '%s') after it was realized", + name, dev->id, object_get_typename(obj)); + } +} + void *qdev_get_prop_ptr(DeviceState *dev, Property *prop) { void *ptr = dev; diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 380976a..60f9df1 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -26,6 +26,7 @@ this API directly. */ #include "hw/qdev.h" +#include "hw/fw-path-provider.h" #include "sysemu/sysemu.h" #include "qapi/error.h" #include "qapi/qmp/qerror.h" @@ -98,6 +99,8 @@ static void bus_add_child(BusState *bus, DeviceState *child) object_property_add_link(OBJECT(bus), name, object_get_typename(OBJECT(child)), (Object **)&kid->child, + NULL, /* read-only property */ + 0, /* return ownership on prop deletion */ NULL); } @@ -501,6 +504,45 @@ static void bus_unparent(Object *obj) } } +static bool bus_get_realized(Object *obj, Error **err) +{ + BusState *bus = BUS(obj); + + return bus->realized; +} + +static void bus_set_realized(Object *obj, bool value, Error **err) +{ + BusState *bus = BUS(obj); + BusClass *bc = BUS_GET_CLASS(bus); + Error *local_err = NULL; + + if (value && !bus->realized) { + if (bc->realize) { + bc->realize(bus, &local_err); + + if (local_err != NULL) { + goto error; + } + + } + } else if (!value && bus->realized) { + if (bc->unrealize) { + bc->unrealize(bus, &local_err); + + if (local_err != NULL) { + goto error; + } + } + } + + bus->realized = value; + return; + +error: + error_propagate(err, local_err); +} + void qbus_create_inplace(void *bus, size_t size, const char *typename, DeviceState *parent, const char *name) { @@ -529,6 +571,18 @@ static char *bus_get_fw_dev_path(BusState *bus, DeviceState *dev) return NULL; } +static char *qdev_get_fw_dev_path_from_handler(BusState *bus, DeviceState *dev) +{ + Object *obj = OBJECT(dev); + char *d = NULL; + + while (!d && obj->parent) { + obj = obj->parent; + d = fw_path_provider_try_get_dev_path(obj, bus, dev); + } + return d; +} + static int qdev_get_fw_dev_path_helper(DeviceState *dev, char *p, int size) { int l = 0; @@ -536,7 +590,10 @@ static int qdev_get_fw_dev_path_helper(DeviceState *dev, char *p, int size) if (dev && dev->parent_bus) { char *d; l = qdev_get_fw_dev_path_helper(dev->parent_bus->parent, p, size); - d = bus_get_fw_dev_path(dev->parent_bus, dev); + d = qdev_get_fw_dev_path_from_handler(dev->parent_bus, dev); + if (!d) { + d = bus_get_fw_dev_path(dev->parent_bus, dev); + } if (d) { l += snprintf(p + l, size - l, "%s", d); g_free(d); @@ -677,6 +734,7 @@ static void device_set_realized(Object *obj, bool value, Error **err) { DeviceState *dev = DEVICE(obj); DeviceClass *dc = DEVICE_GET_CLASS(dev); + BusState *bus; Error *local_err = NULL; if (dev->hotplugged && !dc->hotpluggable) { @@ -710,14 +768,30 @@ static void device_set_realized(Object *obj, bool value, Error **err) dev->instance_id_alias, dev->alias_required_for_version); } + if (local_err == NULL) { + QLIST_FOREACH(bus, &dev->child_bus, sibling) { + object_property_set_bool(OBJECT(bus), true, "realized", + &local_err); + if (local_err != NULL) { + break; + } + } + } if (dev->hotplugged && local_err == NULL) { device_reset(dev); } } else if (!value && dev->realized) { - if (qdev_get_vmsd(dev)) { + QLIST_FOREACH(bus, &dev->child_bus, sibling) { + object_property_set_bool(OBJECT(bus), false, "realized", + &local_err); + if (local_err != NULL) { + break; + } + } + if (qdev_get_vmsd(dev) && local_err == NULL) { vmstate_unregister(dev, qdev_get_vmsd(dev), dev); } - if (dc->unrealize) { + if (dc->unrealize && local_err == NULL) { dc->unrealize(dev, &local_err); } } @@ -735,7 +809,8 @@ static bool device_get_hotpluggable(Object *obj, Error **err) DeviceClass *dc = DEVICE_GET_CLASS(obj); DeviceState *dev = DEVICE(obj); - return dc->hotpluggable && dev->parent_bus->allow_hotplug; + return dc->hotpluggable && (dev->parent_bus == NULL || + dev->parent_bus->allow_hotplug); } static void device_initfn(Object *obj) @@ -767,7 +842,8 @@ static void device_initfn(Object *obj) } while (class != object_class_by_name(TYPE_DEVICE)); object_property_add_link(OBJECT(dev), "parent_bus", TYPE_BUS, - (Object **)&dev->parent_bus, &error_abort); + (Object **)&dev->parent_bus, NULL, 0, + &error_abort); } static void device_post_init(Object *obj) @@ -792,14 +868,6 @@ static void device_class_base_init(ObjectClass *class, void *data) * so do not propagate them to the subclasses. */ klass->props = NULL; - - /* by default all devices were considered as hotpluggable, - * so with intent to check it in generic qdev_unplug() / - * device_set_realized() functions make every device - * hotpluggable. Devices that shouldn't be hotpluggable, - * should override it in their class_init() - */ - klass->hotpluggable = true; } static void device_unparent(Object *obj) @@ -809,13 +877,13 @@ static void device_unparent(Object *obj) QObject *event_data; bool have_realized = dev->realized; + if (dev->realized) { + object_property_set_bool(obj, false, "realized", NULL); + } while (dev->num_child_bus) { bus = QLIST_FIRST(&dev->child_bus); object_unparent(OBJECT(bus)); } - if (dev->realized) { - object_property_set_bool(obj, false, "realized", NULL); - } if (dev->parent_bus) { bus_remove_child(dev->parent_bus, dev); object_unref(OBJECT(dev->parent_bus)); @@ -845,6 +913,14 @@ static void device_class_init(ObjectClass *class, void *data) class->unparent = device_unparent; dc->realize = device_realize; dc->unrealize = device_unrealize; + + /* by default all devices were considered as hotpluggable, + * so with intent to check it in generic qdev_unplug() / + * device_set_realized() functions make every device + * hotpluggable. Devices that shouldn't be hotpluggable, + * should override it in their class_init() + */ + dc->hotpluggable = true; } void device_reset(DeviceState *dev) @@ -887,7 +963,12 @@ static void qbus_initfn(Object *obj) QTAILQ_INIT(&bus->children); object_property_add_link(obj, QDEV_HOTPLUG_HANDLER_PROPERTY, TYPE_HOTPLUG_HANDLER, - (Object **)&bus->hotplug_handler, NULL); + (Object **)&bus->hotplug_handler, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + NULL); + object_property_add_bool(obj, "realized", + bus_get_realized, bus_set_realized, NULL); } static char *default_bus_get_fw_dev_path(DeviceState *dev) diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c index 5da3dc5..85252a2 100644 --- a/hw/display/ads7846.c +++ b/hw/display/ads7846.c @@ -133,11 +133,12 @@ static const VMStateDescription vmstate_ads7846 = { } }; -static int ads7846_init(SSISlave *dev) +static int ads7846_init(SSISlave *d) { - ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev); + DeviceState *dev = DEVICE(d); + ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d); - qdev_init_gpio_out(&dev->qdev, &s->interrupt, 1); + qdev_init_gpio_out(dev, &s->interrupt, 1); s->input[0] = ADS_TEMP0; /* TEMP0 */ s->input[2] = ADS_VBAT; /* VBAT */ diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index 46c3b40..971152e 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -336,18 +336,19 @@ static const GraphicHwOps ssd0323_ops = { .gfx_update = ssd0323_update_display, }; -static int ssd0323_init(SSISlave *dev) +static int ssd0323_init(SSISlave *d) { - ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev); + DeviceState *dev = DEVICE(d); + ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d); s->col_end = 63; s->row_end = 79; - s->con = graphic_console_init(DEVICE(dev), 0, &ssd0323_ops, s); + s->con = graphic_console_init(dev, 0, &ssd0323_ops, s); qemu_console_resize(s->con, 128 * MAGNIFY, 64 * MAGNIFY); - qdev_init_gpio_in(&dev->qdev, ssd0323_cd, 1); + qdev_init_gpio_in(dev, ssd0323_cd, 1); - register_savevm(&dev->qdev, "ssd0323_oled", -1, 1, + register_savevm(dev, "ssd0323_oled", -1, 1, ssd0323_save, ssd0323_load, s); return 0; } diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index bd2c108..6ae3348 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -25,6 +25,7 @@ #include "hw/loader.h" #include "trace.h" #include "ui/console.h" +#include "ui/vnc.h" #include "hw/pci/pci.h" #undef VERBOSE @@ -218,7 +219,7 @@ enum { /* These values can probably be changed arbitrarily. */ #define SVGA_SCRATCH_SIZE 0x8000 -#define SVGA_MAX_WIDTH 2360 +#define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) #define SVGA_MAX_HEIGHT 1770 #ifdef VERBOSE diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 19f07b3..14b887b 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -537,9 +537,15 @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp) Error *local_errp = NULL; object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA, - (Object **)&ds->dma, &local_errp); + (Object **)&ds->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &local_errp); object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA, - (Object **)&cs->dma, &local_errp); + (Object **)&cs->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &local_errp); if (local_errp) { goto xilinx_axidma_realize_fail; } @@ -571,10 +577,16 @@ static void xilinx_axidma_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, - (Object **)&s->tx_data_dev, &error_abort); + (Object **)&s->tx_data_dev, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &error_abort); object_property_add_link(obj, "axistream-control-connected", TYPE_STREAM_SLAVE, - (Object **)&s->tx_control_dev, &error_abort); + (Object **)&s->tx_control_dev, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &error_abort); object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), TYPE_XILINX_AXI_DMA_DATA_STREAM); diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 72025d0..a1c3d1c 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -406,7 +406,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) } if (!kvm_enabled()) { - cpu_restore_state(env, env->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } @@ -448,8 +448,8 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) if (!kvm_enabled()) { cs->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); - cpu_resume_from_signal(env, NULL); + tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); + cpu_resume_from_signal(cs, NULL); } } diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5e1d2d3..7930a26 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -267,6 +267,7 @@ static void pc_compat_1_7(QEMUMachineInitArgs *args) smbios_type1_defaults = false; gigabyte_align = false; option_rom_has_mr = true; + x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); } static void pc_compat_1_6(QEMUMachineInitArgs *args) @@ -299,7 +300,7 @@ static void pc_compat_1_3(QEMUMachineInitArgs *args) static void pc_compat_1_2(QEMUMachineInitArgs *args) { pc_compat_1_3(args); - disable_kvm_pv_eoi(); + x86_cpu_compat_disable_kvm_features(FEAT_KVM, KVM_FEATURE_PV_EOI); } static void pc_init_pci_1_7(QEMUMachineInitArgs *args) @@ -345,7 +346,7 @@ static void pc_init_pci_no_kvmclock(QEMUMachineInitArgs *args) has_pci_info = false; has_acpi_build = false; smbios_type1_defaults = false; - disable_kvm_pv_eoi(); + x86_cpu_compat_disable_kvm_features(FEAT_KVM, KVM_FEATURE_PV_EOI); enable_compat_apic_id_mode(); pc_init1(args, 1, 0); } @@ -358,7 +359,7 @@ static void pc_init_isa(QEMUMachineInitArgs *args) if (!args->cpu_model) { args->cpu_model = "486"; } - disable_kvm_pv_eoi(); + x86_cpu_compat_disable_kvm_features(FEAT_KVM, KVM_FEATURE_PV_EOI); enable_compat_apic_id_mode(); pc_init1(args, 0, 1); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 4b0456a..c844dc2 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -245,6 +245,7 @@ static void pc_compat_1_7(QEMUMachineInitArgs *args) smbios_type1_defaults = false; gigabyte_align = false; option_rom_has_mr = true; + x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); } static void pc_compat_1_6(QEMUMachineInitArgs *args) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index fbea9e8..bfe633f 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -118,11 +118,12 @@ static uint32_t ahci_port_read(AHCIState *s, int port, int offset) static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) { AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); - PCIDevice *pci_dev = PCI_DEVICE(d); + PCIDevice *pci_dev = + (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); DPRINTF(0, "raise irq\n"); - if (msi_enabled(pci_dev)) { + if (pci_dev && msi_enabled(pci_dev)) { msi_notify(pci_dev, 0); } else { qemu_irq_raise(s->irq); @@ -132,10 +133,12 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) { AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); + PCIDevice *pci_dev = + (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); DPRINTF(0, "lower irq\n"); - if (!msi_enabled(PCI_DEVICE(d))) { + if (!pci_dev || !msi_enabled(pci_dev)) { qemu_irq_lower(s->irq); } } @@ -1311,7 +1314,7 @@ static const VMStateDescription vmstate_sysbus_ahci = { .name = "sysbus-ahci", .unmigratable = 1, /* Still buggy under I/O load */ .fields = (VMStateField []) { - VMSTATE_AHCI(ahci, AHCIPCIState), + VMSTATE_AHCI(ahci, SysbusAHCIState), VMSTATE_END_OF_LIST() }, }; @@ -1328,7 +1331,7 @@ static void sysbus_ahci_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); SysbusAHCIState *s = SYSBUS_AHCI(dev); - ahci_init(&s->ahci, dev, NULL, s->num_ports); + ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports); sysbus_init_mmio(sbd, &s->ahci.mem); sysbus_init_irq(sbd, &s->ahci.irq); diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 100b6bf..719d227 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -148,7 +148,7 @@ typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu, uint32_t *field, bool to_kernel); /* synthetic translate function used for clear/set registers to completely - * clear a setting using a clear-register before setting the remaing bits + * clear a setting using a clear-register before setting the remaining bits * using a set-register */ static void translate_clear(GICState *s, int irq, int cpu, uint32_t *field, bool to_kernel) diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index a5bbc24..c93dae0 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -269,7 +269,16 @@ static void ics_kvm_set_irq(void *opaque, int srcno, int val) static void ics_kvm_reset(DeviceState *dev) { - ics_set_kvm_state(ICS(dev), 1); + ICSState *ics = ICS(dev); + int i; + + memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); + for (i = 0; i < ics->nr_irqs; i++) { + ics->irqs[i].priority = 0xff; + ics->irqs[i].saved_priority = 0xff; + } + + ics_set_kvm_state(ics, 1); } static void ics_kvm_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index d477ecd..bba87c2 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -13,7 +13,8 @@ #include "hw/ssi.h" typedef struct { - SSISlave ssidev; + SSISlave parent_obj; + qemu_irq interrupt; uint8_t tb1, rb2, rb3; int cycle; @@ -22,6 +23,14 @@ typedef struct { int inputs, com; } MAX111xState; +#define TYPE_MAX_111X "max111x" + +#define MAX_111X(obj) \ + OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X) + +#define TYPE_MAX_1110 "max1110" +#define TYPE_MAX_1111 "max1111" + /* Control-byte bitfields */ #define CB_PD0 (1 << 0) #define CB_PD1 (1 << 1) @@ -92,7 +101,7 @@ static void max111x_write(MAX111xState *s, uint32_t value) static uint32_t max111x_transfer(SSISlave *dev, uint32_t value) { - MAX111xState *s = FROM_SSI_SLAVE(MAX111xState, dev); + MAX111xState *s = MAX_111X(dev); max111x_write(s, value); return max111x_read(s); } @@ -103,7 +112,7 @@ static const VMStateDescription vmstate_max111x = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_SSI_SLAVE(ssidev, MAX111xState), + VMSTATE_SSI_SLAVE(parent_obj, MAX111xState), VMSTATE_UINT8(tb1, MAX111xState), VMSTATE_UINT8(rb2, MAX111xState), VMSTATE_UINT8(rb3, MAX111xState), @@ -115,11 +124,12 @@ static const VMStateDescription vmstate_max111x = { } }; -static int max111x_init(SSISlave *dev, int inputs) +static int max111x_init(SSISlave *d, int inputs) { - MAX111xState *s = FROM_SSI_SLAVE(MAX111xState, dev); + DeviceState *dev = DEVICE(d); + MAX111xState *s = MAX_111X(dev); - qdev_init_gpio_out(&dev->qdev, &s->interrupt, 1); + qdev_init_gpio_out(dev, &s->interrupt, 1); s->inputs = inputs; /* TODO: add a user interface for setting these */ @@ -133,7 +143,7 @@ static int max111x_init(SSISlave *dev, int inputs) s->input[7] = 0x80; s->com = 0; - vmstate_register(&dev->qdev, -1, &vmstate_max111x, s); + vmstate_register(dev, -1, &vmstate_max111x, s); return 0; } @@ -149,23 +159,36 @@ static int max1111_init(SSISlave *dev) void max111x_set_input(DeviceState *dev, int line, uint8_t value) { - MAX111xState *s = FROM_SSI_SLAVE(MAX111xState, SSI_SLAVE_FROM_QDEV(dev)); + MAX111xState *s = MAX_111X(dev); assert(line >= 0 && line < s->inputs); s->input[line] = value; } -static void max1110_class_init(ObjectClass *klass, void *data) +static void max111x_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); - k->init = max1110_init; k->transfer = max111x_transfer; } -static const TypeInfo max1110_info = { - .name = "max1110", +static const TypeInfo max111x_info = { + .name = TYPE_MAX_111X, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(MAX111xState), + .class_init = max111x_class_init, + .abstract = true, +}; + +static void max1110_class_init(ObjectClass *klass, void *data) +{ + SSISlaveClass *k = SSI_SLAVE_CLASS(klass); + + k->init = max1110_init; +} + +static const TypeInfo max1110_info = { + .name = TYPE_MAX_1110, + .parent = TYPE_MAX_111X, .class_init = max1110_class_init, }; @@ -174,18 +197,17 @@ static void max1111_class_init(ObjectClass *klass, void *data) SSISlaveClass *k = SSI_SLAVE_CLASS(klass); k->init = max1111_init; - k->transfer = max111x_transfer; } static const TypeInfo max1111_info = { - .name = "max1111", - .parent = TYPE_SSI_SLAVE, - .instance_size = sizeof(MAX111xState), + .name = TYPE_MAX_1111, + .parent = TYPE_MAX_111X, .class_init = max1111_class_init, }; static void max111x_register_types(void) { + type_register_static(&max111x_info); type_register_static(&max1110_info); type_register_static(&max1111_info); } diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c index 7760272..e36cfbe 100644 --- a/hw/net/fsl_etsec/rings.c +++ b/hw/net/fsl_etsec/rings.c @@ -195,8 +195,8 @@ static void process_tx_fcb(eTSEC *etsec) /* if packet is IP4 and IP checksum is requested */ if (flags & FCB_TX_IP && flags & FCB_TX_CIP) { - /* do IP4 checksum (TODO This funtion does TCP/UDP checksum but not sure - * if it also does IP4 checksum. */ + /* do IP4 checksum (TODO This function does TCP/UDP checksum + * but not sure if it also does IP4 checksum.) */ net_checksum_calculate(etsec->tx_buffer + 8, etsec->tx_buffer_len - 8); } @@ -592,7 +592,7 @@ void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr) /* TODO: Broadcast and Multicast */ - if (bd.flags | BD_INTERRUPT) { + if (bd.flags & BD_INTERRUPT) { /* Set RXFx */ etsec->regs[RSTAT].value |= 1 << (7 - ring_nbr); @@ -601,7 +601,7 @@ void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr) } } else { - if (bd.flags | BD_INTERRUPT) { + if (bd.flags & BD_INTERRUPT) { /* Set IEVENT */ ievent_set(etsec, IEVENT_RXB); } diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c index f6fbcb5..c433337 100644 --- a/hw/net/spapr_llan.c +++ b/hw/net/spapr_llan.c @@ -29,6 +29,7 @@ #include "hw/qdev.h" #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" +#include "sysemu/sysemu.h" #include <libfdt.h> @@ -213,6 +214,8 @@ static int spapr_vlan_init(VIOsPAPRDevice *sdev) object_get_typename(OBJECT(sdev)), sdev->qdev.id, dev); qemu_format_nic_info_str(qemu_get_queue(dev->nic), dev->nicconf.macaddr.a); + add_boot_device_path(dev->nicconf.bootindex, DEVICE(dev), ""); + return 0; } diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 0bd5eda..839d97c 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -945,9 +945,15 @@ static void xilinx_enet_realize(DeviceState *dev, Error **errp) Error *local_errp = NULL; object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", - (Object **) &ds->enet, &local_errp); + (Object **) &ds->enet, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &local_errp); object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", - (Object **) &cs->enet, &local_errp); + (Object **) &cs->enet, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &local_errp); if (local_errp) { goto xilinx_enet_realize_fail; } @@ -982,10 +988,16 @@ static void xilinx_enet_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, - (Object **) &s->tx_data_dev, &error_abort); + (Object **) &s->tx_data_dev, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &error_abort); object_property_add_link(obj, "axistream-control-connected", TYPE_STREAM_SLAVE, - (Object **) &s->tx_control_dev, &error_abort); + (Object **) &s->tx_control_dev, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &error_abort); object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), TYPE_XILINX_AXI_ENET_DATA_STREAM); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index cb36dc2..282341a 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -504,7 +504,7 @@ static void fw_cfg_machine_ready(struct Notifier *n, void *data) { size_t len; FWCfgState *s = container_of(n, FWCfgState, machine_ready); - char *bootindex = get_boot_devices_list(&len); + char *bootindex = get_boot_devices_list(&len, false); fw_cfg_add_file(s, "bootorder", (uint8_t*)bootindex, len); } diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 0c948e2..d3e746c 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -28,7 +28,9 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" +#include "hw/loader.h" #include "exec/address-spaces.h" +#include "elf.h" #define TYPE_RAVEN_PCI_DEVICE "raven" #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" @@ -38,6 +40,10 @@ typedef struct RavenPCIState { PCIDevice dev; + + uint32_t elf_machine; + char *bios_name; + MemoryRegion bios; } RavenPCIState; #define RAVEN_PCI_HOST_BRIDGE(obj) \ @@ -46,13 +52,25 @@ typedef struct RavenPCIState { typedef struct PRePPCIState { PCIHostState parent_obj; - MemoryRegion intack; qemu_irq irq[PCI_NUM_PINS]; PCIBus pci_bus; + AddressSpace pci_io_as; + MemoryRegion pci_io; + MemoryRegion pci_io_non_contiguous; + MemoryRegion pci_memory; + MemoryRegion pci_intack; + MemoryRegion bm; + MemoryRegion bm_ram_alias; + MemoryRegion bm_pci_memory_alias; + AddressSpace bm_as; RavenPCIState pci_dev; + + int contiguous_map; } PREPPCIState; -static inline uint32_t PPC_PCIIO_config(hwaddr addr) +#define BIOS_SIZE (1024 * 1024) + +static inline uint32_t raven_pci_io_config(hwaddr addr) { int i; @@ -64,53 +82,133 @@ static inline uint32_t PPC_PCIIO_config(hwaddr addr) return (addr & 0x7ff) | (i << 11); } -static void ppc_pci_io_write(void *opaque, hwaddr addr, - uint64_t val, unsigned int size) +static void raven_pci_io_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) { PREPPCIState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size); + pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); } -static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr, - unsigned int size) +static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, + unsigned int size) { PREPPCIState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size); + return pci_data_read(phb->bus, raven_pci_io_config(addr), size); } -static const MemoryRegionOps PPC_PCIIO_ops = { - .read = ppc_pci_io_read, - .write = ppc_pci_io_write, +static const MemoryRegionOps raven_pci_io_ops = { + .read = raven_pci_io_read, + .write = raven_pci_io_write, .endianness = DEVICE_LITTLE_ENDIAN, }; -static uint64_t ppc_intack_read(void *opaque, hwaddr addr, - unsigned int size) +static uint64_t raven_intack_read(void *opaque, hwaddr addr, + unsigned int size) { return pic_read_irq(isa_pic); } -static const MemoryRegionOps PPC_intack_ops = { - .read = ppc_intack_read, +static const MemoryRegionOps raven_intack_ops = { + .read = raven_intack_read, .valid = { .max_access_size = 1, }, }; -static int prep_map_irq(PCIDevice *pci_dev, int irq_num) +static inline hwaddr raven_io_address(PREPPCIState *s, + hwaddr addr) +{ + if (s->contiguous_map == 0) { + /* 64 KB contiguous space for IOs */ + addr &= 0xFFFF; + } else { + /* 8 MB non-contiguous space for IOs */ + addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); + } + + /* FIXME: handle endianness switch */ + + return addr; +} + +static uint64_t raven_io_read(void *opaque, hwaddr addr, + unsigned int size) +{ + PREPPCIState *s = opaque; + uint8_t buf[4]; + + addr = raven_io_address(s, addr); + address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size); + + if (size == 1) { + return buf[0]; + } else if (size == 2) { + return lduw_p(buf); + } else if (size == 4) { + return ldl_p(buf); + } else { + g_assert_not_reached(); + } +} + +static void raven_io_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + PREPPCIState *s = opaque; + uint8_t buf[4]; + + addr = raven_io_address(s, addr); + + if (size == 1) { + buf[0] = val; + } else if (size == 2) { + stw_p(buf, val); + } else if (size == 4) { + stl_p(buf, val); + } else { + g_assert_not_reached(); + } + + address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size); +} + +static const MemoryRegionOps raven_io_ops = { + .read = raven_io_read, + .write = raven_io_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.max_access_size = 4, + .valid.unaligned = true, +}; + +static int raven_map_irq(PCIDevice *pci_dev, int irq_num) { return (irq_num + (pci_dev->devfn >> 3)) & 1; } -static void prep_set_irq(void *opaque, int irq_num, int level) +static void raven_set_irq(void *opaque, int irq_num, int level) { qemu_irq *pic = opaque; qemu_set_irq(pic[irq_num] , level); } +static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, + int devfn) +{ + PREPPCIState *s = opaque; + + return &s->bm_as; +} + +static void raven_change_gpio(void *opaque, int n, int level) +{ + PREPPCIState *s = opaque; + + s->contiguous_map = level; +} + static void raven_pcihost_realizefn(DeviceState *d, Error **errp) { SysBusDevice *dev = SYS_BUS_DEVICE(d); @@ -119,29 +217,30 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) MemoryRegion *address_space_mem = get_system_memory(); int i; - isa_mem_base = 0xc0000000; - for (i = 0; i < PCI_NUM_PINS; i++) { sysbus_init_irq(dev, &s->irq[i]); } - pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS); + qdev_init_gpio_in(d, raven_change_gpio, 1); + + pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq, + PCI_NUM_PINS); - memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s, - "pci-conf-idx", 1); - sysbus_add_io(dev, 0xcf8, &h->conf_mem); - sysbus_init_ioports(&h->busdev, 0xcf8, 1); + memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, + "pci-conf-idx", 4); + memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); - memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s, - "pci-conf-data", 1); - sysbus_add_io(dev, 0xcfc, &h->data_mem); - sysbus_init_ioports(&h->busdev, 0xcfc, 1); + memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, + "pci-conf-data", 4); + memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); - memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000); + memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, + "pciio", 0x00400000); memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); - memory_region_init_io(&s->intack, OBJECT(s), &PPC_intack_ops, s, "pci-intack", 1); - memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack); + memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, + "pci-intack", 1); + memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); /* TODO Remove once realize propagates to child devices. */ object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); @@ -152,11 +251,36 @@ static void raven_pcihost_initfn(Object *obj) PCIHostState *h = PCI_HOST_BRIDGE(obj); PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *address_space_io = get_system_io(); DeviceState *pci_dev; + memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); + memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, + "pci-io-non-contiguous", 0x00800000); + /* Open Hack'Ware hack: real size should be only 0x3f000000 bytes */ + memory_region_init(&s->pci_memory, obj, "pci-memory", + 0x3f000000 + 0xc0000000ULL); + address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); + + /* CPU address space */ + memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io); + memory_region_add_subregion_overlap(address_space_mem, 0x80000000, + &s->pci_io_non_contiguous, 1); + memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, - address_space_mem, address_space_io, 0, TYPE_PCI_BUS); + &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); + + /* Bus master address space */ + memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX); + memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory", + &s->pci_memory, 0, + memory_region_size(&s->pci_memory)); + memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system", + get_system_memory(), 0, 0x80000000); + memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); + memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); + address_space_init(&s->bm_as, &s->bm, "raven-bm"); + pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s); + h->bus = &s->pci_bus; object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); @@ -169,10 +293,45 @@ static void raven_pcihost_initfn(Object *obj) static int raven_init(PCIDevice *d) { + RavenPCIState *s = RAVEN_PCI_DEVICE(d); + char *filename; + int bios_size = -1; + d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer d->config[0x34] = 0x00; // capabilities_pointer + memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE); + memory_region_set_readonly(&s->bios, true); + memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), + &s->bios); + vmstate_register_ram_global(&s->bios); + if (s->bios_name) { + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); + if (filename) { + if (s->elf_machine != EM_NONE) { + bios_size = load_elf(filename, NULL, NULL, NULL, + NULL, NULL, 1, s->elf_machine, 0); + } + if (bios_size < 0) { + bios_size = get_image_size(filename); + if (bios_size > 0 && bios_size <= BIOS_SIZE) { + hwaddr bios_addr; + bios_size = (bios_size + 0xfff) & ~0xfff; + bios_addr = (uint32_t)(-BIOS_SIZE); + bios_size = load_image_targphys(filename, bios_addr, + bios_size); + } + } + } + if (bios_size < 0 || bios_size > BIOS_SIZE) { + hw_error("qemu: could not load bios image '%s'\n", s->bios_name); + } + if (filename) { + g_free(filename); + } + } + return 0; } @@ -212,12 +371,20 @@ static const TypeInfo raven_info = { .class_init = raven_class_init, }; +static Property raven_pcihost_properties[] = { + DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, + EM_NONE), + DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), + DEFINE_PROP_END_OF_LIST() +}; + static void raven_pcihost_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->realize = raven_pcihost_realizefn; + dc->props = raven_pcihost_properties; dc->fw_name = "pci"; } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 4e0701d..8f722dd 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -48,7 +48,6 @@ static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); static char *pcibus_get_dev_path(DeviceState *dev); static char *pcibus_get_fw_dev_path(DeviceState *dev); static void pcibus_reset(BusState *qbus); -static void pci_bus_finalize(Object *obj); static Property pci_props[] = { DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), @@ -61,6 +60,34 @@ static Property pci_props[] = { DEFINE_PROP_END_OF_LIST() }; +static const VMStateDescription vmstate_pcibus = { + .name = "PCIBUS", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_INT32_EQUAL(nirq, PCIBus), + VMSTATE_VARRAY_INT32(irq_count, PCIBus, + nirq, 0, vmstate_info_int32, + int32_t), + VMSTATE_END_OF_LIST() + } +}; + +static void pci_bus_realize(BusState *qbus, Error **errp) +{ + PCIBus *bus = PCI_BUS(qbus); + + vmstate_register(NULL, -1, &vmstate_pcibus, bus); +} + +static void pci_bus_unrealize(BusState *qbus, Error **errp) +{ + PCIBus *bus = PCI_BUS(qbus); + + vmstate_unregister(NULL, &vmstate_pcibus, bus); +} + static void pci_bus_class_init(ObjectClass *klass, void *data) { BusClass *k = BUS_CLASS(klass); @@ -68,6 +95,8 @@ static void pci_bus_class_init(ObjectClass *klass, void *data) k->print_dev = pcibus_dev_print; k->get_dev_path = pcibus_get_dev_path; k->get_fw_dev_path = pcibus_get_fw_dev_path; + k->realize = pci_bus_realize; + k->unrealize = pci_bus_unrealize; k->reset = pcibus_reset; } @@ -75,7 +104,6 @@ static const TypeInfo pci_bus_info = { .name = TYPE_PCI_BUS, .parent = TYPE_BUS, .instance_size = sizeof(PCIBus), - .instance_finalize = pci_bus_finalize, .class_init = pci_bus_class_init, }; @@ -95,17 +123,6 @@ static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; static QLIST_HEAD(, PCIHostState) pci_host_bridges; -static const VMStateDescription vmstate_pcibus = { - .name = "PCIBUS", - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, - .fields = (VMStateField []) { - VMSTATE_INT32_EQUAL(nirq, PCIBus), - VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), - VMSTATE_END_OF_LIST() - } -}; static int pci_bar(PCIDevice *d, int reg) { uint8_t type; @@ -299,8 +316,6 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent, QLIST_INIT(&bus->child); pci_host_bus_register(bus, parent); - - vmstate_register(NULL, -1, &vmstate_pcibus, bus); } bool pci_bus_is_express(PCIBus *bus) @@ -369,12 +384,6 @@ int pci_bus_num(PCIBus *s) return s->parent_dev->config[PCI_SECONDARY_BUS]; } -static void pci_bus_finalize(Object *obj) -{ - PCIBus *bus = PCI_BUS(obj); - vmstate_unregister(NULL, &vmstate_pcibus, bus); -} - static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) { PCIDevice *s = container_of(pv, PCIDevice, config); diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c index 8f17596..96f3774 100644 --- a/hw/pcmcia/pxa2xx.c +++ b/hw/pcmcia/pxa2xx.c @@ -198,7 +198,9 @@ static void pxa2xx_pcmcia_initfn(Object *obj) s->slot.irq = qemu_allocate_irqs(pxa2xx_pcmcia_set_irq, s, 1)[0]; object_property_add_link(obj, "card", TYPE_PCMCIA_CARD, - (Object **)&s->card, NULL); + (Object **)&s->card, + NULL, /* read-only property */ + 0, NULL); } /* Insert a new card into a slot */ diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 8a08752..d7ba25f 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -472,14 +472,13 @@ static void ppce500_cpu_reset_sec(void *opaque) { PowerPCCPU *cpu = opaque; CPUState *cs = CPU(cpu); - CPUPPCState *env = &cpu->env; cpu_reset(cs); /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } static void ppce500_cpu_reset(void *opaque) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index ca520e8..54ba59e 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -44,7 +44,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); ram_addr_t bdloc; int i, n; diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 78b23fa..f9fdc8c 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -117,7 +117,7 @@ static void spin_kick(void *data) mmubooke_create_initial_mapping(env, 0, map_start, map_size); cpu->halted = 0; - env->exception_index = -1; + cpu->exception_index = -1; cpu->stopped = false; qemu_cpu_kick(cpu); } diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 9f8538c..e243651 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -185,6 +185,7 @@ typedef struct sysctrl_t { uint8_t state; uint8_t syscontrol; int contiguous_map; + qemu_irq contiguous_map_irq; int endian; } sysctrl_t; @@ -253,6 +254,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) case 0x0850: /* I/O map type register */ sysctrl->contiguous_map = val & 0x01; + qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); break; default: printf("ERROR: unaffected IO port write: %04" PRIx32 @@ -327,91 +329,6 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) return retval; } -static inline hwaddr prep_IO_address(sysctrl_t *sysctrl, - hwaddr addr) -{ - if (sysctrl->contiguous_map == 0) { - /* 64 KB contiguous space for IOs */ - addr &= 0xFFFF; - } else { - /* 8 MB non-contiguous space for IOs */ - addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); - } - - return addr; -} - -static void PPC_prep_io_writeb (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl = opaque; - - addr = prep_IO_address(sysctrl, addr); - cpu_outb(addr, value); -} - -static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl = opaque; - uint32_t ret; - - addr = prep_IO_address(sysctrl, addr); - ret = cpu_inb(addr); - - return ret; -} - -static void PPC_prep_io_writew (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl = opaque; - - addr = prep_IO_address(sysctrl, addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); - cpu_outw(addr, value); -} - -static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl = opaque; - uint32_t ret; - - addr = prep_IO_address(sysctrl, addr); - ret = cpu_inw(addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); - - return ret; -} - -static void PPC_prep_io_writel (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl = opaque; - - addr = prep_IO_address(sysctrl, addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); - cpu_outl(addr, value); -} - -static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl = opaque; - uint32_t ret; - - addr = prep_IO_address(sysctrl, addr); - ret = cpu_inl(addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); - - return ret; -} - -static const MemoryRegionOps PPC_prep_io_ops = { - .old_mmio = { - .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, - .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, -}; #define NVRAM_SIZE 0x2000 @@ -456,17 +373,15 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) MemoryRegion *sysmem = get_system_memory(); PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; - char *filename; nvram_t nvram; M48t59State *m48t59; - MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); PortioList *port_list = g_new(PortioList, 1); #if 0 MemoryRegion *xcsr = g_new(MemoryRegion, 1); #endif - int linux_boot, i, nb_nics1, bios_size; + int linux_boot, i, nb_nics1; MemoryRegion *ram = g_new(MemoryRegion, 1); - MemoryRegion *bios = g_new(MemoryRegion, 1); + MemoryRegion *vga = g_new(MemoryRegion, 1); uint32_t kernel_base, initrd_base; long kernel_size, initrd_size; DeviceState *dev; @@ -509,43 +424,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) vmstate_register_ram_global(ram); memory_region_add_subregion(sysmem, 0, ram); - /* allocate and load BIOS */ - memory_region_init_ram(bios, NULL, "ppc_prep.bios", BIOS_SIZE); - memory_region_set_readonly(bios, true); - memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios); - vmstate_register_ram_global(bios); - if (bios_name == NULL) - bios_name = BIOS_FILENAME; - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - if (filename) { - bios_size = load_elf(filename, NULL, NULL, NULL, - NULL, NULL, 1, ELF_MACHINE, 0); - if (bios_size < 0) { - bios_size = get_image_size(filename); - if (bios_size > 0 && bios_size <= BIOS_SIZE) { - hwaddr bios_addr; - bios_size = (bios_size + 0xfff) & ~0xfff; - bios_addr = (uint32_t)(-bios_size); - bios_size = load_image_targphys(filename, bios_addr, bios_size); - } - if (bios_size > BIOS_SIZE) { - fprintf(stderr, "qemu: PReP bios '%s' is too large (0x%x)\n", - bios_name, bios_size); - exit(1); - } - } - } else { - bios_size = -1; - } - if (bios_size < 0 && !qtest_enabled()) { - fprintf(stderr, "qemu: could not load PPC PReP bios '%s'\n", - bios_name); - exit(1); - } - if (filename) { - g_free(filename); - } - if (linux_boot) { kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ @@ -593,6 +471,11 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) } dev = qdev_create(NULL, "raven-pcihost"); + if (bios_name == NULL) { + bios_name = BIOS_FILENAME; + } + qdev_prop_set_string(dev, "bios-name", bios_name); + qdev_prop_set_uint32(dev, "elf-machine", ELF_MACHINE); pcihost = PCI_HOST_BRIDGE(dev); object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); qdev_init_nofail(dev); @@ -601,6 +484,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) fprintf(stderr, "Couldn't create PCI host controller.\n"); exit(1); } + sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); /* PCI -> ISA bridge */ pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); @@ -621,13 +505,16 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ qdev_init_nofail(dev); - /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ - memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl, - "ppc-io", 0x00800000); - memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); - /* init basic PC hardware */ pci_vga_init(pci_bus); + /* Open Hack'Ware hack: PCI BAR#0 is programmed to 0xf0000000. + * While bios will access framebuffer at 0xf0000000, real physical + * address is 0xf0000000 + 0xc0000000 (PCI memory base). + * Alias the wrong memory accesses to the right place. + */ + memory_region_init_alias(vga, NULL, "vga-alias", pci_address_space(pci), + 0xf0000000, 0x1000000); + memory_region_add_subregion_overlap(sysmem, 0xf0000000, vga, 10); nb_nics1 = nb_nics; if (nb_nics1 > NE2000_NB_MAX) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index bf46c38..a11e121 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -26,6 +26,7 @@ */ #include "sysemu/sysemu.h" #include "hw/hw.h" +#include "hw/fw-path-provider.h" #include "elf.h" #include "net/net.h" #include "sysemu/blockdev.h" @@ -45,6 +46,8 @@ #include "hw/pci/msi.h" #include "hw/pci/pci.h" +#include "hw/scsi/scsi.h" +#include "hw/virtio/virtio-scsi.h" #include "exec/address-spaces.h" #include "hw/usb.h" @@ -81,6 +84,8 @@ #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) +#define TYPE_SPAPR_MACHINE "spapr-machine" + sPAPREnvironment *spapr; int spapr_allocate_irq(int hint, bool lsi) @@ -598,7 +603,9 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr, hwaddr rtas_addr, hwaddr rtas_size) { - int ret; + int ret, i; + size_t cb = 0; + char *bootlist; void *fdt; sPAPRPHBState *phb; @@ -640,6 +647,21 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr, fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); } + bootlist = get_boot_devices_list(&cb, true); + if (cb && bootlist) { + int offset = fdt_path_offset(fdt, "/chosen"); + if (offset < 0) { + exit(1); + } + for (i = 0; i < cb; i++) { + if (bootlist[i] == '\n') { + bootlist[i] = ' '; + } + + } + ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); + } + if (!spapr->has_graphics) { spapr_populate_chosen_stdout(fdt, spapr->vio_bus); } @@ -781,13 +803,15 @@ static int spapr_vga_init(PCIBus *pci_bus) { switch (vga_interface_type) { case VGA_NONE: + return false; + case VGA_DEVICE: + return true; case VGA_STD: return pci_vga_init(pci_bus) != NULL; default: fprintf(stderr, "This vga model is not supported," "currently it only supports -vga std\n"); exit(0); - break; } } @@ -1408,9 +1432,86 @@ static QEMUMachine spapr_machine = { .kvm_type = spapr_kvm_type, }; -static void spapr_machine_init(void) +/* + * Implementation of an interface to adjust firmware patch + * for the bootindex property handling. + */ +static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, + DeviceState *dev) +{ +#define CAST(type, obj, name) \ + ((type *)object_dynamic_cast(OBJECT(obj), (name))) + SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); + sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); + + if (d) { + void *spapr = CAST(void, bus->parent, "spapr-vscsi"); + VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); + USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); + + if (spapr) { + /* + * Replace "channel@0/disk@0,0" with "disk@8000000000000000": + * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun + * in the top 16 bits of the 64-bit LUN + */ + unsigned id = 0x8000 | (d->id << 8) | d->lun; + return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), + (uint64_t)id << 48); + } else if (virtio) { + /* + * We use SRP luns of the form 01000000 | (target << 8) | lun + * in the top 32 bits of the 64-bit LUN + * Note: the quote above is from SLOF and it is wrong, + * the actual binding is: + * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) + */ + unsigned id = 0x1000000 | (d->id << 16) | d->lun; + return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), + (uint64_t)id << 32); + } else if (usb) { + /* + * We use SRP luns of the form 01000000 | (usb-port << 16) | lun + * in the top 32 bits of the 64-bit LUN + */ + unsigned usb_port = atoi(usb->port->path); + unsigned id = 0x1000000 | (usb_port << 16) | d->lun; + return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), + (uint64_t)id << 32); + } + } + + if (phb) { + /* Replace "pci" with "pci@800000020000000" */ + return g_strdup_printf("pci@%"PRIX64, phb->buid); + } + + return NULL; +} + +static void spapr_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); + + mc->qemu_machine = data; + fwc->get_dev_path = spapr_get_fw_dev_path; +} + +static const TypeInfo spapr_machine_info = { + .name = TYPE_SPAPR_MACHINE, + .parent = TYPE_MACHINE, + .class_init = spapr_machine_class_init, + .class_data = &spapr_machine, + .interfaces = (InterfaceInfo[]) { + { TYPE_FW_PATH_PROVIDER }, + { } + }, +}; + +static void spapr_machine_register_types(void) { - qemu_register_machine(&spapr_machine); + type_register_static(&spapr_machine_info); } -machine_init(spapr_machine_init); +type_init(spapr_machine_register_types) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index d918780..0bae053 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -4,6 +4,36 @@ #include "hw/ppc/spapr.h" #include "mmu-hash64.h" +struct SPRSyncState { + CPUState *cs; + int spr; + target_ulong value; + target_ulong mask; +}; + +static void do_spr_sync(void *arg) +{ + struct SPRSyncState *s = arg; + PowerPCCPU *cpu = POWERPC_CPU(s->cs); + CPUPPCState *env = &cpu->env; + + cpu_synchronize_state(s->cs); + env->spr[s->spr] &= ~s->mask; + env->spr[s->spr] |= s->value; +} + +static void set_spr(CPUState *cs, int spr, target_ulong value, + target_ulong mask) +{ + struct SPRSyncState s = { + .cs = cs, + .spr = spr, + .value = value, + .mask = mask + }; + run_on_cpu(cs, do_spr_sync, &s); +} + static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, target_ulong pte_index) { @@ -110,16 +140,15 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr, if (likely((flags & H_EXACT) == 0)) { pte_index &= ~7ULL; token = ppc_hash64_start_access(cpu, pte_index); - do { - if (index == 8) { - ppc_hash64_stop_access(token); - return H_PTEG_FULL; - } + for (; index < 8; index++) { if ((ppc_hash64_load_hpte0(env, token, index) & HPTE64_V_VALID) == 0) { break; } - } while (index++); + } ppc_hash64_stop_access(token); + if (index == 8) { + return H_PTEG_FULL; + } } else { token = ppc_hash64_start_access(cpu, pte_index); if (ppc_hash64_load_hpte0(env, token, 0) & HPTE64_V_VALID) { @@ -356,7 +385,7 @@ static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr, static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint16_t size; uint8_t tmp; @@ -406,7 +435,7 @@ static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint32_t size; if (addr == 0) { @@ -442,7 +471,7 @@ static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint32_t size; if (addr == 0) { @@ -529,7 +558,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, hreg_compute_hflags(env); if (!cpu_has_work(cs)) { cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cs->exit_request = 1; } return H_SUCCESS; @@ -690,7 +719,7 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong value2 = args[3]; target_ulong ret = H_P2; - if (resource == H_SET_MODE_ENDIAN) { + if (resource == H_SET_MODE_RESOURCE_LE) { if (value1) { ret = H_P3; goto out; @@ -699,22 +728,17 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, ret = H_P4; goto out; } - switch (mflags) { case H_SET_MODE_ENDIAN_BIG: CPU_FOREACH(cs) { - PowerPCCPU *cp = POWERPC_CPU(cs); - CPUPPCState *env = &cp->env; - env->spr[SPR_LPCR] &= ~LPCR_ILE; + set_spr(cs, SPR_LPCR, 0, LPCR_ILE); } ret = H_SUCCESS; break; case H_SET_MODE_ENDIAN_LITTLE: CPU_FOREACH(cs) { - PowerPCCPU *cp = POWERPC_CPU(cs); - CPUPPCState *env = &cp->env; - env->spr[SPR_LPCR] |= LPCR_ILE; + set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); } ret = H_SUCCESS; break; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index cea9469..cbef095 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -32,6 +32,7 @@ #include "exec/address-spaces.h" #include <libfdt.h> #include "trace.h" +#include "qemu/error-report.h" #include "hw/pci/pci_bus.h" @@ -292,7 +293,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, ret_intr_type = RTAS_TYPE_MSIX; break; default: - fprintf(stderr, "rtas_ibm_change_msi(%u) is not implemented\n", func); + error_report("rtas_ibm_change_msi(%u) is not implemented", func); rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); return; } @@ -326,7 +327,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, /* Find a device number in the map to add or reuse the existing one */ ndev = spapr_msicfg_find(phb, config_addr, true); if (ndev >= SPAPR_MSIX_MAX_DEVS || ndev < 0) { - fprintf(stderr, "No free entry for a new MSI device\n"); + error_report("No free entry for a new MSI device"); rtas_st(rets, 0, RTAS_OUT_HW_ERROR); return; } @@ -335,7 +336,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, /* Check if there is an old config and MSI number has not changed */ if (phb->msi_table[ndev].nvec && (req_num != phb->msi_table[ndev].nvec)) { /* Unexpected behaviour */ - fprintf(stderr, "Cannot reuse MSI config for device#%d", ndev); + error_report("Cannot reuse MSI config for device#%d", ndev); rtas_st(rets, 0, RTAS_OUT_HW_ERROR); return; } @@ -345,7 +346,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, irq = spapr_allocate_irq_block(req_num, false, ret_intr_type == RTAS_TYPE_MSI); if (irq < 0) { - fprintf(stderr, "Cannot allocate MSIs for device#%d", ndev); + error_report("Cannot allocate MSIs for device#%d", ndev); rtas_st(rets, 0, RTAS_OUT_HW_ERROR); return; } @@ -505,12 +506,11 @@ static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) return &phb->iommu_as; } -static int spapr_phb_init(SysBusDevice *s) +static void spapr_phb_realize(DeviceState *dev, Error **errp) { - DeviceState *dev = DEVICE(s); + SysBusDevice *s = SYS_BUS_DEVICE(dev); sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); PCIHostState *phb = PCI_HOST_BRIDGE(s); - const char *busname; char *namebuf; int i; PCIBus *bus; @@ -521,9 +521,9 @@ static int spapr_phb_init(SysBusDevice *s) if ((sphb->buid != -1) || (sphb->dma_liobn != -1) || (sphb->mem_win_addr != -1) || (sphb->io_win_addr != -1)) { - fprintf(stderr, "Either \"index\" or other parameters must" - " be specified for PAPR PHB, not both\n"); - return -1; + error_setg(errp, "Either \"index\" or other parameters must" + " be specified for PAPR PHB, not both"); + return; } sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; @@ -536,28 +536,28 @@ static int spapr_phb_init(SysBusDevice *s) } if (sphb->buid == -1) { - fprintf(stderr, "BUID not specified for PHB\n"); - return -1; + error_setg(errp, "BUID not specified for PHB"); + return; } if (sphb->dma_liobn == -1) { - fprintf(stderr, "LIOBN not specified for PHB\n"); - return -1; + error_setg(errp, "LIOBN not specified for PHB"); + return; } if (sphb->mem_win_addr == -1) { - fprintf(stderr, "Memory window address not specified for PHB\n"); - return -1; + error_setg(errp, "Memory window address not specified for PHB"); + return; } if (sphb->io_win_addr == -1) { - fprintf(stderr, "IO window address not specified for PHB\n"); - return -1; + error_setg(errp, "IO window address not specified for PHB"); + return; } if (find_phb(spapr, sphb->buid)) { - fprintf(stderr, "PCI host bridges must have unique BUIDs\n"); - return -1; + error_setg(errp, "PCI host bridges must have unique BUIDs"); + return; } sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); @@ -594,26 +594,8 @@ static int spapr_phb_init(SysBusDevice *s) get_system_io(), 0, SPAPR_PCI_IO_WIN_SIZE); memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, &sphb->iowindow); - /* - * Selecting a busname is more complex than you'd think, due to - * interacting constraints. If the user has specified an id - * explicitly for the phb , then we want to use the qdev default - * of naming the bus based on the bridge device (so the user can - * then assign devices to it in the way they expect). For the - * first / default PCI bus (index=0) we want to use just "pci" - * because libvirt expects there to be a bus called, simply, - * "pci". Otherwise, we use the same name as in the device tree, - * since it's unique by construction, and makes the guest visible - * BUID clear. - */ - if (dev->id) { - busname = NULL; - } else if (sphb->index == 0) { - busname = "pci"; - } else { - busname = sphb->dtbusname; - } - bus = pci_register_bus(dev, busname, + + bus = pci_register_bus(dev, NULL, pci_spapr_set_irq, pci_spapr_map_irq, sphb, &sphb->memspace, &sphb->iospace, PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); @@ -624,8 +606,9 @@ static int spapr_phb_init(SysBusDevice *s) sphb->tcet = spapr_tce_new_table(dev, sphb->dma_liobn, sphb->dma_window_size); if (!sphb->tcet) { - fprintf(stderr, "Unable to create TCE table for %s\n", sphb->dtbusname); - return -1; + error_setg(errp, "Unable to create TCE table for %s", + sphb->dtbusname); + return; } address_space_init(&sphb->iommu_as, spapr_tce_get_iommu(sphb->tcet), sphb->dtbusname); @@ -642,13 +625,12 @@ static int spapr_phb_init(SysBusDevice *s) irq = spapr_allocate_lsi(0); if (!irq) { - return -1; + error_setg(errp, "spapr_allocate_lsi failed"); + return; } sphb->lsi_table[i].irq = irq; } - - return 0; } static void spapr_phb_reset(DeviceState *qdev) @@ -731,11 +713,10 @@ static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, static void spapr_phb_class_init(ObjectClass *klass, void *data) { PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); hc->root_bus_path = spapr_phb_root_bus_path; - sdc->init = spapr_phb_init; + dc->realize = spapr_phb_realize; dc->props = spapr_phb_properties; dc->reset = spapr_phb_reset; dc->vmsd = &vmstate_spapr_pci; diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index 4e33f46..2ae06a3 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -68,6 +68,7 @@ static void spapr_vio_bus_class_init(ObjectClass *klass, void *data) BusClass *k = BUS_CLASS(klass); k->get_dev_path = spapr_vio_get_dev_name; + k->get_fw_dev_path = spapr_vio_get_dev_name; } static const TypeInfo spapr_vio_bus_info = { @@ -529,7 +530,9 @@ static int spapr_vio_bridge_init(SysBusDevice *dev) static void spapr_vio_bridge_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + dc->fw_name = "vdevice"; k->init = spapr_vio_bridge_init; } diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 32d38a0..4fa9cff 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -80,7 +80,7 @@ static int s390_ipl_init(SysBusDevice *dev) bios_size = load_elf(bios_filename, NULL, NULL, &ipl->start_addr, NULL, NULL, 1, ELF_MACHINE, 0); - if (bios_size == -1) { + if (bios_size < 0) { bios_size = load_image_targphys(bios_filename, ZIPL_IMAGE_START, 4096); ipl->start_addr = ZIPL_IMAGE_START; diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c index e4fc353..9c71afa 100644 --- a/hw/s390x/s390-virtio-bus.c +++ b/hw/s390x/s390-virtio-bus.c @@ -313,7 +313,9 @@ static void s390_virtio_rng_instance_init(Object *obj) object_initialize(&dev->vdev, sizeof(dev->vdev), TYPE_VIRTIO_RNG); object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL); object_property_add_link(obj, "rng", TYPE_RNG_BACKEND, - (Object **)&dev->vdev.conf.rng, NULL); + (Object **)&dev->vdev.conf.rng, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, NULL); } static uint64_t s390_virtio_device_vq_token(VirtIOS390Device *dev, int vq) diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c index 0f03fd1..aef2003 100644 --- a/hw/s390x/s390-virtio.c +++ b/hw/s390x/s390-virtio.c @@ -135,25 +135,23 @@ static unsigned s390_running_cpus; void s390_add_running_cpu(S390CPU *cpu) { CPUState *cs = CPU(cpu); - CPUS390XState *env = &cpu->env; if (cs->halted) { s390_running_cpus++; cs->halted = 0; - env->exception_index = -1; + cs->exception_index = -1; } } unsigned s390_del_running_cpu(S390CPU *cpu) { CPUState *cs = CPU(cpu); - CPUS390XState *env = &cpu->env; if (cs->halted == 0) { assert(s390_running_cpus >= 1); s390_running_cpus--; cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } return s390_running_cpus; } @@ -196,7 +194,7 @@ void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys) ipi_states[i] = cpu; cs->halted = 1; - cpu->env.exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu->env.storage_keys = storage_keys; } } diff --git a/hw/s390x/sclpcpu.c b/hw/s390x/sclpcpu.c index b9c238a..3600fe2 100644 --- a/hw/s390x/sclpcpu.c +++ b/hw/s390x/sclpcpu.c @@ -25,13 +25,13 @@ typedef struct ConfigMgtData { uint8_t event_qualifier; } QEMU_PACKED ConfigMgtData; -static qemu_irq irq_cpu_hotplug; /* Only used in this file */ +static qemu_irq *irq_cpu_hotplug; /* Only used in this file */ #define EVENT_QUAL_CPU_CHANGE 1 void raise_irq_cpu_hotplug(void) { - qemu_irq_raise(irq_cpu_hotplug); + qemu_irq_raise(*irq_cpu_hotplug); } static unsigned int send_mask(void) @@ -81,7 +81,7 @@ static void trigger_signal(void *opaque, int n, int level) static int irq_cpu_hotplug_init(SCLPEvent *event) { - irq_cpu_hotplug = *qemu_allocate_irqs(trigger_signal, event, 1); + irq_cpu_hotplug = qemu_allocate_irqs(trigger_signal, event, 1); return 0; } diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index a01801e..2bf0af8 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -1272,7 +1272,9 @@ static void virtio_ccw_rng_instance_init(Object *obj) object_initialize(&dev->vdev, sizeof(dev->vdev), TYPE_VIRTIO_RNG); object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL); object_property_add_link(obj, "rng", TYPE_RNG_BACKEND, - (Object **)&dev->vdev.conf.rng, NULL); + (Object **)&dev->vdev.conf.rng, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, NULL); } static Property virtio_ccw_rng_properties[] = { diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c index 50a0acf..eaad925 100644 --- a/hw/scsi/scsi-bus.c +++ b/hw/scsi/scsi-bus.c @@ -1905,6 +1905,26 @@ static const VMStateInfo vmstate_info_scsi_requests = { .put = put_scsi_requests, }; +static bool scsi_sense_state_needed(void *opaque) +{ + SCSIDevice *s = opaque; + + return s->sense_len > SCSI_SENSE_BUF_SIZE_OLD; +} + +static const VMStateDescription vmstate_scsi_sense_state = { + .name = "SCSIDevice/sense", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT8_SUB_ARRAY(sense, SCSIDevice, + SCSI_SENSE_BUF_SIZE_OLD, + SCSI_SENSE_BUF_SIZE - SCSI_SENSE_BUF_SIZE_OLD), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_scsi_device = { .name = "SCSIDevice", .version_id = 1, @@ -1915,7 +1935,7 @@ const VMStateDescription vmstate_scsi_device = { VMSTATE_UINT8(unit_attention.asc, SCSIDevice), VMSTATE_UINT8(unit_attention.ascq, SCSIDevice), VMSTATE_BOOL(sense_is_ua, SCSIDevice), - VMSTATE_UINT8_ARRAY(sense, SCSIDevice, SCSI_SENSE_BUF_SIZE), + VMSTATE_UINT8_SUB_ARRAY(sense, SCSIDevice, 0, SCSI_SENSE_BUF_SIZE_OLD), VMSTATE_UINT32(sense_len, SCSIDevice), { .name = "requests", @@ -1927,6 +1947,14 @@ const VMStateDescription vmstate_scsi_device = { .offset = 0, }, VMSTATE_END_OF_LIST() + }, + .subsections = (VMStateSubsection []) { + { + .vmsd = &vmstate_scsi_sense_state, + .needed = scsi_sense_state_needed, + }, { + /* empty */ + } } }; diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c index b3835c8..34478f0 100644 --- a/hw/scsi/spapr_vscsi.c +++ b/hw/scsi/spapr_vscsi.c @@ -195,9 +195,9 @@ static int vscsi_send_iu(VSCSIState *s, vscsi_req *req, req->crq.s.IU_data_ptr = req->iu.srp.rsp.tag; /* right byte order */ if (rc == 0) { - req->crq.s.status = 0x99; /* Just needs to be non-zero */ + req->crq.s.status = VIOSRP_OK; } else { - req->crq.s.status = 0x00; + req->crq.s.status = VIOSRP_ADAPTER_FAIL; } rc1 = spapr_vio_send_crq(&s->vdev, req->crq.raw); diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c index 6610b3a..b0d7517 100644 --- a/hw/scsi/virtio-scsi.c +++ b/hw/scsi/virtio-scsi.c @@ -304,6 +304,8 @@ static void virtio_scsi_command_complete(SCSIRequest *r, uint32_t status, size_t resid) { VirtIOSCSIReq *req = r->hba_private; + VirtIOSCSI *s = req->dev; + VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(s); uint32_t sense_len; if (r->io_canceled) { @@ -317,7 +319,7 @@ static void virtio_scsi_command_complete(SCSIRequest *r, uint32_t status, } else { req->resp.cmd->resid = 0; sense_len = scsi_req_get_sense(r, req->resp.cmd->sense, - VIRTIO_SCSI_SENSE_SIZE); + vs->sense_size); req->resp.cmd->sense_len = tswap32(sense_len); } virtio_scsi_complete_req(req); diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 1bb56c4..3273c8a 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -238,9 +238,10 @@ static int ssi_sd_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static int ssi_sd_init(SSISlave *dev) +static int ssi_sd_init(SSISlave *d) { - ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev); + DeviceState *dev = DEVICE(d); + ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d); DriveInfo *dinfo; s->mode = SSI_SD_CMD; @@ -249,7 +250,7 @@ static int ssi_sd_init(SSISlave *dev) if (s->sd == NULL) { return -1; } - register_savevm(&dev->qdev, "ssi_sd", -1, 1, ssi_sd_save, ssi_sd_load, s); + register_savevm(dev, "ssi_sd", -1, 1, ssi_sd_save, ssi_sd_load, s); return 0; } diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 1439ba4..4a39357 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { - tlb_flush(&s->cpu->env, 1); + tlb_flush(CPU(s->cpu), 1); } s->cpu->env.pteh = mem_value; return; diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index 2c25260..017f022 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -15,7 +15,7 @@ #include "hw/ssi.h" struct SSIBus { - BusState qbus; + BusState parent_obj; }; #define TYPE_SSI_BUS "SSI" @@ -60,7 +60,7 @@ static int ssi_slave_init(DeviceState *dev) if (ssc->transfer_raw == ssi_transfer_raw_default && ssc->cs_polarity != SSI_CS_NONE) { - qdev_init_gpio_in(&s->qdev, ssi_cs_default, 1); + qdev_init_gpio_in(dev, ssi_cs_default, 1); } return ssc->init(s); @@ -88,7 +88,7 @@ static const TypeInfo ssi_slave_info = { DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name) { - return qdev_create(&bus->qbus, name); + return qdev_create(BUS(bus), name); } DeviceState *ssi_create_slave(SSIBus *bus, const char *name) @@ -108,11 +108,12 @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name) uint32_t ssi_transfer(SSIBus *bus, uint32_t val) { + BusState *b = BUS(bus); BusChild *kid; SSISlaveClass *ssc; uint32_t r = 0; - QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { + QTAILQ_FOREACH(kid, &b->children, sibling) { SSISlave *slave = SSI_SLAVE(kid->child); ssc = SSI_SLAVE_GET_CLASS(slave); r |= ssc->transfer_raw(slave, val); @@ -156,7 +157,7 @@ static int ssi_auto_connect_slave(Object *child, void *opaque) } cs_line = qdev_get_gpio_in(DEVICE(dev), 0); - qdev_set_parent_bus(DEVICE(dev), &arg->bus->qbus); + qdev_set_parent_bus(DEVICE(dev), BUS(arg->bus)); **arg->cs_linep = cs_line; (*arg->cs_linep)++; return 0; diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 6a28746..8977243 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -43,7 +43,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) -#define IFMODE (1 << 31) +#define IFMODE (1U << 31) #define ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) @@ -87,7 +87,7 @@ #define R_LQSPI_CFG (0xa0 / 4) #define R_LQSPI_CFG_RESET 0x03A002EB -#define LQSPI_CFG_LQ_MODE (1 << 31) +#define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) #define LQSPI_CFG_SEP_BUS (1 << 30) #define LQSPI_CFG_U_PAGE (1 << 28) diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index 74c16d6..7672d3a 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -106,9 +106,9 @@ static void grlib_gptimer_enable(GPTimer *timer) /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at underflow. Set count + 1 to simulate the GPTimer behavior. */ - trace_grlib_gptimer_enable(timer->id, timer->counter + 1); + trace_grlib_gptimer_enable(timer->id, timer->counter); - ptimer_set_count(timer->ptimer, timer->counter + 1); + ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1); ptimer_run(timer->ptimer, 1); } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 7b91841..ce97514 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1517,7 +1517,9 @@ static void virtio_rng_initfn(Object *obj) object_initialize(&dev->vdev, sizeof(dev->vdev), TYPE_VIRTIO_RNG); object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL); object_property_add_link(obj, "rng", TYPE_RNG_BACKEND, - (Object **)&dev->vdev.conf.rng, NULL); + (Object **)&dev->vdev.conf.rng, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, NULL); } diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c index a16e3bc..b6ab361 100644 --- a/hw/virtio/virtio-rng.c +++ b/hw/virtio/virtio-rng.c @@ -162,6 +162,9 @@ static void virtio_rng_device_realize(DeviceState *dev, Error **errp) OBJECT(vrng->conf.default_backend), NULL); + /* The child property took a reference, we can safely drop ours now */ + object_unref(OBJECT(vrng->conf.default_backend)); + object_property_set_link(OBJECT(dev), OBJECT(vrng->conf.default_backend), "rng", NULL); @@ -223,7 +226,9 @@ static void virtio_rng_initfn(Object *obj) VirtIORNG *vrng = VIRTIO_RNG(obj); object_property_add_link(obj, "rng", TYPE_RNG_BACKEND, - (Object **)&vrng->conf.rng, NULL); + (Object **)&vrng->conf.rng, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, NULL); } static const TypeInfo virtio_rng_info = { diff --git a/include/block/aio.h b/include/block/aio.h index 2efdf41..a92511b 100644 --- a/include/block/aio.h +++ b/include/block/aio.h @@ -19,6 +19,7 @@ #include "qemu/queue.h" #include "qemu/event_notifier.h" #include "qemu/thread.h" +#include "qemu/rfifolock.h" #include "qemu/timer.h" typedef struct BlockDriverAIOCB BlockDriverAIOCB; @@ -47,6 +48,9 @@ typedef void IOHandler(void *opaque); struct AioContext { GSource source; + /* Protects all fields from multi-threaded access */ + RFifoLock lock; + /* The list of registered AIO handlers */ QLIST_HEAD(, AioHandler) aio_handlers; @@ -104,6 +108,20 @@ void aio_context_ref(AioContext *ctx); */ void aio_context_unref(AioContext *ctx); +/* Take ownership of the AioContext. If the AioContext will be shared between + * threads, a thread must have ownership when calling aio_poll(). + * + * Note that multiple threads calling aio_poll() means timers, BHs, and + * callbacks may be invoked from a different thread than they were registered + * from. Therefore, code must use AioContext acquire/release or use + * fine-grained synchronization to protect shared state if other threads will + * be accessing it simultaneously. + */ +void aio_context_acquire(AioContext *ctx); + +/* Relinquish ownership of the AioContext. */ +void aio_context_release(AioContext *ctx); + /** * aio_bh_new: Allocate a new bottom half structure. * diff --git a/include/block/block.h b/include/block/block.h index 780f48b..1ed55d8 100644 --- a/include/block/block.h +++ b/include/block/block.h @@ -286,15 +286,6 @@ int bdrv_check(BlockDriverState *bs, BdrvCheckResult *res, BdrvCheckMode fix); int bdrv_amend_options(BlockDriverState *bs_new, QEMUOptionParameter *options); /* external snapshots */ - -typedef enum { - BS_IS_A_FILTER, - BS_FILTER_PASS_DOWN, - BS_AUTHORIZATION_COUNT, -} BsAuthorization; - -bool bdrv_generic_is_first_non_filter(BlockDriverState *bs, - BlockDriverState *candidate); bool bdrv_recurse_is_first_non_filter(BlockDriverState *bs, BlockDriverState *candidate); bool bdrv_is_first_non_filter(BlockDriverState *candidate); @@ -338,8 +329,8 @@ BlockDriverAIOCB *bdrv_aio_ioctl(BlockDriverState *bs, BlockDriverCompletionFunc *cb, void *opaque); /* Invalidate any cached metadata used by image formats */ -void bdrv_invalidate_cache(BlockDriverState *bs); -void bdrv_invalidate_cache_all(void); +void bdrv_invalidate_cache(BlockDriverState *bs, Error **errp); +void bdrv_invalidate_cache_all(Error **errp); void bdrv_clear_incoming_migration_all(void); diff --git a/include/block/block_int.h b/include/block/block_int.h index 0bcf1c9..cd5bc73 100644 --- a/include/block/block_int.h +++ b/include/block/block_int.h @@ -76,10 +76,10 @@ struct BlockDriver { const char *format_name; int instance_size; - /* this table of boolean contains authorizations for the block operations */ - bool authorizations[BS_AUTHORIZATION_COUNT]; - /* for snapshots complex block filter like Quorum can implement the - * following recursive callback instead of BS_IS_A_FILTER. + /* set to true if the BlockDriver is a block filter */ + bool is_filter; + /* for snapshots block filter like Quorum can implement the + * following recursive callback. * It's purpose is to recurse on the filter children while calling * bdrv_recurse_is_first_non_filter on them. * For a sample implementation look in the future Quorum block filter. @@ -153,7 +153,7 @@ struct BlockDriver { /* * Invalidate any cached meta-data. */ - void (*bdrv_invalidate_cache)(BlockDriverState *bs); + void (*bdrv_invalidate_cache)(BlockDriverState *bs, Error **errp); /* * Flushes all data that was already written to the OS all the way down to diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4cb4b4a..fb649a4 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -360,9 +360,6 @@ int page_check_range(target_ulong start, target_ulong len, int flags); CPUArchState *cpu_copy(CPUArchState *env); -void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) - GCC_FMT_ATTR(2, 3); - /* Flags for use in ENV->INTERRUPT_PENDING. The numbers assigned here are non-sequential in order to preserve @@ -413,27 +410,6 @@ void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) | CPU_INTERRUPT_TGT_EXT_3 \ | CPU_INTERRUPT_TGT_EXT_4) -/* Breakpoint/watchpoint flags */ -#define BP_MEM_READ 0x01 -#define BP_MEM_WRITE 0x02 -#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) -#define BP_STOP_BEFORE_ACCESS 0x04 -#define BP_WATCHPOINT_HIT 0x08 -#define BP_GDB 0x10 -#define BP_CPU 0x20 - -int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, - CPUBreakpoint **breakpoint); -int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); -void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); -void cpu_breakpoint_remove_all(CPUArchState *env, int mask); -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, - int flags, CPUWatchpoint **watchpoint); -int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, - target_ulong len, int flags); -void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); -void cpu_watchpoint_remove_all(CPUArchState *env, int mask); - #if !defined(CONFIG_USER_ONLY) /* memory API */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 01cd8c7..2dd6206 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -24,7 +24,6 @@ #endif #include "config.h" -#include <setjmp.h> #include <inttypes.h> #include "qemu/osdep.h" #include "qemu/queue.h" @@ -59,9 +58,7 @@ typedef uint64_t target_ulong; #define EXCP_HLT 0x10001 /* hlt instruction reached */ #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ - -#define TB_JMP_CACHE_BITS 12 -#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) +#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for addresses on the same page. The top bits are the same. This allows @@ -117,66 +114,9 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #endif -#ifdef HOST_WORDS_BIGENDIAN -typedef struct icount_decr_u16 { - uint16_t high; - uint16_t low; -} icount_decr_u16; -#else -typedef struct icount_decr_u16 { - uint16_t low; - uint16_t high; -} icount_decr_u16; -#endif - -typedef struct CPUBreakpoint { - target_ulong pc; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUBreakpoint) entry; -} CPUBreakpoint; - -typedef struct CPUWatchpoint { - target_ulong vaddr; - target_ulong len_mask; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUWatchpoint) entry; -} CPUWatchpoint; - #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ - /* in order to avoid passing too many arguments to the MMIO \ - helpers, we store some rarely used information in the CPU \ - context) */ \ - uintptr_t mem_io_pc; /* host pc at which the memory was \ - accessed */ \ - target_ulong mem_io_vaddr; /* target virtual addr at which the \ - memory was accessed */ \ CPU_COMMON_TLB \ - struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ - \ - int64_t icount_extra; /* Instructions until next timer event. */ \ - /* Number of cycles left, with interrupt flag in high bit. \ - This allows a single read-compare-cbranch-write sequence to test \ - for both decrementer underflow and exceptions. */ \ - union { \ - uint32_t u32; \ - icount_decr_u16 u16; \ - } icount_decr; \ - uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ - \ - /* from this point: preserved by CPU reset */ \ - /* ice debug support */ \ - QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ - \ - QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ - CPUWatchpoint *watchpoint_hit; \ - \ - /* Core interrupt code */ \ - sigjmp_buf jmp_env; \ - int exception_index; \ - \ - /* user data */ \ - void *opaque; \ #endif diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index e21cb60..b8ecd6f 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -22,7 +22,7 @@ #if !defined(CONFIG_USER_ONLY) /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); -void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, +void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr); void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length); @@ -31,12 +31,12 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr); extern int tlb_flush_count; /* exec.c */ -void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr); +void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); MemoryRegionSection * address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat, hwaddr *plen); -hwaddr memory_region_section_get_iotlb(CPUArchState *env, +hwaddr memory_region_section_get_iotlb(CPUState *cpu, MemoryRegionSection *section, target_ulong vaddr, hwaddr paddr, hwaddr xlat, diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a387922..f9ac332 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -44,7 +44,7 @@ struct TranslationBlock; typedef struct TranslationBlock TranslationBlock; /* XXX: make safe guess about sizes */ -#define MAX_OP_PER_INSTR 208 +#define MAX_OP_PER_INSTR 266 #if HOST_LONG_BITS == 32 #define MAX_OPC_PARAM_PER_ARG 2 @@ -80,16 +80,16 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, void cpu_gen_init(void); int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, int *gen_code_size_ptr); -bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc); +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); -void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); -void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr); -TranslationBlock *tb_gen_code(CPUArchState *env, +void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc); +void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); +TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, int cflags); void cpu_exec_init(CPUArchState *env); -void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1); +void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); int page_unprotect(target_ulong address, uintptr_t pc, void *puc); void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, int is_cpu_write_access); @@ -98,18 +98,18 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, #if !defined(CONFIG_USER_ONLY) void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ -void tlb_flush_page(CPUArchState *env, target_ulong addr); -void tlb_flush(CPUArchState *env, int flush_global); -void tlb_set_page(CPUArchState *env, target_ulong vaddr, +void tlb_flush_page(CPUState *cpu, target_ulong addr); +void tlb_flush(CPUState *cpu, int flush_global); +void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); #else -static inline void tlb_flush_page(CPUArchState *env, target_ulong addr) +static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } -static inline void tlb_flush(CPUArchState *env, int flush_global) +static inline void tlb_flush(CPUState *cpu, int flush_global) { } #endif @@ -332,7 +332,7 @@ bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, uint64_t value, unsigned size); -void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr); uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); @@ -380,20 +380,25 @@ extern int singlestep; /* cpu-exec.c */ extern volatile sig_atomic_t exit_request; -/* Deterministic execution requires that IO only be performed on the last - instruction of a TB so that interrupts take effect immediately. */ -static inline int can_do_io(CPUArchState *env) +/** + * cpu_can_do_io: + * @cpu: The CPU for which to check IO. + * + * Deterministic execution requires that IO only be performed on the last + * instruction of a TB so that interrupts take effect immediately. + * + * Returns: %true if memory-mapped IO is safe, %false otherwise. + */ +static inline bool cpu_can_do_io(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - if (!use_icount) { - return 1; + return true; } /* If not executing code then assume we are ok. */ if (cpu->current_tb == NULL) { - return 1; + return true; } - return env->can_do_io != 0; + return cpu->can_do_io != 0; } #endif diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 39a6b61..da53395 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -26,13 +26,15 @@ static inline void gen_tb_start(void) icount_label = gen_new_label(); count = tcg_temp_local_new_i32(); - tcg_gen_ld_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u32)); + tcg_gen_ld_i32(count, cpu_env, + -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); /* This is a horrid hack to allow fixing up the value later. */ icount_arg = tcg_ctx.gen_opparam_ptr + 1; tcg_gen_subi_i32(count, count, 0xdeadbeef); tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label); - tcg_gen_st16_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u16.low)); + tcg_gen_st16_i32(count, cpu_env, + -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low)); tcg_temp_free_i32(count); } @@ -51,14 +53,14 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns) static inline void gen_io_start(void) { TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } static inline void gen_io_end(void) { TCGv_i32 tmp = tcg_const_i32(0); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index c14a04d..73ed7cf 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -126,12 +126,12 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr); physaddr = (physaddr & TARGET_PAGE_MASK) + addr; - env->mem_io_pc = retaddr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { - cpu_io_recompile(env, retaddr); + cpu->mem_io_pc = retaddr; + if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { + cpu_io_recompile(cpu, retaddr); } - env->mem_io_vaddr = addr; + cpu->mem_io_vaddr = addr; io_mem_read(mr, physaddr, &val, 1 << SHIFT); return val; } @@ -158,7 +158,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; } @@ -240,7 +240,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; } @@ -333,12 +333,12 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr); physaddr = (physaddr & TARGET_PAGE_MASK) + addr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { - cpu_io_recompile(env, retaddr); + if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { + cpu_io_recompile(cpu, retaddr); } - env->mem_io_vaddr = addr; - env->mem_io_pc = retaddr; + cpu->mem_io_vaddr = addr; + cpu->mem_io_pc = retaddr; io_mem_write(mr, physaddr, val, 1 << SHIFT); } @@ -360,7 +360,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, do_unaligned_access(env, addr, 1, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, 1, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].addr_write; } @@ -436,7 +436,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, do_unaligned_access(env, addr, 1, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, 1, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].addr_write; } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 4b4df88..db878c1 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -245,6 +245,13 @@ INLINE flag get_default_nan_mode(float_status *status) void float_raise( int8 flags STATUS_PARAM); /*---------------------------------------------------------------------------- +| If `a' is denormal and we are in flush-to-zero mode then set the +| input-denormal exception and return zero. Otherwise just return the value. +*----------------------------------------------------------------------------*/ +float32 float32_squash_input_denormal(float32 a STATUS_PARAM); +float64 float64_squash_input_denormal(float64 a STATUS_PARAM); + +/*---------------------------------------------------------------------------- | Options to indicate which negations to perform in float*_muladd() | Using these differs from negating an input or output before calling | the muladd function in that this means that a NaN doesn't have its diff --git a/include/hw/boards.h b/include/hw/boards.h index c2096e6..dd2c70d 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -4,8 +4,8 @@ #define HW_BOARDS_H #include "sysemu/blockdev.h" -#include "sysemu/qemumachine.h" #include "hw/qdev.h" +#include "qom/object.h" typedef struct QEMUMachineInitArgs { const QEMUMachine *machine; @@ -50,9 +50,60 @@ struct QEMUMachine { const char *hw_version; }; +#define TYPE_MACHINE_SUFFIX "-machine" int qemu_register_machine(QEMUMachine *m); -QEMUMachine *find_default_machine(void); -extern QEMUMachine *current_machine; +#define TYPE_MACHINE "machine" +#undef MACHINE /* BSD defines it and QEMU does not use it */ +#define MACHINE(obj) \ + OBJECT_CHECK(MachineState, (obj), TYPE_MACHINE) +#define MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MachineClass, (obj), TYPE_MACHINE) +#define MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(MachineClass, (klass), TYPE_MACHINE) + +typedef struct MachineState MachineState; +typedef struct MachineClass MachineClass; + +MachineClass *find_default_machine(void); +extern MachineState *current_machine; + +/** + * MachineClass: + * @qemu_machine: #QEMUMachine + */ +struct MachineClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + QEMUMachine *qemu_machine; +}; + +/** + * MachineState: + */ +struct MachineState { + /*< private >*/ + Object parent_obj; + /*< public >*/ + + char *accel; + bool kernel_irqchip; + int kvm_shadow_mem; + char *kernel; + char *initrd; + char *append; + char *dtb; + char *dumpdtb; + int phandle_start; + char *dt_compatible; + bool dump_guest_core; + bool mem_merge; + bool usb; + char *firmware; + + QEMUMachineInitArgs init_args; +}; #endif diff --git a/include/hw/fw-path-provider.h b/include/hw/fw-path-provider.h new file mode 100644 index 0000000..3018349 --- /dev/null +++ b/include/hw/fw-path-provider.h @@ -0,0 +1,47 @@ +/* + * Firmware patch provider class and helpers definitions. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; under version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef FW_PATH_PROVIDER_H +#define FW_PATH_PROVIDER_H 1 + +#include "qemu-common.h" +#include "qom/object.h" + +#define TYPE_FW_PATH_PROVIDER "fw-path-provider" + +#define FW_PATH_PROVIDER_CLASS(klass) \ + OBJECT_CLASS_CHECK(FWPathProviderClass, (klass), TYPE_FW_PATH_PROVIDER) +#define FW_PATH_PROVIDER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(FWPathProviderClass, (obj), TYPE_FW_PATH_PROVIDER) +#define FW_PATH_PROVIDER(obj) \ + INTERFACE_CHECK(FWPathProvider, (obj), TYPE_FW_PATH_PROVIDER) + +typedef struct FWPathProvider { + Object parent_obj; +} FWPathProvider; + +typedef struct FWPathProviderClass { + InterfaceClass parent_class; + + char *(*get_dev_path)(FWPathProvider *p, BusState *bus, DeviceState *dev); +} FWPathProviderClass; + +char *fw_path_provider_get_dev_path(FWPathProvider *p, BusState *bus, + DeviceState *dev); +char *fw_path_provider_try_get_dev_path(Object *o, BusState *bus, + DeviceState *dev); + +#endif /* FW_PATH_PROVIDER_H */ diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 449fc7c..5fdac1e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -153,8 +153,13 @@ typedef struct sPAPREnvironment { #define H_PP1 (1ULL<<(63-62)) #define H_PP2 (1ULL<<(63-63)) -/* H_SET_MODE flags */ -#define H_SET_MODE_ENDIAN 4 +/* Values for 2nd argument to H_SET_MODE */ +#define H_SET_MODE_RESOURCE_SET_CIABR 1 +#define H_SET_MODE_RESOURCE_SET_DAWR 2 +#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 +#define H_SET_MODE_RESOURCE_LE 4 + +/* Flags for H_SET_MODE_RESOURCE_LE */ #define H_SET_MODE_ENDIAN_BIG 0 #define H_SET_MODE_ENDIAN_LITTLE 1 diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 1ed0691..dbe473c 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -36,6 +36,8 @@ typedef int (*qdev_event)(DeviceState *dev); typedef void (*qdev_resetfn)(DeviceState *dev); typedef void (*DeviceRealize)(DeviceState *dev, Error **errp); typedef void (*DeviceUnrealize)(DeviceState *dev, Error **errp); +typedef void (*BusRealize)(BusState *bus, Error **errp); +typedef void (*BusUnrealize)(BusState *bus, Error **errp); struct VMStateDescription; @@ -174,6 +176,9 @@ struct BusClass { */ char *(*get_fw_dev_path)(DeviceState *dev); void (*reset)(BusState *bus); + BusRealize realize; + BusUnrealize unrealize; + /* maximum devices allowed on the bus, 0: no limit. */ int max_dev; /* number of automatically allocated bus ids (e.g. ide.0) */ @@ -199,6 +204,7 @@ struct BusState { int allow_hotplug; HotplugHandler *hotplug_handler; int max_index; + bool realized; QTAILQ_HEAD(ChildrenHead, BusChild) children; QLIST_ENTRY(BusState) sibling; }; diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 0c0babf..c46e908 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -22,6 +22,7 @@ extern PropertyInfo qdev_prop_bios_chs_trans; extern PropertyInfo qdev_prop_drive; extern PropertyInfo qdev_prop_netdev; extern PropertyInfo qdev_prop_vlan; +extern PropertyInfo qdev_prop_iothread; extern PropertyInfo qdev_prop_pci_devfn; extern PropertyInfo qdev_prop_blocksize; extern PropertyInfo qdev_prop_pci_host_devaddr; @@ -142,6 +143,8 @@ extern PropertyInfo qdev_prop_arraylen; DEFINE_PROP(_n, _s, _f, qdev_prop_vlan, NICPeers) #define DEFINE_PROP_DRIVE(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_drive, BlockDriverState *) +#define DEFINE_PROP_IOTHREAD(_n, _s, _f) \ + DEFINE_PROP(_n, _s, _f, qdev_prop_iothread, IOThread *) #define DEFINE_PROP_MACADDR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ @@ -201,4 +204,15 @@ void qdev_property_add_static(DeviceState *dev, Property *prop, Error **errp); */ void qdev_prop_set_after_realize(DeviceState *dev, const char *name, Error **errp); + +/** + * qdev_prop_allow_set_link_before_realize: + * + * Set the #Error object if an attempt is made to set the link after realize. + * This function should be used as the check() argument to + * object_property_add_link(). + */ +void qdev_prop_allow_set_link_before_realize(Object *obj, const char *name, + Object *val, Error **errp); + #endif diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h index e5fc39d..1adb549 100644 --- a/include/hw/scsi/scsi.h +++ b/include/hw/scsi/scsi.h @@ -31,6 +31,7 @@ typedef struct SCSISense { uint8_t ascq; } SCSISense; +#define SCSI_SENSE_BUF_SIZE_OLD 96 #define SCSI_SENSE_BUF_SIZE 252 struct SCSICommand { diff --git a/include/hw/ssi.h b/include/hw/ssi.h index fdae317..6c13fb2 100644 --- a/include/hw/ssi.h +++ b/include/hw/ssi.h @@ -56,13 +56,12 @@ typedef struct SSISlaveClass { } SSISlaveClass; struct SSISlave { - DeviceState qdev; + DeviceState parent_obj; /* Chip select state */ bool cs; }; -#define SSI_SLAVE_FROM_QDEV(dev) DO_UPCAST(SSISlave, qdev, dev) #define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) extern const VMStateDescription vmstate_ssi_slave; diff --git a/include/hw/virtio/virtio-blk.h b/include/hw/virtio/virtio-blk.h index 41885da..e4c41ff 100644 --- a/include/hw/virtio/virtio-blk.h +++ b/include/hw/virtio/virtio-blk.h @@ -16,6 +16,7 @@ #include "hw/virtio/virtio.h" #include "hw/block/block.h" +#include "sysemu/iothread.h" #define TYPE_VIRTIO_BLK "virtio-blk-device" #define VIRTIO_BLK(obj) \ @@ -106,6 +107,7 @@ struct virtio_scsi_inhdr struct VirtIOBlkConf { BlockConf conf; + IOThread *iothread; char *serial; uint32_t scsi; uint32_t config_wce; @@ -140,13 +142,15 @@ typedef struct VirtIOBlock { DEFINE_BLOCK_CHS_PROPERTIES(_state, _field.conf), \ DEFINE_PROP_STRING("serial", _state, _field.serial), \ DEFINE_PROP_BIT("config-wce", _state, _field.config_wce, 0, true), \ - DEFINE_PROP_BIT("scsi", _state, _field.scsi, 0, true) + DEFINE_PROP_BIT("scsi", _state, _field.scsi, 0, true), \ + DEFINE_PROP_IOTHREAD("x-iothread", _state, _field.iothread) #else #define DEFINE_VIRTIO_BLK_PROPERTIES(_state, _field) \ DEFINE_BLOCK_PROPERTIES(_state, _field.conf), \ DEFINE_BLOCK_CHS_PROPERTIES(_state, _field.conf), \ DEFINE_PROP_STRING("serial", _state, _field.serial), \ - DEFINE_PROP_BIT("config-wce", _state, _field.config_wce, 0, true) + DEFINE_PROP_BIT("config-wce", _state, _field.config_wce, 0, true), \ + DEFINE_PROP_IOTHREAD("x-iothread", _state, _field.iothread) #endif /* __linux__ */ void virtio_blk_set_conf(DeviceState *dev, VirtIOBlkConf *blk); diff --git a/include/hw/virtio/virtio-serial.h b/include/hw/virtio/virtio-serial.h index 1d2040b..4746312 100644 --- a/include/hw/virtio/virtio-serial.h +++ b/include/hw/virtio/virtio-serial.h @@ -81,15 +81,15 @@ typedef struct VirtIOSerialPortClass { bool is_console; /* - * The per-port (or per-app) init function that's called when a + * The per-port (or per-app) realize function that's called when a * new device is found on the bus. */ - int (*init)(VirtIOSerialPort *port); + DeviceRealize realize; /* - * Per-port exit function that's called when a port gets + * Per-port unrealize function that's called when a port gets * hot-unplugged or removed. */ - int (*exit)(VirtIOSerialPort *port); + DeviceUnrealize unrealize; /* Callbacks for guest events */ /* Guest opened/closed device. */ diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h index e181821..9d549fc 100644 --- a/include/hw/xen/xen.h +++ b/include/hw/xen/xen.h @@ -10,7 +10,6 @@ #include "hw/irq.h" #include "qemu-common.h" -#include "sysemu/qemumachine.h" /* xen-machine.c */ enum xen_mode { diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index ded8e23..e7e1705 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -650,6 +650,9 @@ extern const VMStateInfo vmstate_info_bitmap; #define VMSTATE_UINT8_ARRAY(_f, _s, _n) \ VMSTATE_UINT8_ARRAY_V(_f, _s, _n, 0) +#define VMSTATE_UINT8_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint8, uint8_t) + #define VMSTATE_UINT8_2DARRAY(_f, _s, _n1, _n2) \ VMSTATE_UINT8_2DARRAY_V(_f, _s, _n1, _n2, 0) diff --git a/include/qapi/qmp/qerror.h b/include/qapi/qmp/qerror.h index 25193c9..da75abf 100644 --- a/include/qapi/qmp/qerror.h +++ b/include/qapi/qmp/qerror.h @@ -159,7 +159,7 @@ void qerror_report_err(Error *err); ERROR_CLASS_GENERIC_ERROR, "Invalid JSON syntax" #define QERR_KVM_MISSING_CAP \ - ERROR_CLASS_K_V_M_MISSING_CAP, "Using KVM without %s, %s unavailable" + ERROR_CLASS_KVM_MISSING_CAP, "Using KVM without %s, %s unavailable" #define QERR_MIGRATION_ACTIVE \ ERROR_CLASS_GENERIC_ERROR, "There's a migration process in progress" diff --git a/include/qemu-io.h b/include/qemu-io.h index 7e7c07c..5d6006f 100644 --- a/include/qemu-io.h +++ b/include/qemu-io.h @@ -38,6 +38,8 @@ typedef struct cmdinfo { helpfunc_t help; } cmdinfo_t; +extern bool qemuio_misalign; + bool qemuio_command(BlockDriverState *bs, const char *cmd); void qemuio_add_command(const cmdinfo_t *ci); diff --git a/include/qemu/rfifolock.h b/include/qemu/rfifolock.h new file mode 100644 index 0000000..b23ab53 --- /dev/null +++ b/include/qemu/rfifolock.h @@ -0,0 +1,54 @@ +/* + * Recursive FIFO lock + * + * Copyright Red Hat, Inc. 2013 + * + * Authors: + * Stefan Hajnoczi <stefanha@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef QEMU_RFIFOLOCK_H +#define QEMU_RFIFOLOCK_H + +#include "qemu/thread.h" + +/* Recursive FIFO lock + * + * This lock provides more features than a plain mutex: + * + * 1. Fairness - enforces FIFO order. + * 2. Nesting - can be taken recursively. + * 3. Contention callback - optional, called when thread must wait. + * + * The recursive FIFO lock is heavyweight so prefer other synchronization + * primitives if you do not need its features. + */ +typedef struct { + QemuMutex lock; /* protects all fields */ + + /* FIFO order */ + unsigned int head; /* active ticket number */ + unsigned int tail; /* waiting ticket number */ + QemuCond cond; /* used to wait for our ticket number */ + + /* Nesting */ + QemuThread owner_thread; /* thread that currently has ownership */ + unsigned int nesting; /* amount of nesting levels */ + + /* Contention callback */ + void (*cb)(void *); /* called when thread must wait, with ->lock + * held so it may not recursively lock/unlock + */ + void *cb_opaque; +} RFifoLock; + +void rfifolock_init(RFifoLock *r, void (*cb)(void *), void *opaque); +void rfifolock_destroy(RFifoLock *r); +void rfifolock_lock(RFifoLock *r); +void rfifolock_unlock(RFifoLock *r); + +#endif /* QEMU_RFIFOLOCK_H */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 83c9b16..bf8daac 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -30,6 +30,7 @@ typedef struct MemoryListener MemoryListener; typedef struct MemoryMappingList MemoryMappingList; +typedef struct QEMUMachine QEMUMachine; typedef struct NICInfo NICInfo; typedef struct HCIInfo HCIInfo; typedef struct AudioState AudioState; diff --git a/include/qom/cpu.h b/include/qom/cpu.h index d734be8..f99885a 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -21,6 +21,7 @@ #define QEMU_CPU_H #include <signal.h> +#include <setjmp.h> #include "hw/qdev-core.h" #include "exec/hwaddr.h" #include "qemu/queue.h" @@ -68,8 +69,10 @@ struct TranslationBlock; * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an * instantiatable CPU type. + * @parse_features: Callback to parse command line arguments. * @reset: Callback to reset the #CPUState to its initial state. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. + * @has_work: Callback for checking if there is work to do. * @do_interrupt: Callback for interrupt handling. * @do_unassigned_access: Callback for unassigned access handling. * @memory_rw_debug: Callback for GDB memory access. @@ -81,6 +84,7 @@ struct TranslationBlock; * @set_pc: Callback for setting the Program Counter register. * @synchronize_from_tb: Callback for synchronizing state from a TCG * #TranslationBlock. + * @handle_mmu_fault: Callback for handling an MMU fault. * @get_phys_page_debug: Callback for obtaining a physical address. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. @@ -96,9 +100,11 @@ typedef struct CPUClass { /*< public >*/ ObjectClass *(*class_by_name)(const char *cpu_model); + void (*parse_features)(CPUState *cpu, char *str, Error **errp); void (*reset)(CPUState *cpu); int reset_dump_flags; + bool (*has_work)(CPUState *cpu); void (*do_interrupt)(CPUState *cpu); CPUUnassignedAccess do_unassigned_access; int (*memory_rw_debug)(CPUState *cpu, vaddr addr, @@ -113,6 +119,8 @@ typedef struct CPUClass { Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); + int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, + int mmu_index); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); @@ -131,9 +139,37 @@ typedef struct CPUClass { const char *gdb_core_xml_file; } CPUClass; +#ifdef HOST_WORDS_BIGENDIAN +typedef struct icount_decr_u16 { + uint16_t high; + uint16_t low; +} icount_decr_u16; +#else +typedef struct icount_decr_u16 { + uint16_t low; + uint16_t high; +} icount_decr_u16; +#endif + +typedef struct CPUBreakpoint { + vaddr pc; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUBreakpoint) entry; +} CPUBreakpoint; + +typedef struct CPUWatchpoint { + vaddr vaddr; + vaddr len_mask; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUWatchpoint) entry; +} CPUWatchpoint; + struct KVMState; struct kvm_run; +#define TB_JMP_CACHE_BITS 12 +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) + /** * CPUState: * @cpu_index: CPU index (informative). @@ -150,12 +186,20 @@ struct kvm_run; * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this * CPU and return to its top level loop. * @singlestep_enabled: Flags for single-stepping. + * @icount_extra: Instructions until next timer event. + * @icount_decr: Number of cycles left, with interrupt flag in high bit. + * This allows a single read-compare-cbranch-write sequence to test + * for both decrementer underflow and exceptions. + * @can_do_io: Nonzero if memory-mapped IO is safe. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. * @gdb_regs: Additional GDB registers. * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. * @next_cpu: Next CPU sharing TB cache. + * @opaque: User data. + * @mem_io_pc: Host Program Counter at which the memory was accessed. + * @mem_io_vaddr: Target virtual address at which the memory was accessed. * @kvm_fd: vCPU file descriptor for KVM. * * State of one CPU core or thread. @@ -183,20 +227,36 @@ struct CPUState { bool stop; bool stopped; volatile sig_atomic_t exit_request; - volatile sig_atomic_t tcg_exit_req; uint32_t interrupt_request; int singlestep_enabled; + int64_t icount_extra; + sigjmp_buf jmp_env; AddressSpace *as; MemoryListener *tcg_as_listener; void *env_ptr; /* CPUArchState */ struct TranslationBlock *current_tb; + struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; struct GDBRegisterState *gdb_regs; int gdb_num_regs; int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + /* ice debug support */ + QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; + + QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; + CPUWatchpoint *watchpoint_hit; + + void *opaque; + + /* In order to avoid passing too many arguments to the MMIO helpers, + * we store some rarely used information in the CPU context. + */ + uintptr_t mem_io_pc; + vaddr mem_io_vaddr; + int kvm_fd; bool kvm_vcpu_dirty; struct KVMState *kvm_state; @@ -205,6 +265,18 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; /* used by alpha TCG */ uint32_t halted; /* used by alpha, cris, ppc TCG */ + union { + uint32_t u32; + icount_decr_u16 u16; + } icount_decr; + uint32_t can_do_io; + int32_t exception_index; /* used by m68k TCG */ + + /* Note that this is accessed at the start of every TB via a negative + offset from AREG0. Leave this field at the end so as to make the + (absolute value) offset as small as possible. This reduces code + size, especially for hosts without large memory offsets. */ + volatile sig_atomic_t tcg_exit_req; }; QTAILQ_HEAD(CPUTailQ, CPUState); @@ -348,14 +420,31 @@ void cpu_reset(CPUState *cpu); ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); /** - * qemu_cpu_has_work: + * cpu_generic_init: + * @typename: The CPU base type. + * @cpu_model: The model string including optional parameters. + * + * Instantiates a CPU, processes optional parameters and realizes the CPU. + * + * Returns: A #CPUState or %NULL if an error occurred. + */ +CPUState *cpu_generic_init(const char *typename, const char *cpu_model); + +/** + * cpu_has_work: * @cpu: The vCPU to check. * * Checks whether the CPU has work to do. * * Returns: %true if the CPU has work, %false otherwise. */ -bool qemu_cpu_has_work(CPUState *cpu); +static inline bool cpu_has_work(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + g_assert(cc->has_work); + return cc->has_work(cpu); +} /** * qemu_cpu_is_self: @@ -511,6 +600,31 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); +/* Breakpoint/watchpoint flags */ +#define BP_MEM_READ 0x01 +#define BP_MEM_WRITE 0x02 +#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) +#define BP_STOP_BEFORE_ACCESS 0x04 +#define BP_WATCHPOINT_HIT 0x08 +#define BP_GDB 0x10 +#define BP_CPU 0x20 + +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, + CPUBreakpoint **breakpoint); +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); +void cpu_breakpoint_remove_all(CPUState *cpu, int mask); + +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + int flags, CPUWatchpoint **watchpoint); +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags); +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); +void cpu_watchpoint_remove_all(CPUState *cpu, int mask); + +void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + #ifdef CONFIG_SOFTMMU extern const struct VMStateDescription vmstate_cpu_common; #else diff --git a/include/qom/object.h b/include/qom/object.h index 9c7c361..a641dcd 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -974,6 +974,14 @@ const char *object_property_get_type(Object *obj, const char *name, Object *object_get_root(void); /** + * object_get_canonical_path_component: + * + * Returns: The final component in the object's canonical path. The canonical + * path is the path within the composition tree starting from the root. + */ +gchar *object_get_canonical_path_component(Object *obj); + +/** * object_get_canonical_path: * * Returns: The canonical path for a object. This is the path within the @@ -1059,12 +1067,29 @@ Object *object_resolve_path_component(Object *parent, const gchar *part); void object_property_add_child(Object *obj, const char *name, Object *child, Error **errp); +typedef enum { + /* Unref the link pointer when the property is deleted */ + OBJ_PROP_LINK_UNREF_ON_RELEASE = 0x1, +} ObjectPropertyLinkFlags; + +/** + * object_property_allow_set_link: + * + * The default implementation of the object_property_add_link() check() + * callback function. It allows the link property to be set and never returns + * an error. + */ +void object_property_allow_set_link(Object *, const char *, + Object *, Error **); + /** * object_property_add_link: * @obj: the object to add a property to * @name: the name of the property * @type: the qobj type of the link * @child: a pointer to where the link object reference is stored + * @check: callback to veto setting or NULL if the property is read-only + * @flags: additional options for the link * @errp: if an error occurs, a pointer to an area to store the area * * Links establish relationships between objects. Links are unidirectional @@ -1073,13 +1098,23 @@ void object_property_add_child(Object *obj, const char *name, * * Links form the graph in the object model. * + * The <code>@check()</code> callback is invoked when + * object_property_set_link() is called and can raise an error to prevent the + * link being set. If <code>@check</code> is NULL, the property is read-only + * and cannot be set. + * * Ownership of the pointer that @child points to is transferred to the * link property. The reference count for <code>*@child</code> is * managed by the property from after the function returns till the - * property is deleted with object_property_del(). + * property is deleted with object_property_del(). If the + * <code>@flags</code> <code>OBJ_PROP_LINK_UNREF_ON_RELEASE</code> bit is set, + * the reference count is decremented when the property is deleted. */ void object_property_add_link(Object *obj, const char *name, const char *type, Object **child, + void (*check)(Object *obj, const char *name, + Object *val, Error **errp), + ObjectPropertyLinkFlags flags, Error **errp); /** diff --git a/include/sysemu/iothread.h b/include/sysemu/iothread.h new file mode 100644 index 0000000..a32214a --- /dev/null +++ b/include/sysemu/iothread.h @@ -0,0 +1,30 @@ +/* + * Event loop thread + * + * Copyright Red Hat Inc., 2013 + * + * Authors: + * Stefan Hajnoczi <stefanha@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef IOTHREAD_H +#define IOTHREAD_H + +#include "block/aio.h" + +#define TYPE_IOTHREAD "iothread" + +typedef struct IOThread IOThread; + +#define IOTHREAD(obj) \ + OBJECT_CHECK(IOThread, obj, TYPE_IOTHREAD) + +IOThread *iothread_find(const char *id); +char *iothread_get_id(IOThread *iothread); +AioContext *iothread_get_aio_context(IOThread *iothread); + +#endif /* IOTHREAD_H */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index ed01998..0bee1e8 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -18,7 +18,6 @@ #include "config-host.h" #include "qemu/queue.h" #include "qom/cpu.h" -#include "sysemu/qemumachine.h" #ifdef CONFIG_KVM #include <linux/kvm.h> diff --git a/include/sysemu/qemumachine.h b/include/sysemu/qemumachine.h deleted file mode 100644 index 4cefd56..0000000 --- a/include/sysemu/qemumachine.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * QEMU Machine typedef - * - * Copyright Alexander Graf <agraf@suse.de> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#ifndef QEMUMACHINE_H -#define QEMUMACHINE_H - -typedef struct QEMUMachine QEMUMachine; - -#endif /* !QEMUMACHINE_H */ diff --git a/include/sysemu/qtest.h b/include/sysemu/qtest.h index e62281d..224131f 100644 --- a/include/sysemu/qtest.h +++ b/include/sysemu/qtest.h @@ -16,7 +16,6 @@ #include "qemu-common.h" #include "qapi/error.h" -#include "sysemu/qemumachine.h" extern bool qtest_allowed; diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index 90f192a..ba5c7f8 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -104,7 +104,7 @@ extern int autostart; typedef enum { VGA_NONE, VGA_STD, VGA_CIRRUS, VGA_VMWARE, VGA_XENFB, VGA_QXL, - VGA_TCX, VGA_CG3, + VGA_TCX, VGA_CG3, VGA_DEVICE } VGAInterfaceType; extern int vga_interface_type; @@ -193,7 +193,7 @@ void rtc_change_mon_event(struct tm *tm); void add_boot_device_path(int32_t bootindex, DeviceState *dev, const char *suffix); -char *get_boot_devices_list(size_t *size); +char *get_boot_devices_list(size_t *size, bool ignore_suffixes); DeviceState *get_boot_device(uint32_t position); diff --git a/include/ui/console.h b/include/ui/console.h index 08a38ea..8a86617 100644 --- a/include/ui/console.h +++ b/include/ui/console.h @@ -345,6 +345,6 @@ int index_from_key(const char *key); /* gtk.c */ void early_gtk_display_init(void); -void gtk_display_init(DisplayState *ds, bool full_screen); +void gtk_display_init(DisplayState *ds, bool full_screen, bool grab_on_hover); #endif diff --git a/iothread.c b/iothread.c new file mode 100644 index 0000000..cb5986b --- /dev/null +++ b/iothread.c @@ -0,0 +1,178 @@ +/* + * Event loop thread + * + * Copyright Red Hat Inc., 2013 + * + * Authors: + * Stefan Hajnoczi <stefanha@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qom/object.h" +#include "qom/object_interfaces.h" +#include "qemu/module.h" +#include "qemu/thread.h" +#include "block/aio.h" +#include "sysemu/iothread.h" +#include "qmp-commands.h" + +#define IOTHREADS_PATH "/objects" + +typedef ObjectClass IOThreadClass; +struct IOThread { + Object parent_obj; + + QemuThread thread; + AioContext *ctx; + QemuMutex init_done_lock; + QemuCond init_done_cond; /* is thread initialization done? */ + bool stopping; + int thread_id; +}; + +#define IOTHREAD_GET_CLASS(obj) \ + OBJECT_GET_CLASS(IOThreadClass, obj, TYPE_IOTHREAD) +#define IOTHREAD_CLASS(klass) \ + OBJECT_CLASS_CHECK(IOThreadClass, klass, TYPE_IOTHREAD) + +static void *iothread_run(void *opaque) +{ + IOThread *iothread = opaque; + + qemu_mutex_lock(&iothread->init_done_lock); + iothread->thread_id = qemu_get_thread_id(); + qemu_cond_signal(&iothread->init_done_cond); + qemu_mutex_unlock(&iothread->init_done_lock); + + while (!iothread->stopping) { + aio_context_acquire(iothread->ctx); + while (!iothread->stopping && aio_poll(iothread->ctx, true)) { + /* Progress was made, keep going */ + } + aio_context_release(iothread->ctx); + } + return NULL; +} + +static void iothread_instance_finalize(Object *obj) +{ + IOThread *iothread = IOTHREAD(obj); + + iothread->stopping = true; + aio_notify(iothread->ctx); + qemu_thread_join(&iothread->thread); + qemu_cond_destroy(&iothread->init_done_cond); + qemu_mutex_destroy(&iothread->init_done_lock); + aio_context_unref(iothread->ctx); +} + +static void iothread_complete(UserCreatable *obj, Error **errp) +{ + IOThread *iothread = IOTHREAD(obj); + + iothread->stopping = false; + iothread->ctx = aio_context_new(); + iothread->thread_id = -1; + + qemu_mutex_init(&iothread->init_done_lock); + qemu_cond_init(&iothread->init_done_cond); + + /* This assumes we are called from a thread with useful CPU affinity for us + * to inherit. + */ + qemu_thread_create(&iothread->thread, "iothread", iothread_run, + iothread, QEMU_THREAD_JOINABLE); + + /* Wait for initialization to complete */ + qemu_mutex_lock(&iothread->init_done_lock); + while (iothread->thread_id == -1) { + qemu_cond_wait(&iothread->init_done_cond, + &iothread->init_done_lock); + } + qemu_mutex_unlock(&iothread->init_done_lock); +} + +static void iothread_class_init(ObjectClass *klass, void *class_data) +{ + UserCreatableClass *ucc = USER_CREATABLE_CLASS(klass); + ucc->complete = iothread_complete; +} + +static const TypeInfo iothread_info = { + .name = TYPE_IOTHREAD, + .parent = TYPE_OBJECT, + .class_init = iothread_class_init, + .instance_size = sizeof(IOThread), + .instance_finalize = iothread_instance_finalize, + .interfaces = (InterfaceInfo[]) { + {TYPE_USER_CREATABLE}, + {} + }, +}; + +static void iothread_register_types(void) +{ + type_register_static(&iothread_info); +} + +type_init(iothread_register_types) + +IOThread *iothread_find(const char *id) +{ + Object *container = container_get(object_get_root(), IOTHREADS_PATH); + Object *child; + + child = object_property_get_link(container, id, NULL); + if (!child) { + return NULL; + } + return (IOThread *)object_dynamic_cast(child, TYPE_IOTHREAD); +} + +char *iothread_get_id(IOThread *iothread) +{ + return object_get_canonical_path_component(OBJECT(iothread)); +} + +AioContext *iothread_get_aio_context(IOThread *iothread) +{ + return iothread->ctx; +} + +static int query_one_iothread(Object *object, void *opaque) +{ + IOThreadInfoList ***prev = opaque; + IOThreadInfoList *elem; + IOThreadInfo *info; + IOThread *iothread; + + iothread = (IOThread *)object_dynamic_cast(object, TYPE_IOTHREAD); + if (!iothread) { + return 0; + } + + info = g_new0(IOThreadInfo, 1); + info->id = iothread_get_id(iothread); + info->thread_id = iothread->thread_id; + + elem = g_new0(IOThreadInfoList, 1); + elem->value = info; + elem->next = NULL; + + **prev = elem; + *prev = &elem->next; + return 0; +} + +IOThreadInfoList *qmp_query_iothreads(Error **errp) +{ + IOThreadInfoList *head = NULL; + IOThreadInfoList **prev = &head; + Object *container = container_get(object_get_root(), IOTHREADS_PATH); + + object_child_foreach(container, query_one_iothread, &prev); + return head; +} @@ -1423,11 +1423,10 @@ int kvm_init(QEMUMachine *machine) nc->name, nc->num, soft_vcpus_limit); if (nc->num > hard_vcpus_limit) { - ret = -EINVAL; fprintf(stderr, "Number of %s cpus requested (%d) exceeds " "the maximum cpus supported by KVM (%d)\n", nc->name, nc->num, hard_vcpus_limit); - goto err; + exit(1); } } nc++; @@ -14,7 +14,6 @@ #include "hw/hw.h" #include "cpu.h" #include "sysemu/kvm.h" -#include "sysemu/qemumachine.h" #ifndef CONFIG_USER_ONLY #include "hw/pci/msi.h" diff --git a/linux-user/alpha/syscall.h b/linux-user/alpha/syscall.h index 15a0100..ed13d9a 100644 --- a/linux-user/alpha/syscall.h +++ b/linux-user/alpha/syscall.h @@ -39,6 +39,7 @@ struct target_pt_regs { }; #define UNAME_MACHINE "alpha" +#define UNAME_MINIMUM_RELEASE "2.6.32" #undef TARGET_EDEADLK #define TARGET_EDEADLK 11 diff --git a/linux-user/arm/syscall.h b/linux-user/arm/syscall.h index 73f2931..ce2c2a8 100644 --- a/linux-user/arm/syscall.h +++ b/linux-user/arm/syscall.h @@ -40,5 +40,6 @@ struct target_pt_regs { #else #define UNAME_MACHINE "armv5tel" #endif +#define UNAME_MINIMUM_RELEASE "2.6.32" #define TARGET_CLONE_BACKWARDS diff --git a/linux-user/cris/syscall.h b/linux-user/cris/syscall.h index 832ee64..f5783c0 100644 --- a/linux-user/cris/syscall.h +++ b/linux-user/cris/syscall.h @@ -1,8 +1,8 @@ #ifndef CRIS_SYSCALL_H #define CRIS_SYSCALL_H 1 - #define UNAME_MACHINE "cris" +#define UNAME_MINIMUM_RELEASE "2.6.32" /* pt_regs not only specifices the format in the user-struct during * ptrace but is also the frame format used in the kernel prologue/epilogues diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c0687e3..99a2c58 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -352,6 +352,9 @@ enum ARM_HWCAP_ARM_VFPv3D16 = 1 << 13, }; +#ifndef TARGET_AARCH64 +/* The commpage only exists for 32 bit kernels */ + #define TARGET_HAS_VALIDATE_GUEST_SPACE /* Return 1 if the proposed guest space is suitable for the guest. * Return 0 if the proposed guest space isn't suitable, but another @@ -411,7 +414,7 @@ static int validate_guest_space(unsigned long guest_base, return 1; /* All good */ } - +#endif #define ELF_HWCAP get_elf_hwcap() @@ -2621,7 +2624,8 @@ static int write_note(struct memelfnote *men, int fd) static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env) { - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; struct elf_thread_status *ets; ets = g_malloc0(sizeof (*ets)); @@ -2650,8 +2654,8 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu = NULL; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; int i; info->notes = g_malloc0(NUMNOTES * sizeof (struct memelfnote)); @@ -2775,7 +2779,8 @@ static int write_note_info(struct elf_note_info *info, int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const TaskState *ts = (const TaskState *)env->opaque; + const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + const TaskState *ts = (const TaskState *)cpu->opaque; struct vm_area_struct *vma = NULL; char corefile[PATH_MAX]; struct elf_note_info info; diff --git a/linux-user/i386/syscall.h b/linux-user/i386/syscall.h index 12b8c3b..9bfc1ad 100644 --- a/linux-user/i386/syscall.h +++ b/linux-user/i386/syscall.h @@ -144,5 +144,6 @@ struct target_vm86plus_struct { }; #define UNAME_MACHINE "i686" +#define UNAME_MINIMUM_RELEASE "2.6.32" #define TARGET_CLONE_BACKWARDS diff --git a/linux-user/linuxload.c b/linux-user/linuxload.c index f2997c2..506e837 100644 --- a/linux-user/linuxload.c +++ b/linux-user/linuxload.c @@ -89,8 +89,7 @@ static int prepare_binprm(struct linux_binprm *bprm) abi_ulong loader_build_argptr(int envc, int argc, abi_ulong sp, abi_ulong stringp, int push_ptr) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + TaskState *ts = (TaskState *)thread_cpu->opaque; int n = sizeof(abi_ulong); abi_ulong envp; abi_ulong argv; diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c index d5926ee..1994e40 100644 --- a/linux-user/m68k-sim.c +++ b/linux-user/m68k-sim.c @@ -98,6 +98,7 @@ static int translate_openflags(int flags) #define ARG(x) tswap32(args[x]) void do_m68k_simcall(CPUM68KState *env, int nr) { + M68kCPU *cpu = m68k_env_get_cpu(env); uint32_t *args; args = (uint32_t *)(unsigned long)(env->aregs[7] + 4); @@ -165,6 +166,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr) check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2))); break; default: - cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr); + cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr); } } diff --git a/linux-user/m68k/syscall.h b/linux-user/m68k/syscall.h index 2618793..889eaf7 100644 --- a/linux-user/m68k/syscall.h +++ b/linux-user/m68k/syscall.h @@ -15,7 +15,7 @@ struct target_pt_regs { uint16_t __fill; }; - #define UNAME_MACHINE "m68k" +#define UNAME_MINIMUM_RELEASE "2.6.32" void do_m68k_simcall(CPUM68KState *, int); diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h index cad9c90..bb4d3fa 100644 --- a/linux-user/m68k/target_cpu.h +++ b/linux-user/m68k/target_cpu.h @@ -31,7 +31,9 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp) static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; + ts->tp_value = newtls; } diff --git a/linux-user/main.c b/linux-user/main.c index be9491b..af924dc 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -685,7 +685,7 @@ void cpu_loop(CPUARMState *env) switch(trapnr) { case EXCP_UDEF: { - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; uint32_t opcode; int rc; @@ -1577,11 +1577,11 @@ void cpu_loop(CPUPPCState *env) /* Just go on */ break; case POWERPC_EXCP_CRITICAL: /* Critical input */ - cpu_abort(env, "Critical interrupt while in user mode. " + cpu_abort(cs, "Critical interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_MCHECK: /* Machine check exception */ - cpu_abort(env, "Machine check exception while in user mode. " + cpu_abort(cs, "Machine check exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DSI: /* Data storage exception */ @@ -1645,7 +1645,7 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_EXTERNAL: /* External input */ - cpu_abort(env, "External interrupt while in user mode. " + cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ALIGN: /* Alignment exception */ @@ -1739,11 +1739,11 @@ void cpu_loop(CPUPPCState *env) } break; case POWERPC_EXCP_TRAP: - cpu_abort(env, "Tried to call a TRAP\n"); + cpu_abort(cs, "Tried to call a TRAP\n"); break; default: /* Should not happen ! */ - cpu_abort(env, "Unknown program exception (%02x)\n", + cpu_abort(cs, "Unknown program exception (%02x)\n", env->error_code); break; } @@ -1759,7 +1759,7 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_SYSCALL: /* System call exception */ - cpu_abort(env, "Syscall exception while in user mode. " + cpu_abort(cs, "Syscall exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ @@ -1771,23 +1771,23 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_DECR: /* Decrementer exception */ - cpu_abort(env, "Decrementer interrupt while in user mode. " + cpu_abort(cs, "Decrementer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ - cpu_abort(env, "Fix interval timer interrupt while in user mode. " + cpu_abort(cs, "Fix interval timer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ - cpu_abort(env, "Watchdog timer interrupt while in user mode. " + cpu_abort(cs, "Watchdog timer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DTLB: /* Data TLB error */ - cpu_abort(env, "Data TLB exception while in user mode. " + cpu_abort(cs, "Data TLB exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ITLB: /* Instruction TLB error */ - cpu_abort(env, "Instruction TLB exception while in user mode. " + cpu_abort(cs, "Instruction TLB exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ @@ -1799,37 +1799,37 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ - cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); + cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); break; case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ - cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); + cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); break; case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ - cpu_abort(env, "Performance monitor exception not handled\n"); + cpu_abort(cs, "Performance monitor exception not handled\n"); break; case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ - cpu_abort(env, "Doorbell interrupt while in user mode. " + cpu_abort(cs, "Doorbell interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ - cpu_abort(env, "Doorbell critical interrupt while in user mode. " + cpu_abort(cs, "Doorbell critical interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_RESET: /* System reset exception */ - cpu_abort(env, "Reset interrupt while in user mode. " + cpu_abort(cs, "Reset interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DSEG: /* Data segment exception */ - cpu_abort(env, "Data segment exception while in user mode. " + cpu_abort(cs, "Data segment exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ISEG: /* Instruction segment exception */ - cpu_abort(env, "Instruction segment exception " + cpu_abort(cs, "Instruction segment exception " "while in user mode. Aborting\n"); break; /* PowerPC 64 with hypervisor mode support */ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ - cpu_abort(env, "Hypervisor decrementer interrupt " + cpu_abort(cs, "Hypervisor decrementer interrupt " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_TRACE: /* Trace exception */ @@ -1839,19 +1839,19 @@ void cpu_loop(CPUPPCState *env) break; /* PowerPC 64 with hypervisor mode support */ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ - cpu_abort(env, "Hypervisor data storage exception " + cpu_abort(cs, "Hypervisor data storage exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ - cpu_abort(env, "Hypervisor instruction storage exception " + cpu_abort(cs, "Hypervisor instruction storage exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ - cpu_abort(env, "Hypervisor data segment exception " + cpu_abort(cs, "Hypervisor data segment exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ - cpu_abort(env, "Hypervisor instruction segment exception " + cpu_abort(cs, "Hypervisor instruction segment exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_VPU: /* Vector unavailable exception */ @@ -1863,58 +1863,58 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ - cpu_abort(env, "Programmable interval timer interrupt " + cpu_abort(cs, "Programmable interval timer interrupt " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_IO: /* IO error exception */ - cpu_abort(env, "IO error exception while in user mode. " + cpu_abort(cs, "IO error exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_RUNM: /* Run mode exception */ - cpu_abort(env, "Run mode exception while in user mode. " + cpu_abort(cs, "Run mode exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_EMUL: /* Emulation trap exception */ - cpu_abort(env, "Emulation trap exception not handled\n"); + cpu_abort(cs, "Emulation trap exception not handled\n"); break; case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ - cpu_abort(env, "Instruction fetch TLB exception " + cpu_abort(cs, "Instruction fetch TLB exception " "while in user-mode. Aborting"); break; case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ - cpu_abort(env, "Data load TLB exception while in user-mode. " + cpu_abort(cs, "Data load TLB exception while in user-mode. " "Aborting"); break; case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ - cpu_abort(env, "Data store TLB exception while in user-mode. " + cpu_abort(cs, "Data store TLB exception while in user-mode. " "Aborting"); break; case POWERPC_EXCP_FPA: /* Floating-point assist exception */ - cpu_abort(env, "Floating-point assist exception not handled\n"); + cpu_abort(cs, "Floating-point assist exception not handled\n"); break; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ - cpu_abort(env, "Instruction address breakpoint exception " + cpu_abort(cs, "Instruction address breakpoint exception " "not handled\n"); break; case POWERPC_EXCP_SMI: /* System management interrupt */ - cpu_abort(env, "System management interrupt while in user mode. " + cpu_abort(cs, "System management interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_THERM: /* Thermal interrupt */ - cpu_abort(env, "Thermal interrupt interrupt while in user mode. " + cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ - cpu_abort(env, "Performance monitor exception not handled\n"); + cpu_abort(cs, "Performance monitor exception not handled\n"); break; case POWERPC_EXCP_VPUA: /* Vector assist exception */ - cpu_abort(env, "Vector assist exception not handled\n"); + cpu_abort(cs, "Vector assist exception not handled\n"); break; case POWERPC_EXCP_SOFTP: /* Soft patch exception */ - cpu_abort(env, "Soft patch exception not handled\n"); + cpu_abort(cs, "Soft patch exception not handled\n"); break; case POWERPC_EXCP_MAINT: /* Maintenance exception */ - cpu_abort(env, "Maintenance exception while in user mode. " + cpu_abort(cs, "Maintenance exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_STOP: /* stop translation */ @@ -1970,7 +1970,7 @@ void cpu_loop(CPUPPCState *env) /* just indicate that signals should be handled asap */ break; default: - cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); + cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr); break; } process_pending_signals(env); @@ -2400,6 +2400,10 @@ static int do_break(CPUMIPSState *env, target_siginfo_t *info, ret = 0; break; default: + info->si_signo = TARGET_SIGTRAP; + info->si_errno = 0; + queue_signal(env, info->si_signo, &*info); + ret = 0; break; } @@ -2961,7 +2965,7 @@ void cpu_loop(CPUM68KState *env) int trapnr; unsigned int n; target_siginfo_t info; - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; for(;;) { trapnr = cpu_m68k_exec(env); @@ -3431,28 +3435,30 @@ void init_task_state(TaskState *ts) CPUArchState *cpu_copy(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUArchState *new_env = cpu_init(cpu_model); + CPUState *new_cpu = ENV_GET_CPU(new_env); #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; CPUWatchpoint *wp; #endif /* Reset non arch specific state */ - cpu_reset(ENV_GET_CPU(new_env)); + cpu_reset(new_cpu); memcpy(new_env, env, sizeof(CPUArchState)); /* Clone all break/watchpoints. Note: Once we support ptrace with hw-debug register access, make sure BP_CPU break/watchpoints are handled correctly on clone. */ - QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->breakpoints); + QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { - cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); } - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { - cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { + cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1, wp->flags, NULL); } #endif @@ -3997,7 +4003,7 @@ int main(int argc, char **argv, char **envp) /* build Task State */ ts->info = info; ts->bprm = &bprm; - env->opaque = ts; + cpu->opaque = ts; task_settid(ts); execfd = qemu_getauxval(AT_EXECFD); diff --git a/linux-user/microblaze/syscall.h b/linux-user/microblaze/syscall.h index d550989..5b5f6b4 100644 --- a/linux-user/microblaze/syscall.h +++ b/linux-user/microblaze/syscall.h @@ -1,8 +1,8 @@ #ifndef MICROBLAZE_SYSCALLS_H #define MICROBLAZE_SYSCALLS_H 1 - #define UNAME_MACHINE "microblaze" +#define UNAME_MINIMUM_RELEASE "2.6.32" /* We use microblaze_reg_t to keep things similar to the kernel sources. */ typedef uint32_t microblaze_reg_t; diff --git a/linux-user/mips/syscall.h b/linux-user/mips/syscall.h index 9d437d9..5bc5696 100644 --- a/linux-user/mips/syscall.h +++ b/linux-user/mips/syscall.h @@ -225,5 +225,6 @@ struct target_pt_regs { #define TARGET_QEMU_ESIGRETURN 255 #define UNAME_MACHINE "mips" +#define UNAME_MINIMUM_RELEASE "2.6.32" #define TARGET_CLONE_BACKWARDS diff --git a/linux-user/mips64/syscall.h b/linux-user/mips64/syscall.h index 1710f76..a7f5a58 100644 --- a/linux-user/mips64/syscall.h +++ b/linux-user/mips64/syscall.h @@ -222,5 +222,6 @@ struct target_pt_regs { #define TARGET_QEMU_ESIGRETURN 255 #define UNAME_MACHINE "mips64" +#define UNAME_MINIMUM_RELEASE "2.6.32" #define TARGET_CLONE_BACKWARDS diff --git a/linux-user/openrisc/syscall.h b/linux-user/openrisc/syscall.h index bdbb577..c3b36da 100644 --- a/linux-user/openrisc/syscall.h +++ b/linux-user/openrisc/syscall.h @@ -22,3 +22,4 @@ struct target_pt_regs { }; #define UNAME_MACHINE "openrisc" +#define UNAME_MINIMUM_RELEASE "2.6.32" diff --git a/linux-user/ppc/syscall.h b/linux-user/ppc/syscall.h index ba36acb..6514c63 100644 --- a/linux-user/ppc/syscall.h +++ b/linux-user/ppc/syscall.h @@ -62,5 +62,6 @@ struct target_revectored_struct { #else #define UNAME_MACHINE "ppc" #endif +#define UNAME_MINIMUM_RELEASE "2.6.32" #define TARGET_CLONE_BACKWARDS diff --git a/linux-user/qemu.h b/linux-user/qemu.h index c2f74f3..36d4a73 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -126,6 +126,7 @@ typedef struct TaskState { #endif uint32_t stack_base; int used; /* non zero if used */ + bool sigsegv_blocked; /* SIGSEGV blocked by guest */ struct image_info *info; struct linux_binprm *bprm; @@ -235,6 +236,7 @@ int host_to_target_signal(int sig); long do_sigreturn(CPUArchState *env); long do_rt_sigreturn(CPUArchState *env); abi_long do_sigaltstack(abi_ulong uss_addr, abi_ulong uoss_addr, abi_ulong sp); +int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset); #ifdef TARGET_I386 /* vm86.c */ diff --git a/linux-user/s390x/syscall.h b/linux-user/s390x/syscall.h index e5ce30b..aaad512 100644 --- a/linux-user/s390x/syscall.h +++ b/linux-user/s390x/syscall.h @@ -21,5 +21,6 @@ struct target_pt_regs { }; #define UNAME_MACHINE "s390x" +#define UNAME_MINIMUM_RELEASE "2.6.32" #define TARGET_CLONE_BACKWARDS2 diff --git a/linux-user/sh4/syscall.h b/linux-user/sh4/syscall.h index 014bf58..ccd2216 100644 --- a/linux-user/sh4/syscall.h +++ b/linux-user/sh4/syscall.h @@ -10,3 +10,4 @@ struct target_pt_regs { }; #define UNAME_MACHINE "sh4" +#define UNAME_MINIMUM_RELEASE "2.6.32" diff --git a/linux-user/signal.c b/linux-user/signal.c index 04638e2..e5fb933 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -197,6 +197,55 @@ void target_to_host_old_sigset(sigset_t *sigset, target_to_host_sigset(sigset, &d); } +/* Wrapper for sigprocmask function + * Emulates a sigprocmask in a safe way for the guest. Note that set and oldset + * are host signal set, not guest ones. This wraps the sigprocmask host calls + * that should be protected (calls originated from guest) + */ +int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset) +{ + int ret; + sigset_t val; + sigset_t *temp = NULL; + CPUState *cpu = thread_cpu; + TaskState *ts = (TaskState *)cpu->opaque; + bool segv_was_blocked = ts->sigsegv_blocked; + + if (set) { + bool has_sigsegv = sigismember(set, SIGSEGV); + val = *set; + temp = &val; + + sigdelset(temp, SIGSEGV); + + switch (how) { + case SIG_BLOCK: + if (has_sigsegv) { + ts->sigsegv_blocked = true; + } + break; + case SIG_UNBLOCK: + if (has_sigsegv) { + ts->sigsegv_blocked = false; + } + break; + case SIG_SETMASK: + ts->sigsegv_blocked = has_sigsegv; + break; + default: + g_assert_not_reached(); + } + } + + ret = sigprocmask(how, temp, oldset); + + if (oldset && segv_was_blocked) { + sigaddset(oldset, SIGSEGV); + } + + return ret; +} + /* siginfo conversion */ static inline void host_to_target_siginfo_noswap(target_siginfo_t *tinfo, @@ -370,7 +419,8 @@ void signal_init(void) static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct sigqueue *q = ts->first_free; if (!q) return NULL; @@ -380,7 +430,9 @@ static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; + q->next = ts->first_free; ts->first_free = q; } @@ -388,8 +440,9 @@ static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) /* abort execution with signal */ static void QEMU_NORETURN force_sig(int target_sig) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = thread_cpu; + CPUArchState *env = cpu->env_ptr; + TaskState *ts = (TaskState *)cpu->opaque; int host_sig, core_dumped = 0; struct sigaction act; host_sig = target_to_host_signal(target_sig); @@ -440,7 +493,8 @@ static void QEMU_NORETURN force_sig(int target_sig) as possible */ int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct emulated_sigtable *k; struct sigqueue *q, **pq; abi_ulong handler; @@ -453,6 +507,19 @@ int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info) k = &ts->sigtab[sig - 1]; queue = gdb_queuesig (); handler = sigact_table[sig - 1]._sa_handler; + + if (ts->sigsegv_blocked && sig == TARGET_SIGSEGV) { + /* Guest has blocked SIGSEGV but we got one anyway. Assume this + * is a forced SIGSEGV (ie one the kernel handles via force_sig_info + * because it got a real MMU fault). A blocked SIGSEGV in that + * situation is treated as if using the default handler. This is + * not correct if some other process has randomly sent us a SIGSEGV + * via kill(), but that is not easy to distinguish at this point, + * so we assume it doesn't happen. + */ + handler = TARGET_SIG_DFL; + } + if (!queue && handler == TARGET_SIG_DFL) { if (sig == TARGET_SIGTSTP || sig == TARGET_SIGTTIN || sig == TARGET_SIGTTOU) { kill(getpid(),SIGSTOP); @@ -774,8 +841,9 @@ static int setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr) { - int err = 0; - uint16_t magic; + CPUState *cs = CPU(x86_env_get_cpu(env)); + int err = 0; + uint16_t magic; /* already locked in setup_frame() */ err |= __put_user(env->segs[R_GS].selector, (unsigned int *)&sc->gs); @@ -790,7 +858,7 @@ setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, err |= __put_user(env->regs[R_EDX], &sc->edx); err |= __put_user(env->regs[R_ECX], &sc->ecx); err |= __put_user(env->regs[R_EAX], &sc->eax); - err |= __put_user(env->exception_index, &sc->trapno); + err |= __put_user(cs->exception_index, &sc->trapno); err |= __put_user(env->error_code, &sc->err); err |= __put_user(env->eip, &sc->eip); err |= __put_user(env->segs[R_CS].selector, (unsigned int *)&sc->cs); @@ -1050,7 +1118,7 @@ long do_sigreturn(CPUX86State *env) } target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); /* restore registers */ if (restore_sigcontext(env, &frame->sc, &eax)) @@ -1075,7 +1143,7 @@ long do_rt_sigreturn(CPUX86State *env) if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) goto badframe; target_to_host_sigset(&set, &frame->uc.tuc_sigmask); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); if (restore_sigcontext(env, &frame->uc.tuc_mcontext, &eax)) goto badframe; @@ -1214,7 +1282,7 @@ static int target_restore_sigframe(CPUARMState *env, uint64_t pstate; target_to_host_sigset(&set, &sf->uc.tuc_sigmask); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); for (i = 0; i < 31; i++) { __get_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]); @@ -1233,8 +1301,14 @@ static int target_restore_sigframe(CPUARMState *env, return 1; } - for (i = 0; i < 32 * 2; i++) { - __get_user(env->vfp.regs[i], &aux->fpsimd.vregs[i]); + for (i = 0; i < 32; i++) { +#ifdef TARGET_WORDS_BIGENDIAN + __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2 + 1]); + __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2]); +#else + __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2]); + __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2 + 1]); +#endif } __get_user(fpsr, &aux->fpsimd.fpsr); vfp_set_fpsr(env, fpsr); @@ -1267,7 +1341,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, CPUARMState *env) { struct target_rt_sigframe *frame; - abi_ulong frame_addr; + abi_ulong frame_addr, return_addr; frame_addr = get_sigframe(ka, env); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { @@ -1284,15 +1358,19 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, __put_user(target_sigaltstack_used.ss_size, &frame->uc.tuc_stack.ss_size); target_setup_sigframe(frame, env, set); - /* mov x8,#__NR_rt_sigreturn; svc #0 */ - __put_user(0xd2801168, &frame->tramp[0]); - __put_user(0xd4000001, &frame->tramp[1]); + if (ka->sa_flags & TARGET_SA_RESTORER) { + return_addr = ka->sa_restorer; + } else { + /* mov x8,#__NR_rt_sigreturn; svc #0 */ + __put_user(0xd2801168, &frame->tramp[0]); + __put_user(0xd4000001, &frame->tramp[1]); + return_addr = frame_addr + offsetof(struct target_rt_sigframe, tramp); + } env->xregs[0] = usig; env->xregs[31] = frame_addr; env->xregs[29] = env->xregs[31] + offsetof(struct target_rt_sigframe, fp); env->pc = ka->_sa_handler; - env->xregs[30] = env->xregs[31] + - offsetof(struct target_rt_sigframe, tramp); + env->xregs[30] = return_addr; if (info) { if (copy_siginfo_to_user(&frame->info, info)) { goto give_sigsegv; @@ -1324,7 +1402,7 @@ static void setup_frame(int sig, struct target_sigaction *ka, long do_rt_sigreturn(CPUARMState *env) { - struct target_rt_sigframe *frame; + struct target_rt_sigframe *frame = NULL; abi_ulong frame_addr = env->xregs[31]; if (frame_addr & 15) { @@ -1845,7 +1923,7 @@ static long do_sigreturn_v1(CPUARMState *env) } target_to_host_sigset_internal(&host_set, &set); - sigprocmask(SIG_SETMASK, &host_set, NULL); + do_sigprocmask(SIG_SETMASK, &host_set, NULL); if (restore_sigcontext(env, &frame->sc)) goto badframe; @@ -1926,7 +2004,7 @@ static int do_sigframe_return_v2(CPUARMState *env, target_ulong frame_addr, abi_ulong *regspace; target_to_host_sigset(&host_set, &uc->tuc_sigmask); - sigprocmask(SIG_SETMASK, &host_set, NULL); + do_sigprocmask(SIG_SETMASK, &host_set, NULL); if (restore_sigcontext(env, &uc->tuc_mcontext)) return 1; @@ -2017,7 +2095,7 @@ static long do_rt_sigreturn_v1(CPUARMState *env) goto badframe; target_to_host_sigset(&host_set, &frame->uc.tuc_sigmask); - sigprocmask(SIG_SETMASK, &host_set, NULL); + do_sigprocmask(SIG_SETMASK, &host_set, NULL); if (restore_sigcontext(env, &frame->uc.tuc_mcontext)) goto badframe; @@ -2428,7 +2506,7 @@ long do_sigreturn(CPUSPARCState *env) } target_to_host_sigset_internal(&host_set, &set); - sigprocmask(SIG_SETMASK, &host_set, NULL); + do_sigprocmask(SIG_SETMASK, &host_set, NULL); if (err) goto segv_and_exit; @@ -2551,7 +2629,7 @@ void sparc64_set_context(CPUSPARCState *env) goto do_sigsegv; } target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); } env->pc = pc; env->npc = npc; @@ -2640,7 +2718,7 @@ void sparc64_get_context(CPUSPARCState *env) err = 0; - sigprocmask(0, NULL, &set); + do_sigprocmask(0, NULL, &set); host_to_target_sigset_internal(&target_set, &set); if (TARGET_NSIG_WORDS == 1) { err |= __put_user(target_set.sig[0], @@ -2975,7 +3053,7 @@ long do_sigreturn(CPUMIPSState *regs) } target_to_host_sigset_internal(&blocked, &target_set); - sigprocmask(SIG_SETMASK, &blocked, NULL); + do_sigprocmask(SIG_SETMASK, &blocked, NULL); if (restore_sigcontext(regs, &frame->sf_sc)) goto badframe; @@ -3079,7 +3157,7 @@ long do_rt_sigreturn(CPUMIPSState *env) goto badframe; target_to_host_sigset(&blocked, &frame->rs_uc.tuc_sigmask); - sigprocmask(SIG_SETMASK, &blocked, NULL); + do_sigprocmask(SIG_SETMASK, &blocked, NULL); if (restore_sigcontext(env, &frame->rs_uc.tuc_mcontext)) goto badframe; @@ -3369,7 +3447,7 @@ long do_sigreturn(CPUSH4State *regs) goto badframe; target_to_host_sigset_internal(&blocked, &target_set); - sigprocmask(SIG_SETMASK, &blocked, NULL); + do_sigprocmask(SIG_SETMASK, &blocked, NULL); if (restore_sigcontext(regs, &frame->sc, &r0)) goto badframe; @@ -3398,7 +3476,7 @@ long do_rt_sigreturn(CPUSH4State *regs) goto badframe; target_to_host_sigset(&blocked, &frame->uc.tuc_sigmask); - sigprocmask(SIG_SETMASK, &blocked, NULL); + do_sigprocmask(SIG_SETMASK, &blocked, NULL); if (restore_sigcontext(regs, &frame->uc.tuc_mcontext, &r0)) goto badframe; @@ -3628,7 +3706,7 @@ long do_sigreturn(CPUMBState *env) goto badframe; } target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); restore_sigcontext(&frame->uc.tuc_mcontext, env); /* We got here through a sigreturn syscall, our path back is via an @@ -3803,7 +3881,7 @@ long do_sigreturn(CPUCRISState *env) goto badframe; } target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); restore_sigcontext(&frame->sc, env); unlock_user_struct(frame, frame_addr, 0); @@ -4334,7 +4412,7 @@ long do_sigreturn(CPUS390XState *env) } target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); /* ~_BLOCKABLE? */ + do_sigprocmask(SIG_SETMASK, &set, NULL); /* ~_BLOCKABLE? */ if (restore_sigregs(env, &frame->sregs)) { goto badframe; @@ -4362,7 +4440,7 @@ long do_rt_sigreturn(CPUS390XState *env) } target_to_host_sigset(&set, &frame->uc.tuc_sigmask); - sigprocmask(SIG_SETMASK, &set, NULL); /* ~_BLOCKABLE? */ + do_sigprocmask(SIG_SETMASK, &set, NULL); /* ~_BLOCKABLE? */ if (restore_sigregs(env, &frame->uc.tuc_mcontext)) { goto badframe; @@ -4890,7 +4968,7 @@ long do_sigreturn(CPUPPCState *env) goto sigsegv; #endif target_to_host_sigset_internal(&blocked, &set); - sigprocmask(SIG_SETMASK, &blocked, NULL); + do_sigprocmask(SIG_SETMASK, &blocked, NULL); if (__get_user(sr_addr, &sc->regs)) goto sigsegv; @@ -4934,7 +5012,7 @@ static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig) return 1; target_to_host_sigset_internal(&blocked, &set); - sigprocmask(SIG_SETMASK, &blocked, NULL); + do_sigprocmask(SIG_SETMASK, &blocked, NULL); if (restore_user_regs(env, mcp, sig)) goto sigsegv; @@ -5308,7 +5386,7 @@ long do_sigreturn(CPUM68KState *env) } target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); /* restore registers */ @@ -5336,7 +5414,7 @@ long do_rt_sigreturn(CPUM68KState *env) goto badframe; target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); /* restore registers */ @@ -5583,7 +5661,7 @@ long do_sigreturn(CPUAlphaState *env) } target_to_host_sigset_internal(&set, &target_set); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); if (restore_sigcontext(env, sc)) { goto badframe; @@ -5606,7 +5684,7 @@ long do_rt_sigreturn(CPUAlphaState *env) goto badframe; } target_to_host_sigset(&set, &frame->uc.tuc_sigmask); - sigprocmask(SIG_SETMASK, &set, NULL); + do_sigprocmask(SIG_SETMASK, &set, NULL); if (restore_sigcontext(env, &frame->uc.tuc_mcontext)) { goto badframe; @@ -5665,7 +5743,7 @@ void process_pending_signals(CPUArchState *cpu_env) struct emulated_sigtable *k; struct target_sigaction *sa; struct sigqueue *q; - TaskState *ts = cpu_env->opaque; + TaskState *ts = cpu->opaque; if (!ts->signal_pending) return; @@ -5700,6 +5778,14 @@ void process_pending_signals(CPUArchState *cpu_env) handler = sa->_sa_handler; } + if (ts->sigsegv_blocked && sig == TARGET_SIGSEGV) { + /* Guest has blocked SIGSEGV but we got one anyway. Assume this + * is a forced SIGSEGV (ie one the kernel handles via force_sig_info + * because it got a real MMU fault), and treat as if default handler. + */ + handler = TARGET_SIG_DFL; + } + if (handler == TARGET_SIG_DFL) { /* default handler : ignore some signal. The other are job control or fatal */ if (sig == TARGET_SIGTSTP || sig == TARGET_SIGTTIN || sig == TARGET_SIGTTOU) { @@ -5723,7 +5809,7 @@ void process_pending_signals(CPUArchState *cpu_env) sigaddset(&set, target_to_host_signal(sig)); /* block signals in the handler using Linux */ - sigprocmask(SIG_BLOCK, &set, &old_set); + do_sigprocmask(SIG_BLOCK, &set, &old_set); /* save the previous blocked signal state to restore it at the end of the signal execution (see do_sigreturn) */ host_to_target_sigset_internal(&target_old_set, &old_set); diff --git a/linux-user/sparc/syscall.h b/linux-user/sparc/syscall.h index 4cd64bf..9549ea0 100644 --- a/linux-user/sparc/syscall.h +++ b/linux-user/sparc/syscall.h @@ -7,6 +7,7 @@ struct target_pt_regs { }; #define UNAME_MACHINE "sun4" +#define UNAME_MINIMUM_RELEASE "2.6.32" /* SPARC kernels don't define this in their Kconfig, but they have the * same ABI as if they did, implemented by sparc-specific code which fishes diff --git a/linux-user/sparc64/syscall.h b/linux-user/sparc64/syscall.h index e60bf31..82b1680 100644 --- a/linux-user/sparc64/syscall.h +++ b/linux-user/sparc64/syscall.h @@ -8,6 +8,7 @@ struct target_pt_regs { }; #define UNAME_MACHINE "sun4u" +#define UNAME_MINIMUM_RELEASE "2.6.32" /* SPARC kernels don't define this in their Kconfig, but they have the * same ABI as if they did, implemented by sparc-specific code which fishes diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 1407b7a..2eac6d5 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -43,6 +43,7 @@ #include <sys/resource.h> #include <sys/mman.h> #include <sys/swap.h> +#include <linux/capability.h> #include <signal.h> #include <sched.h> #ifdef __ia64__ @@ -243,6 +244,10 @@ _syscall3(int, sys_sched_setaffinity, pid_t, pid, unsigned int, len, unsigned long *, user_mask_ptr); _syscall4(int, reboot, int, magic1, int, magic2, unsigned int, cmd, void *, arg); +_syscall2(int, capget, struct __user_cap_header_struct *, header, + struct __user_cap_data_struct *, data); +_syscall2(int, capset, struct __user_cap_header_struct *, header, + struct __user_cap_data_struct *, data); static bitmask_transtbl fcntl_flags_tbl[] = { { TARGET_O_ACCMODE, TARGET_O_WRONLY, O_ACCMODE, O_WRONLY, }, @@ -1904,23 +1909,16 @@ static abi_long do_connect(int sockfd, abi_ulong target_addr, return get_errno(connect(sockfd, addr, addrlen)); } -/* do_sendrecvmsg() Must return target values and target errnos. */ -static abi_long do_sendrecvmsg(int fd, abi_ulong target_msg, - int flags, int send) +/* do_sendrecvmsg_locked() Must return target values and target errnos. */ +static abi_long do_sendrecvmsg_locked(int fd, struct target_msghdr *msgp, + int flags, int send) { abi_long ret, len; - struct target_msghdr *msgp; struct msghdr msg; int count; struct iovec *vec; abi_ulong target_vec; - /* FIXME */ - if (!lock_user_struct(send ? VERIFY_READ : VERIFY_WRITE, - msgp, - target_msg, - send ? 1 : 0)) - return -TARGET_EFAULT; if (msgp->msg_name) { msg.msg_namelen = tswap32(msgp->msg_namelen); msg.msg_name = alloca(msg.msg_namelen); @@ -1975,10 +1973,75 @@ static abi_long do_sendrecvmsg(int fd, abi_ulong target_msg, out: unlock_iovec(vec, target_vec, count, !send); out2: + return ret; +} + +static abi_long do_sendrecvmsg(int fd, abi_ulong target_msg, + int flags, int send) +{ + abi_long ret; + struct target_msghdr *msgp; + + if (!lock_user_struct(send ? VERIFY_READ : VERIFY_WRITE, + msgp, + target_msg, + send ? 1 : 0)) { + return -TARGET_EFAULT; + } + ret = do_sendrecvmsg_locked(fd, msgp, flags, send); unlock_user_struct(msgp, target_msg, send ? 0 : 1); return ret; } +#ifdef TARGET_NR_sendmmsg +/* We don't rely on the C library to have sendmmsg/recvmmsg support, + * so it might not have this *mmsg-specific flag either. + */ +#ifndef MSG_WAITFORONE +#define MSG_WAITFORONE 0x10000 +#endif + +static abi_long do_sendrecvmmsg(int fd, abi_ulong target_msgvec, + unsigned int vlen, unsigned int flags, + int send) +{ + struct target_mmsghdr *mmsgp; + abi_long ret = 0; + int i; + + if (vlen > UIO_MAXIOV) { + vlen = UIO_MAXIOV; + } + + mmsgp = lock_user(VERIFY_WRITE, target_msgvec, sizeof(*mmsgp) * vlen, 1); + if (!mmsgp) { + return -TARGET_EFAULT; + } + + for (i = 0; i < vlen; i++) { + ret = do_sendrecvmsg_locked(fd, &mmsgp[i].msg_hdr, flags, send); + if (is_error(ret)) { + break; + } + mmsgp[i].msg_len = tswap32(ret); + /* MSG_WAITFORONE turns on MSG_DONTWAIT after one packet */ + if (flags & MSG_WAITFORONE) { + flags |= MSG_DONTWAIT; + } + } + + unlock_user(mmsgp, target_msgvec, sizeof(*mmsgp) * i); + + /* Return number of datagrams sent if we sent any at all; + * otherwise return the error. + */ + if (i) { + return i; + } + return ret; +} +#endif + /* If we don't have a system accept4() then just call accept. * The callsites to do_accept4() will ensure that they don't * pass a non-zero flags argument in this config. @@ -4185,7 +4248,7 @@ static void *clone_func(void *arg) env = info->env; cpu = ENV_GET_CPU(env); thread_cpu = cpu; - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; info->tid = gettid(); cpu->host_tid = info->tid; task_settid(ts); @@ -4213,8 +4276,10 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { + CPUState *cpu = ENV_GET_CPU(env); int ret; TaskState *ts; + CPUState *new_cpu; CPUArchState *new_env; unsigned int nptl_flags; sigset_t sigmask; @@ -4224,7 +4289,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, flags &= ~(CLONE_VFORK | CLONE_VM); if (flags & CLONE_VM) { - TaskState *parent_ts = (TaskState *)env->opaque; + TaskState *parent_ts = (TaskState *)cpu->opaque; new_thread_info info; pthread_attr_t attr; @@ -4234,7 +4299,8 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, new_env = cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_env->opaque = ts; + new_cpu = ENV_GET_CPU(new_env); + new_cpu->opaque = ts; ts->bprm = parent_ts->bprm; ts->info = parent_ts->info; nptl_flags = flags; @@ -4306,7 +4372,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, put_user_u32(gettid(), child_tidptr); if (flags & CLONE_PARENT_SETTID) put_user_u32(gettid(), parent_tidptr); - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; if (flags & CLONE_SETTLS) cpu_set_tls (env, newtls); if (flags & CLONE_CHILD_CLEARTID) @@ -4360,6 +4426,14 @@ static int target_to_host_fcntl_cmd(int cmd) #endif case TARGET_F_NOTIFY: return F_NOTIFY; +#ifdef F_GETOWN_EX + case TARGET_F_GETOWN_EX: + return F_GETOWN_EX; +#endif +#ifdef F_SETOWN_EX + case TARGET_F_SETOWN_EX: + return F_SETOWN_EX; +#endif default: return -TARGET_EINVAL; } @@ -4382,6 +4456,10 @@ static abi_long do_fcntl(int fd, int cmd, abi_ulong arg) struct target_flock *target_fl; struct flock64 fl64; struct target_flock64 *target_fl64; +#ifdef F_GETOWN_EX + struct f_owner_ex fox; + struct target_f_owner_ex *target_fox; +#endif abi_long ret; int host_cmd = target_to_host_fcntl_cmd(cmd); @@ -4475,6 +4553,30 @@ static abi_long do_fcntl(int fd, int cmd, abi_ulong arg) ret = get_errno(fcntl(fd, host_cmd, target_to_host_bitmask(arg, fcntl_flags_tbl))); break; +#ifdef F_GETOWN_EX + case TARGET_F_GETOWN_EX: + ret = get_errno(fcntl(fd, host_cmd, &fox)); + if (ret >= 0) { + if (!lock_user_struct(VERIFY_WRITE, target_fox, arg, 0)) + return -TARGET_EFAULT; + target_fox->type = tswap32(fox.type); + target_fox->pid = tswap32(fox.pid); + unlock_user_struct(target_fox, arg, 1); + } + break; +#endif + +#ifdef F_SETOWN_EX + case TARGET_F_SETOWN_EX: + if (!lock_user_struct(VERIFY_READ, target_fox, arg, 1)) + return -TARGET_EFAULT; + fox.type = tswap32(target_fox->type); + fox.pid = tswap32(target_fox->pid); + unlock_user_struct(target_fox, arg, 0); + ret = get_errno(fcntl(fd, host_cmd, &fox)); + break; +#endif + case TARGET_F_SETOWN: case TARGET_F_GETOWN: case TARGET_F_SETSIG: @@ -4528,6 +4630,9 @@ static inline int tswapid(int id) { return tswap16(id); } + +#define put_user_id(x, gaddr) put_user_u16(x, gaddr) + #else /* !USE_UID16 */ static inline int high2lowuid(int uid) { @@ -4549,6 +4654,9 @@ static inline int tswapid(int id) { return tswap32(id); } + +#define put_user_id(x, gaddr) put_user_u32(x, gaddr) + #endif /* USE_UID16 */ void syscall_init(void) @@ -4910,7 +5018,8 @@ void init_qemu_uname_release(void) static int open_self_maps(void *cpu_env, int fd) { #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; #endif FILE *fp; char *line = NULL; @@ -4962,7 +5071,8 @@ static int open_self_maps(void *cpu_env, int fd) static int open_self_stat(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong start_stack = ts->info->start_stack; int i; @@ -4998,7 +5108,8 @@ static int open_self_stat(void *cpu_env, int fd) static int open_self_auxv(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong auxv = ts->info->saved_auxv; abi_ulong len = ts->info->auxv_len; char *ptr; @@ -5180,14 +5291,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, /* Remove the CPU from the list. */ QTAILQ_REMOVE(&cpus, cpu, node); cpu_list_unlock(); - ts = ((CPUArchState *)cpu_env)->opaque; + ts = cpu->opaque; if (ts->child_tidptr) { put_user_u32(0, ts->child_tidptr); sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX, NULL, NULL, 0); } thread_cpu = NULL; - object_unref(OBJECT(ENV_GET_CPU(cpu_env))); + object_unref(OBJECT(cpu)); g_free(ts); pthread_exit(NULL); } @@ -5923,7 +6034,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, { sigset_t cur_set; abi_ulong target_set; - sigprocmask(0, NULL, &cur_set); + do_sigprocmask(0, NULL, &cur_set); host_to_target_old_sigset(&target_set, &cur_set); ret = target_set; } @@ -5934,10 +6045,10 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, { sigset_t set, oset, cur_set; abi_ulong target_set = arg1; - sigprocmask(0, NULL, &cur_set); + do_sigprocmask(0, NULL, &cur_set); target_to_host_old_sigset(&set, &target_set); sigorset(&set, &set, &cur_set); - sigprocmask(SIG_SETMASK, &set, &oset); + do_sigprocmask(SIG_SETMASK, &set, &oset); host_to_target_old_sigset(&target_set, &oset); ret = target_set; } @@ -5968,7 +6079,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, mask = arg2; target_to_host_old_sigset(&set, &mask); - ret = get_errno(sigprocmask(how, &set, &oldset)); + ret = get_errno(do_sigprocmask(how, &set, &oldset)); if (!is_error(ret)) { host_to_target_old_sigset(&mask, &oldset); ret = mask; @@ -6002,7 +6113,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, how = 0; set_ptr = NULL; } - ret = get_errno(sigprocmask(how, set_ptr, &oldset)); + ret = get_errno(do_sigprocmask(how, set_ptr, &oldset)); if (!is_error(ret) && arg3) { if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(target_sigset_t), 0))) goto efault; @@ -6042,7 +6153,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, how = 0; set_ptr = NULL; } - ret = get_errno(sigprocmask(how, set_ptr, &oldset)); + ret = get_errno(do_sigprocmask(how, set_ptr, &oldset)); if (!is_error(ret) && arg3) { if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(target_sigset_t), 0))) goto efault; @@ -6121,11 +6232,17 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, puts = NULL; } ret = get_errno(sigtimedwait(&set, &uinfo, puts)); - if (!is_error(ret) && arg2) { - if (!(p = lock_user(VERIFY_WRITE, arg2, sizeof(target_siginfo_t), 0))) - goto efault; - host_to_target_siginfo(p, &uinfo); - unlock_user(p, arg2, sizeof(target_siginfo_t)); + if (!is_error(ret)) { + if (arg2) { + p = lock_user(VERIFY_WRITE, arg2, sizeof(target_siginfo_t), + 0); + if (!p) { + goto efault; + } + host_to_target_siginfo(p, &uinfo); + unlock_user(p, arg2, sizeof(target_siginfo_t)); + } + ret = host_to_target_signal(ret); } } break; @@ -6485,7 +6602,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; case TARGET_NR_mprotect: { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; /* Special hack to detect libc making the stack executable. */ if ((arg3 & PROT_GROWSDOWN) && arg1 >= ts->info->stack_limit @@ -6710,6 +6827,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, ret = do_sendrecvmsg(arg1, arg2, arg3, 1); break; #endif +#ifdef TARGET_NR_sendmmsg + case TARGET_NR_sendmmsg: + ret = do_sendrecvmmsg(arg1, arg2, arg3, arg4, 1); + break; + case TARGET_NR_recvmmsg: + ret = do_sendrecvmmsg(arg1, arg2, arg3, arg4, 0); + break; +#endif #ifdef TARGET_NR_sendto case TARGET_NR_sendto: ret = do_sendto(arg1, arg2, arg3, arg4, arg5, arg6); @@ -7557,9 +7682,75 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, unlock_user(p, arg1, ret); break; case TARGET_NR_capget: - goto unimplemented; case TARGET_NR_capset: - goto unimplemented; + { + struct target_user_cap_header *target_header; + struct target_user_cap_data *target_data = NULL; + struct __user_cap_header_struct header; + struct __user_cap_data_struct data[2]; + struct __user_cap_data_struct *dataptr = NULL; + int i, target_datalen; + int data_items = 1; + + if (!lock_user_struct(VERIFY_WRITE, target_header, arg1, 1)) { + goto efault; + } + header.version = tswap32(target_header->version); + header.pid = tswap32(target_header->pid); + + if (header.version != _LINUX_CAPABILITY_VERSION) { + /* Version 2 and up takes pointer to two user_data structs */ + data_items = 2; + } + + target_datalen = sizeof(*target_data) * data_items; + + if (arg2) { + if (num == TARGET_NR_capget) { + target_data = lock_user(VERIFY_WRITE, arg2, target_datalen, 0); + } else { + target_data = lock_user(VERIFY_READ, arg2, target_datalen, 1); + } + if (!target_data) { + unlock_user_struct(target_header, arg1, 0); + goto efault; + } + + if (num == TARGET_NR_capset) { + for (i = 0; i < data_items; i++) { + data[i].effective = tswap32(target_data[i].effective); + data[i].permitted = tswap32(target_data[i].permitted); + data[i].inheritable = tswap32(target_data[i].inheritable); + } + } + + dataptr = data; + } + + if (num == TARGET_NR_capget) { + ret = get_errno(capget(&header, dataptr)); + } else { + ret = get_errno(capset(&header, dataptr)); + } + + /* The kernel always updates version for both capget and capset */ + target_header->version = tswap32(header.version); + unlock_user_struct(target_header, arg1, 1); + + if (arg2) { + if (num == TARGET_NR_capget) { + for (i = 0; i < data_items; i++) { + target_data[i].effective = tswap32(data[i].effective); + target_data[i].permitted = tswap32(data[i].permitted); + target_data[i].inheritable = tswap32(data[i].inheritable); + } + unlock_user(target_data, arg2, target_datalen); + } else { + unlock_user(target_data, arg2, 0); + } + } + break; + } case TARGET_NR_sigaltstack: #if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_MIPS) || \ defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_ALPHA) || \ @@ -7805,9 +7996,9 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, uid_t ruid, euid, suid; ret = get_errno(getresuid(&ruid, &euid, &suid)); if (!is_error(ret)) { - if (put_user_u16(high2lowuid(ruid), arg1) - || put_user_u16(high2lowuid(euid), arg2) - || put_user_u16(high2lowuid(suid), arg3)) + if (put_user_id(high2lowuid(ruid), arg1) + || put_user_id(high2lowuid(euid), arg2) + || put_user_id(high2lowuid(suid), arg3)) goto efault; } } @@ -7826,9 +8017,9 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, gid_t rgid, egid, sgid; ret = get_errno(getresgid(&rgid, &egid, &sgid)); if (!is_error(ret)) { - if (put_user_u16(high2lowgid(rgid), arg1) - || put_user_u16(high2lowgid(egid), arg2) - || put_user_u16(high2lowgid(sgid), arg3)) + if (put_user_id(high2lowgid(rgid), arg1) + || put_user_id(high2lowgid(egid), arg2) + || put_user_id(high2lowgid(sgid), arg3)) goto efault; } } @@ -8041,7 +8232,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, } mask = arg2; target_to_host_old_sigset(&set, &mask); - sigprocmask(how, &set, &oldset); + do_sigprocmask(how, &set, &oldset); host_to_target_old_sigset(&mask, &oldset); ret = mask; } @@ -8569,7 +8760,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ts->tp_value = arg1; ret = 0; break; @@ -8585,7 +8776,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ret = ts->tp_value; break; } @@ -9064,6 +9255,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, case TARGET_NR_atomic_barrier: { /* Like the kernel implementation and the qemu arm barrier, no-op this? */ + ret = 0; break; } #endif diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 3c8869e..fdf9a47 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -53,7 +53,8 @@ #define TARGET_IOC_NRBITS 8 #define TARGET_IOC_TYPEBITS 8 -#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SPARC) \ +#if defined(TARGET_I386) || (defined(TARGET_ARM) && defined(TARGET_ABI32)) \ + || defined(TARGET_SPARC) \ || defined(TARGET_M68K) || defined(TARGET_SH4) || defined(TARGET_CRIS) /* 16 bit uid wrappers emulation */ #define USE_UID16 @@ -239,6 +240,10 @@ __target_cmsg_nxthdr (struct target_msghdr *__mhdr, struct target_cmsghdr *__cms return __cmsg; } +struct target_mmsghdr { + struct target_msghdr msg_hdr; /* Message header */ + unsigned int msg_len; /* Number of bytes transmitted */ +}; struct target_rusage { struct target_timeval ru_utime; /* user time used */ @@ -2118,6 +2123,8 @@ struct target_statfs64 { #define TARGET_F_SETOWN 8 /* for sockets. */ #define TARGET_F_GETOWN 9 /* for sockets. */ #endif +#define TARGET_F_SETOWN_EX 15 +#define TARGET_F_GETOWN_EX 16 #ifndef TARGET_F_RDLCK #define TARGET_F_RDLCK 0 @@ -2300,6 +2307,11 @@ struct target_eabi_flock64 { } QEMU_PACKED; #endif +struct target_f_owner_ex { + int type; /* Owner type of ID. */ + int pid; /* ID of owner. */ +}; + /* soundcard defines */ /* XXX: convert them all to arch indepedent entries */ #define TARGET_SNDCTL_COPR_HALT TARGET_IOWR('C', 7, int); @@ -2554,3 +2566,14 @@ struct target_sigevent { } _sigev_thread; } _sigev_un; }; + +struct target_user_cap_header { + uint32_t version; + int pid; +}; + +struct target_user_cap_data { + uint32_t effective; + uint32_t permitted; + uint32_t inheritable; +}; diff --git a/linux-user/unicore32/syscall.h b/linux-user/unicore32/syscall.h index 010cdd8..f7e5525 100644 --- a/linux-user/unicore32/syscall.h +++ b/linux-user/unicore32/syscall.h @@ -51,5 +51,6 @@ struct target_pt_regs { #define UC32_SYSCALL_NR_set_tls (UC32_SYSCALL_ARCH_BASE + 5) #define UNAME_MACHINE "UniCore-II" +#define UNAME_MINIMUM_RELEASE "2.6.32" #endif /* __UC32_SYSCALL_H__ */ diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 2c4ffeb..45ef559 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -72,7 +72,8 @@ static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16) void save_v86_state(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0)) @@ -131,7 +132,8 @@ static inline void return_to_32bit(CPUX86State *env, int retval) static inline int set_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags |= VIF_MASK; if (ts->v86flags & VIP_MASK) { @@ -143,7 +145,8 @@ static inline int set_IF(CPUX86State *env) static inline void clear_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags &= ~VIF_MASK; } @@ -160,7 +163,8 @@ static inline void clear_AC(CPUX86State *env) static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, eflags, ts->v86mask); set_flags(env->eflags, eflags, SAFE_MASK); @@ -173,7 +177,8 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) static inline int set_vflags_short(unsigned short flags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); set_flags(env->eflags, flags, SAFE_MASK); @@ -186,7 +191,8 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env) static inline unsigned int get_vflags(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; unsigned int flags; flags = env->eflags & RETURN_MASK; @@ -202,7 +208,8 @@ static inline unsigned int get_vflags(CPUX86State *env) support TSS interrupt revectoring, so this code is always executed) */ static void do_int(CPUX86State *env, int intno) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t int_addr, segoffs, ssp; unsigned int sp; @@ -260,7 +267,8 @@ void handle_vm86_trap(CPUX86State *env, int trapno) void handle_vm86_fault(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t csp, ssp; unsigned int ip, sp, newflags, newip, newcs, opcode, intno; int data32, pref_done; @@ -384,7 +392,8 @@ void handle_vm86_fault(CPUX86State *env) int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; int ret; diff --git a/linux-user/x86_64/syscall.h b/linux-user/x86_64/syscall.h index 81314cf..e03b5a0 100644 --- a/linux-user/x86_64/syscall.h +++ b/linux-user/x86_64/syscall.h @@ -91,6 +91,7 @@ struct target_msqid64_ds { }; #define UNAME_MACHINE "x86_64" +#define UNAME_MINIMUM_RELEASE "2.6.32" #define TARGET_ARCH_SET_GS 0x1001 #define TARGET_ARCH_SET_FS 0x1002 diff --git a/main-loop.c b/main-loop.c index c3c9c28..8a85493 100644 --- a/main-loop.c +++ b/main-loop.c @@ -25,6 +25,7 @@ #include "qemu-common.h" #include "qemu/timer.h" #include "qemu/sockets.h" // struct in_addr needed for libslirp.h +#include "sysemu/qtest.h" #include "slirp/libslirp.h" #include "qemu/main-loop.h" #include "block/aio.h" @@ -208,7 +209,7 @@ static int os_host_main_loop_wait(int64_t timeout) if (!timeout && (spin_counter > MAX_MAIN_LOOP_SPIN)) { static bool notified; - if (!notified) { + if (!notified && !qtest_enabled()) { fprintf(stderr, "main-loop: WARNING: I/O thread spun for %d iterations\n", MAX_MAIN_LOOP_SPIN); diff --git a/migration.c b/migration.c index 00f465e..e0e24d4 100644 --- a/migration.c +++ b/migration.c @@ -101,6 +101,7 @@ void qemu_start_incoming_migration(const char *uri, Error **errp) static void process_incoming_migration_co(void *opaque) { QEMUFile *f = opaque; + Error *local_err = NULL; int ret; ret = qemu_loadvm_state(f); @@ -115,7 +116,12 @@ static void process_incoming_migration_co(void *opaque) bdrv_clear_incoming_migration_all(); /* Make sure all file formats flush their mutable metadata */ - bdrv_invalidate_cache_all(); + bdrv_invalidate_cache_all(&local_err); + if (local_err) { + qerror_report_err(local_err); + error_free(local_err); + exit(EXIT_FAILURE); + } if (autostart) { vm_start(); diff --git a/net/slirp.c b/net/slirp.c index 124e953..cce026b 100644 --- a/net/slirp.c +++ b/net/slirp.c @@ -529,7 +529,8 @@ static int slirp_smb(SlirpState* s, const char *exported_dir, "state directory=%s\n" "log file=%s/log.smbd\n" "smb passwd file=%s/smbpasswd\n" - "security = share\n" + "security = user\n" + "map to guest = Bad User\n" "[qemu]\n" "path=%s\n" "read only=no\n" @@ -549,7 +550,8 @@ static int slirp_smb(SlirpState* s, const char *exported_dir, snprintf(smb_cmdline, sizeof(smb_cmdline), "%s -s %s", CONFIG_SMBD_COMMAND, smb_conf); - if (slirp_add_exec(s->slirp, 0, smb_cmdline, &vserver_addr, 139) < 0) { + if (slirp_add_exec(s->slirp, 0, smb_cmdline, &vserver_addr, 139) < 0 || + slirp_add_exec(s->slirp, 0, smb_cmdline, &vserver_addr, 445) < 0) { slirp_smb_cleanup(s); error_report("conflicting/invalid smbserver address"); return -1; @@ -190,7 +190,7 @@ static void tap_send(void *opaque) TAPState *s = opaque; int size; - do { + while (qemu_can_send_packet(&s->nc)) { uint8_t *buf = s->buf; size = tap_read_packet(s->fd, s->buf, sizeof(s->buf)); @@ -206,8 +206,11 @@ static void tap_send(void *opaque) size = qemu_send_packet_async(&s->nc, buf, size, tap_send_completed); if (size == 0) { tap_read_poll(s, false); + break; + } else if (size < 0) { + break; } - } while (size > 0 && qemu_can_send_packet(&s->nc)); + } } static bool tap_has_ufo(NetClientState *nc) @@ -44,10 +44,6 @@ #include <sys/prctl.h> #endif -#ifdef __FreeBSD__ -#include <sys/sysctl.h> -#endif - static struct passwd *user_pwd; static const char *chroot_dir; static int daemonize; diff --git a/pc-bios/README b/pc-bios/README index 5914200..ef6008d 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -5,19 +5,19 @@ project (http://www.nongnu.org/vgabios/). - The PowerPC Open Hack'Ware Open Firmware Compatible BIOS is - available at http://perso.magic.fr/l_indien/OpenHackWare/index.htm. + available at http://repo.or.cz/w/openhackware.git. - OpenBIOS (http://www.openbios.org/) is a free (GPL v2) portable firmware implementation. The goal is to implement a 100% IEEE 1275-1994 (referred to as Open Firmware) compliant firmware. The included images for PowerPC (for 32 and 64 bit PPC CPUs), Sparc32 (including QEMU,tcx.bin and QEMU,cgthree.bin) and Sparc64 are built - from OpenBIOS SVN revision 1246. + from OpenBIOS SVN revision 1280. - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware implementation for certain IBM POWER hardware. The sources are at https://github.com/aik/SLOF, and the image currently in qemu is - built from git tag qemu-slof-20131015. + built from git tag qemu-slof-20140304. - sgabios (the Serial Graphics Adapter option ROM) provides a means for legacy x86 software to communicate with an attached serial console as diff --git a/pc-bios/ohw.diff b/pc-bios/ohw.diff deleted file mode 100644 index c6b6623..0000000 --- a/pc-bios/ohw.diff +++ /dev/null @@ -1,1843 +0,0 @@ -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/bios.h OpenHackWare-release-0.4/src/bios.h ---- OpenHackWare-release-0.4.org/src/bios.h 2005-04-06 23:20:22.000000000 +0200 -+++ OpenHackWare-release-0.4/src/bios.h 2005-07-07 01:10:20.000000000 +0200 -@@ -64,6 +64,7 @@ - ARCH_CHRP, - ARCH_MAC99, - ARCH_POP, -+ ARCH_HEATHROW, - }; - - /* Hardware definition(s) */ -@@ -174,6 +175,7 @@ - int bd_ioctl (bloc_device_t *bd, int func, void *args); - uint32_t bd_seclen (bloc_device_t *bd); - void bd_close (bloc_device_t *bd); -+void bd_reset_all(void); - uint32_t bd_seclen (bloc_device_t *bd); - uint32_t bd_maxbloc (bloc_device_t *bd); - void bd_sect2CHS (bloc_device_t *bd, uint32_t secnum, -@@ -183,12 +185,12 @@ - part_t *bd_probe (int boot_device); - bloc_device_t *bd_get (int device); - void bd_put (bloc_device_t *bd); --void bd_set_boot_part (bloc_device_t *bd, part_t *partition); -+void bd_set_boot_part (bloc_device_t *bd, part_t *partition, int partnum); - part_t **_bd_parts (bloc_device_t *bd); - - void ide_pci_pc_register (uint32_t io_base0, uint32_t io_base1, - uint32_t io_base2, uint32_t io_base3, -- void *OF_private); -+ void *OF_private0, void *OF_private1); - void ide_pci_pmac_register (uint32_t io_base0, uint32_t io_base1, - void *OF_private); - -@@ -399,17 +401,23 @@ - uint16_t min_grant, uint16_t max_latency); - void OF_finalize_pci_host (void *dev, int first_bus, int nb_busses); - void OF_finalize_pci_device (void *dev, uint8_t bus, uint8_t devfn, -- uint32_t *regions, uint32_t *sizes); -+ uint32_t *regions, uint32_t *sizes, -+ int irq_line); - void OF_finalize_pci_macio (void *dev, uint32_t base_address, uint32_t size, - void *private_data); -+void OF_finalize_pci_ide (void *dev, -+ uint32_t io_base0, uint32_t io_base1, -+ uint32_t io_base2, uint32_t io_base3); - int OF_register_bus (const unsigned char *name, uint32_t address, - const unsigned char *type); - int OF_register_serial (const unsigned char *bus, const unsigned char *name, - uint32_t io_base, int irq); - int OF_register_stdio (const unsigned char *dev_in, - const unsigned char *dev_out); --void OF_vga_register (const unsigned char *name, uint32_t address, -- int width, int height, int depth); -+void OF_vga_register (const unsigned char *name, unused uint32_t address, -+ int width, int height, int depth, -+ unsigned long vga_bios_addr, -+ unsigned long vga_bios_size); - void *OF_blockdev_register (void *parent, void *private, - const unsigned char *type, - const unsigned char *name, int devnum, -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/bloc.c OpenHackWare-release-0.4/src/bloc.c ---- OpenHackWare-release-0.4.org/src/bloc.c 2005-04-06 23:21:00.000000000 +0200 -+++ OpenHackWare-release-0.4/src/bloc.c 2005-07-08 00:28:26.000000000 +0200 -@@ -55,6 +55,7 @@ - /* Partitions */ - part_t *parts, *bparts; - part_t *boot_part; -+ int bpartnum; - /* Chain */ - bloc_device_t *next; - }; -@@ -66,6 +67,7 @@ - - static int ide_initialize (bloc_device_t *bd, int device); - static int ide_read_sector (bloc_device_t *bd, void *buffer, int secnum); -+static int ide_reset (bloc_device_t *bd); - - static int mem_initialize (bloc_device_t *bd, int device); - static int mem_read_sector (bloc_device_t *bd, void *buffer, int secnum); -@@ -212,6 +214,17 @@ - { - } - -+void bd_reset_all(void) -+{ -+ bloc_device_t *bd; -+ for (bd = bd_list; bd != NULL; bd = bd->next) { -+ if (bd->init == &ide_initialize) { -+ /* reset IDE drive because Darwin wants all IDE devices to be reset */ -+ ide_reset(bd); -+ } -+ } -+} -+ - uint32_t bd_seclen (bloc_device_t *bd) - { - return bd->seclen; -@@ -223,10 +236,12 @@ - } - - /* XXX: to be suppressed */ --void bd_set_boot_part (bloc_device_t *bd, part_t *partition) -+void bd_set_boot_part (bloc_device_t *bd, part_t *partition, int partnum) - { -+ dprintf("%s: part %p (%p) %d\n", __func__, partition, bd->boot_part, partnum); - if (bd->boot_part == NULL) { - bd->boot_part = partition; -+ bd->bpartnum = partnum; - } - } - -@@ -240,6 +255,13 @@ - return &bd->bparts; - } - -+void bd_set_boot_device (bloc_device_t *bd) -+{ -+#if defined (USE_OPENFIRMWARE) -+ OF_blockdev_set_boot_device(bd->OF_private, bd->bpartnum, "\\\\ofwboot"); -+#endif -+} -+ - part_t *bd_probe (int boot_device) - { - char devices[] = { /*'a', 'b',*/ 'c', 'd', 'e', 'f', 'm', '\0', }; -@@ -272,9 +294,7 @@ - tmp = part_probe(bd, force_raw); - if (boot_device == bd->device) { - boot_part = tmp; --#if defined (USE_OPENFIRMWARE) -- OF_blockdev_set_boot_device(bd->OF_private, 2, "\\\\ofwboot"); --#endif -+ bd_set_boot_device(bd); - } - } - -@@ -717,34 +737,29 @@ - /* IDE PCI access for pc */ - static uint8_t ide_pci_port_read (bloc_device_t *bd, int port) - { -- eieio(); -- -- return *(uint8_t *)(bd->io_base + port); -+ uint8_t value; -+ value = inb(bd->io_base + port); -+ return value; - } - - static void ide_pci_port_write (bloc_device_t *bd, int port, uint8_t value) - { -- *(uint8_t *)(bd->io_base + port) = value; -- eieio(); -+ outb(bd->io_base + port, value); - } - - static uint32_t ide_pci_data_readl (bloc_device_t *bd) - { -- eieio(); -- -- return *((uint32_t *)bd->io_base); -+ return inl(bd->io_base); - } - - static void ide_pci_data_writel (bloc_device_t *bd, uint32_t val) - { -- *(uint32_t *)(bd->io_base) = val; -- eieio(); -+ outl(bd->io_base, val); - } - - static void ide_pci_control_write (bloc_device_t *bd, uint32_t val) - { -- *((uint8_t *)bd->tmp) = val; -- eieio(); -+ outb(bd->tmp + 2, val); - } - - static ide_ops_t ide_pci_pc_ops = { -@@ -761,7 +776,7 @@ - - void ide_pci_pc_register (uint32_t io_base0, uint32_t io_base1, - uint32_t io_base2, uint32_t io_base3, -- unused void *OF_private) -+ void *OF_private0, void *OF_private1) - { - if (ide_pci_ops == NULL) { - ide_pci_ops = malloc(sizeof(ide_ops_t)); -@@ -770,19 +785,19 @@ - memcpy(ide_pci_ops, &ide_pci_pc_ops, sizeof(ide_ops_t)); - } - if ((io_base0 != 0 || io_base1 != 0) && -- ide_pci_ops->base[0] == 0 && ide_pci_ops->base[1] == 0) { -+ ide_pci_ops->base[0] == 0 && ide_pci_ops->base[2] == 0) { - ide_pci_ops->base[0] = io_base0; -- ide_pci_ops->base[1] = io_base1; -+ ide_pci_ops->base[2] = io_base1; - #ifdef USE_OPENFIRMWARE -- ide_pci_ops->OF_private[0] = OF_private; -+ ide_pci_ops->OF_private[0] = OF_private0; - #endif - } - if ((io_base2 != 0 || io_base3 != 0) && -- ide_pci_ops->base[2] == 0 && ide_pci_ops->base[3] == 0) { -- ide_pci_ops->base[2] = io_base2; -+ ide_pci_ops->base[1] == 0 && ide_pci_ops->base[3] == 0) { -+ ide_pci_ops->base[1] = io_base2; - ide_pci_ops->base[3] = io_base3; - #ifdef USE_OPENFIRMWARE -- ide_pci_ops->OF_private[1] = OF_private; -+ ide_pci_ops->OF_private[1] = OF_private1; - #endif - } - } -@@ -935,6 +950,8 @@ - } - - static void atapi_pad_req (void *buffer, int len); -+static void atapi_make_req (bloc_device_t *bd, uint32_t *buffer, -+ int maxlen); - static int atapi_read_sector (bloc_device_t *bd, void *buffer, int secnum); - - static int ide_initialize (bloc_device_t *bd, int device) -@@ -1035,9 +1052,7 @@ - DPRINTF("INQUIRY\n"); - len = spc_inquiry_req(&atapi_buffer, 36); - atapi_pad_req(&atapi_buffer, len); -- ide_port_write(bd, 0x07, 0xA0); -- for (i = 0; i < 3; i++) -- ide_data_writel(bd, ldswap32(&atapi_buffer[i])); -+ atapi_make_req(bd, atapi_buffer, 36); - status = ide_port_read(bd, 0x07); - if (status != 0x48) { - ERROR("ATAPI INQUIRY : status %0x != 0x48\n", status); -@@ -1053,9 +1068,7 @@ - DPRINTF("READ_CAPACITY\n"); - len = mmc_read_capacity_req(&atapi_buffer); - atapi_pad_req(&atapi_buffer, len); -- ide_port_write(bd, 0x07, 0xA0); -- for (i = 0; i < 3; i++) -- ide_data_writel(bd, ldswap32(&atapi_buffer[i])); -+ atapi_make_req(bd, atapi_buffer, 8); - status = ide_port_read(bd, 0x07); - if (status != 0x48) { - ERROR("ATAPI READ_CAPACITY : status %0x != 0x48\n", status); -@@ -1105,6 +1118,22 @@ - memset(p + len, 0, 12 - len); - } - -+static void atapi_make_req (bloc_device_t *bd, uint32_t *buffer, -+ int maxlen) -+{ -+ int i; -+ /* select drive */ -+ if (bd->drv == 0) -+ ide_port_write(bd, 0x06, 0x40); -+ else -+ ide_port_write(bd, 0x06, 0x50); -+ ide_port_write(bd, 0x04, maxlen & 0xff); -+ ide_port_write(bd, 0x05, (maxlen >> 8) & 0xff); -+ ide_port_write(bd, 0x07, 0xA0); -+ for (i = 0; i < 3; i++) -+ ide_data_writel(bd, ldswap32(&buffer[i])); -+} -+ - static int atapi_read_sector (bloc_device_t *bd, void *buffer, int secnum) - { - uint32_t atapi_buffer[4]; -@@ -1112,16 +1141,9 @@ - uint32_t status, value; - int i, len; - -- /* select drive */ -- if (bd->drv == 0) -- ide_port_write(bd, 0x06, 0x40); -- else -- ide_port_write(bd, 0x06, 0x50); - len = mmc_read12_req(atapi_buffer, secnum, 1); - atapi_pad_req(&atapi_buffer, len); -- ide_port_write(bd, 0x07, 0xA0); -- for (i = 0; i < 3; i++) -- ide_data_writel(bd, ldswap32(&atapi_buffer[i])); -+ atapi_make_req(bd, atapi_buffer, bd->seclen); - status = ide_port_read(bd, 0x07); - if (status != 0x48) { - ERROR("ATAPI READ12 : status %0x != 0x48\n", status); -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/libpart/apple.c OpenHackWare-release-0.4/src/libpart/apple.c ---- OpenHackWare-release-0.4.org/src/libpart/apple.c 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/libpart/apple.c 2005-07-03 16:17:41.000000000 +0200 -@@ -199,14 +199,18 @@ - if (len == 0) { - /* Place holder. Skip it */ - DPRINTF("%s placeholder part\t%d\n", __func__, i); -+ part->flags = PART_TYPE_APPLE | PART_FLAG_DUMMY; -+ part_register(bd, part, name, i); - } else if (strncmp("Apple_Void", type, 32) == 0) { - /* Void partition. Skip it */ - DPRINTF("%s Void part\t%d [%s]\n", __func__, i, type); -+ part->flags = PART_TYPE_APPLE | PART_FLAG_DUMMY; -+ part_register(bd, part, name, i); - } else if (strncmp("Apple_Free", type, 32) == 0) { - /* Free space. Skip it */ - DPRINTF("%s Free part (%d)\n", __func__, i); - part->flags = PART_TYPE_APPLE | PART_FLAG_DUMMY; -- part_register(bd, part, name); -+ part_register(bd, part, name, i); - } else if (strncmp("Apple_partition_map", type, 32) == 0 || - strncmp("Apple_Partition_Map", type, 32) == 0 - #if 0 // Is this really used or is it just a mistake ? -@@ -226,7 +230,7 @@ - */ - } - part->flags = PART_TYPE_APPLE | PART_FLAG_DUMMY; -- part_register(bd, part, name); -+ part_register(bd, part, name, i); - } else if (strncmp("Apple_Driver", type, 32) == 0 || - strncmp("Apple_Driver43", type, 32) == 0 || - strncmp("Apple_Driver43_CD", type, 32) == 0 || -@@ -236,8 +240,12 @@ - strncmp("Apple_Driver_IOKit", type, 32) == 0) { - /* Drivers. don't care for now */ - DPRINTF("%s Drivers part\t%d [%s]\n", __func__, i, type); -+ part->flags = PART_TYPE_APPLE | PART_FLAG_DRIVER; -+ part_register(bd, part, name, i); - } else if (strncmp("Apple_Patches", type, 32) == 0) { - /* Patches: don't care for now */ -+ part->flags = PART_TYPE_APPLE | PART_FLAG_PATCH; -+ part_register(bd, part, name, i); - DPRINTF("%s Patches part\t%d [%s]\n", __func__, i, type); - } else if (strncmp("Apple_HFS", type, 32) == 0 || - strncmp("Apple_MFS", type, 32) == 0 || -@@ -256,9 +264,8 @@ - count = partmap->bloc_cnt * HFS_BLOCSIZE; - if (partmap->boot_size == 0 || partmap->boot_load == 0) { - printf("Not a bootable partition %d %d (%p %p)\n", -- partmap->boot_size, partmap->boot_load,boot_part, part); -- if (boot_part == NULL) -- boot_part = part; -+ partmap->boot_size, partmap->boot_load, -+ boot_part, part); - part->flags = PART_TYPE_APPLE | PART_FLAG_FS; - } else { - part->boot_start.bloc = partmap->boot_start; -@@ -278,8 +285,8 @@ - boot_part = part; - part->flags = PART_TYPE_APPLE | PART_FLAG_FS | PART_FLAG_BOOT; - } -- printf("Partition: %d %s st %0x size %0x", -- i, name, partmap->start_bloc, partmap->bloc_cnt); -+ printf("Partition: %d '%s' '%s' st %0x size %0x", -+ i, name, type, partmap->start_bloc, partmap->bloc_cnt); - #ifndef DEBUG - printf("\n"); - #endif -@@ -290,11 +297,13 @@ - part->boot_load, part->boot_entry); - DPRINTF(" load %0x entry %0x %0x\n", - partmap->boot_load2, partmap->boot_entry2, HFS_BLOCSIZE); -- part_register(bd, part, name); -+ part_register(bd, part, name, i); - } else { - memcpy(tmp, type, 32); - tmp[32] = '\0'; - ERROR("Unknown partition type [%s]\n", tmp); -+ part->flags = PART_TYPE_APPLE | PART_FLAG_DUMMY; -+ part_register(bd, part, name, i); - } - } - error: -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/libpart/core.c OpenHackWare-release-0.4/src/libpart/core.c ---- OpenHackWare-release-0.4.org/src/libpart/core.c 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/libpart/core.c 2005-07-03 16:17:41.000000000 +0200 -@@ -126,7 +126,7 @@ - } - - int part_register (bloc_device_t *bd, part_t *partition, -- const unsigned char *name) -+ const unsigned char *name, int partnum) - { - part_t **cur; - -@@ -134,6 +134,7 @@ - partition->bd = bd; - partition->next = NULL; - partition->name = strdup(name); -+ partition->partnum = partnum; - for (cur = _bd_parts(bd); *cur != NULL; cur = &(*cur)->next) - continue; - *cur = partition; -@@ -141,29 +142,15 @@ - return 0; - } - --static inline int set_boot_part (bloc_device_t *bd, int partnum) --{ -- part_t *cur; -- -- cur = part_get(bd, partnum); -- if (cur == NULL) -- return -1; -- bd_set_boot_part(bd, cur); -- -- return 0; --} -- - part_t *part_get (bloc_device_t *bd, int partnum) - { - part_t **listp, *cur; -- int i; - - listp = _bd_parts(bd); -- cur = *listp; -- for (i = 0; i != partnum; i++) { -- if (cur == NULL) -+ -+ for (cur = *listp; cur != NULL; cur = cur->next) { -+ if (cur->partnum == partnum) - break; -- cur = cur->next; - } - - return cur; -@@ -192,17 +179,20 @@ - part_set_blocsize(bd, part, 512); - part->bd = bd; - part->flags = PART_TYPE_RAW | PART_FLAG_BOOT; -- part_register(bd, part, "Raw"); -+ part_register(bd, part, "Raw", 0); - - return part; - } - -+bloc_device_t *part_get_bd (part_t *part) -+{ -+ return part->bd; -+} -+ - part_t *part_probe (bloc_device_t *bd, int set_raw) - { -- part_t *part0, *boot_part, **cur; -+ part_t *part0 = NULL, *boot_part, **cur; - -- /* Register the 0 partition: raw partition containing the whole disk */ -- part0 = part_get_raw(bd); - /* Try to find a valid boot partition */ - boot_part = Apple_probe_partitions(bd); - if (boot_part == NULL) { -@@ -210,10 +200,13 @@ - if (boot_part == NULL && arch == ARCH_PREP) - boot_part = PREP_find_partition(bd); - if (boot_part == NULL && set_raw != 0) { -- boot_part = part0; -- set_boot_part(bd, 0); -+ dprintf("Use bloc device as raw partition\n"); - } - } -+ if (_bd_parts(bd) == NULL) { -+ /* Register the 0 partition: raw partition containing the whole disk */ -+ part0 = part_get_raw(bd); -+ } - /* Probe filesystem on each found partition */ - for (cur = _bd_parts(bd); *cur != NULL; cur = &(*cur)->next) { - const unsigned char *map, *type; -@@ -248,23 +241,28 @@ - type = "unknown"; - break; - } -- DPRINTF("Probe filesystem on %s %s partition '%s' %s\n", -+ dprintf("Probe filesystem on %s %s partition '%s' %s %p\n", - type, map, (*cur)->name, -- ((*cur)->flags) & PART_FLAG_BOOT ? "(bootable)" : ""); -+ ((*cur)->flags) & PART_FLAG_BOOT ? "(bootable)" : "", *cur); - if (((*cur)->flags) & PART_FLAG_FS) { - if (((*cur)->flags) & PART_FLAG_BOOT) - (*cur)->fs = fs_probe(*cur, 1); - else - (*cur)->fs = fs_probe(*cur, 0); -+ } else if (((*cur)->flags) & PART_TYPE_RAW) { -+ (*cur)->fs = fs_probe(*cur, 2); - } else { - (*cur)->fs = fs_probe(*cur, 2); - } -- if (((*cur)->flags) & PART_FLAG_BOOT) { -- bd_set_boot_part(bd, *cur); - fs_get_bootfile((*cur)->fs); -+ if (((*cur)->flags) & PART_FLAG_BOOT) { -+ dprintf("Partition is bootable (%d)\n", (*cur)->partnum); -+ bd_set_boot_part(bd, *cur, (*cur)->partnum); -+ if (boot_part == NULL) -+ boot_part = *cur; - } - } -- DPRINTF("Boot partition: %p %p %p %p\n", boot_part, boot_part->fs, -+ dprintf("Boot partition: %p %p %p %p\n", boot_part, boot_part->fs, - part_fs(boot_part), part0); - - return boot_part; -@@ -279,6 +277,7 @@ - part->boot_size.offset = 0; - part->boot_load = 0; - part->boot_entry = 0; -+ part->flags |= PART_FLAG_BOOT; - - return 0; - } -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/libpart/isofs.c OpenHackWare-release-0.4/src/libpart/isofs.c ---- OpenHackWare-release-0.4.org/src/libpart/isofs.c 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/libpart/isofs.c 2005-07-03 16:17:41.000000000 +0200 -@@ -242,7 +242,7 @@ - part->boot_start.bloc, part->boot_size.bloc, - part->boot_load, part->boot_entry); - part->flags = PART_TYPE_ISO9660 | PART_FLAG_BOOT; -- part_register(bd, part, name); -+ part_register(bd, part, name, i + 1); - fs_raw_set_bootfile(part, part->boot_start.bloc, - part->boot_start.offset, - part->boot_size.bloc, -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/libpart/libpart.h OpenHackWare-release-0.4/src/libpart/libpart.h ---- OpenHackWare-release-0.4.org/src/libpart/libpart.h 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/libpart/libpart.h 2005-07-03 16:17:41.000000000 +0200 -@@ -30,6 +30,7 @@ - - struct part_t { - bloc_device_t *bd; -+ int partnum; - uint32_t start; /* Partition first bloc */ - uint32_t size; /* Partition size, in blocs */ - uint32_t spb; -@@ -54,7 +55,7 @@ - }; - - int part_register (bloc_device_t *bd, part_t *partition, -- const unsigned char *name); -+ const unsigned char *name, int partnum); - void part_set_blocsize (bloc_device_t *bd, part_t *part, uint32_t blocsize); - void part_private_set (part_t *part, void *private); - void *part_private_get (part_t *part); -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/libpart/prep.c OpenHackWare-release-0.4/src/libpart/prep.c ---- OpenHackWare-release-0.4.org/src/libpart/prep.c 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/libpart/prep.c 2005-07-03 16:17:41.000000000 +0200 -@@ -164,7 +164,7 @@ - part->boot_load = 0; - part->boot_entry = boot_offset - part->bloc_size; - part->flags = PART_TYPE_PREP | PART_FLAG_BOOT; -- part_register(bd, part, "PREP boot"); -+ part_register(bd, part, "PREP boot", i); - fs_raw_set_bootfile(part, part->boot_start.bloc, - part->boot_start.offset, - part->boot_size.bloc, -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/main.c OpenHackWare-release-0.4/src/main.c ---- OpenHackWare-release-0.4.org/src/main.c 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/main.c 2005-06-07 23:48:39.000000000 +0200 -@@ -364,20 +364,24 @@ - void *load_base, *load_entry, *last_alloc, *load_end; - uint32_t memsize, boot_image_size, cmdline_size, ramdisk_size; - uint32_t boot_base, boot_nb; -- int boot_device; -+ int boot_device, i; -+ static const uint32_t isa_base_tab[3] = { -+ 0x80000000, /* PREP */ -+ 0xFE000000, /* Grackle (Heathrow) */ -+ 0xF2000000, /* UniNorth (Mac99) */ -+ }; - - /* Retrieve NVRAM configuration */ -- nvram_retry: -+ for(i = 0; i < 3; i++) { -+ isa_io_base = isa_base_tab[i]; - nvram = NVRAM_get_config(&memsize, &boot_device, - &boot_image, &boot_image_size, - &cmdline, &cmdline_size, - &ramdisk, &ramdisk_size); -- if (nvram == NULL) { -- /* Retry with another isa_io_base */ -- if (isa_io_base == 0x80000000) { -- isa_io_base = 0xF2000000; -- goto nvram_retry; -+ if (nvram) -+ break; - } -+ if (i == 3) { - ERROR("Unable to load configuration from NVRAM. Aborting...\n"); - return -1; - } -@@ -402,7 +406,7 @@ - cpu_name = CPU_get_name(pvr); - OF_register_cpu(cpu_name, 0, pvr, - 200 * 1000 * 1000, 200 * 1000 * 1000, -- 100 * 1000 * 1000, 10 * 1000 * 1000, -+ 100 * 1000 * 1000, 100 * 1000 * 1000, - 0x0092); - } - OF_register_memory(memsize, 512 * 1024 /* TOFIX */); -@@ -433,9 +437,12 @@ - vga_puts(copyright); - vga_puts("\n"); - -+#if 0 - /* QEMU is quite incoherent: d is cdrom, not second drive */ -+ /* XXX: should probe CD-ROM position */ - if (boot_device == 'd') - boot_device = 'e'; -+#endif - /* Open boot device */ - boot_part = bd_probe(boot_device); - if (boot_device == 'm') { -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/nvram.c OpenHackWare-release-0.4/src/nvram.c ---- OpenHackWare-release-0.4.org/src/nvram.c 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/nvram.c 2005-06-04 23:44:03.000000000 +0200 -@@ -334,6 +334,7 @@ - ret = NVRAM_chrp_format(nvram); - break; - case ARCH_MAC99: -+ case ARCH_HEATHROW: /* XXX: may be incorrect */ - ret = NVRAM_mac99_format(nvram); - break; - case ARCH_POP: -@@ -409,13 +410,12 @@ - arch = ARCH_MAC99; - } else if (strcmp(sign, "POP") == 0) { - arch = ARCH_POP; -+ } else if (strcmp(sign, "HEATHROW") == 0) { -+ arch = ARCH_HEATHROW; - } else { - ERROR("Unknown PPC architecture: '%s'\n", sign); - return NULL; - } -- /* HACK */ -- if (arch == ARCH_CHRP) -- arch = ARCH_MAC99; - lword = NVRAM_get_lword(nvram, 0x30); - *RAM_size = lword; - byte = NVRAM_get_byte(nvram, 0x34); -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/of.c OpenHackWare-release-0.4/src/of.c ---- OpenHackWare-release-0.4.org/src/of.c 2005-04-06 23:17:26.000000000 +0200 -+++ OpenHackWare-release-0.4/src/of.c 2005-07-07 23:30:08.000000000 +0200 -@@ -489,7 +489,7 @@ - ERROR("%s can't alloc new node '%s' name\n", __func__, name); - return NULL; - } -- new->prop_address = OF_prop_int_new(env, new, "address", address); -+ new->prop_address = OF_prop_int_new(env, new, "unit-address", address); - if (new->prop_address == NULL) { - free(new->prop_name->value); - free(new->prop_name); -@@ -1017,6 +1017,33 @@ - string, strlen(string) + 1); - } - -+/* convert '\1' char to '\0' */ -+static OF_prop_t *OF_prop_string_new1 (OF_env_t *env, OF_node_t *node, -+ const unsigned char *name, -+ const unsigned char *string) -+{ -+ int len, i; -+ OF_prop_t *ret; -+ unsigned char *str; -+ -+ if (strchr(string, '\1') == NULL) { -+ return OF_prop_string_new(env, node, name, string); -+ } else { -+ len = strlen(string) + 1; -+ str = malloc(len); -+ if (!str) -+ return NULL; -+ memcpy(str, string, len); -+ for(i = 0; i < len; i++) -+ if (str[i] == '\1') -+ str[i] = '\0'; -+ ret = OF_property_new(env, node, name, -+ str, len); -+ free(str); -+ return ret; -+ } -+} -+ - __attribute__ (( section (".OpenFirmware") )) - static OF_prop_t *OF_prop_int_new (OF_env_t *env, OF_node_t *node, - const unsigned char *name, uint32_t value) -@@ -1421,15 +1448,12 @@ - __attribute__ (( section (".OpenFirmware") )) - int OF_init (void) - { -- const unsigned char compat_str[] = - #if 0 - "PowerMac3,1\0MacRISC\0Power Macintosh\0"; - "PowerMac1,2\0MacRISC\0Power Macintosh\0"; - "AAPL,PowerMac G3\0PowerMac G3\0MacRISC\0Power Macintosh\0"; - "AAPL,PowerMac3,0\0MacRISC\0Power Macintosh\0"; - "AAPL,Gossamer\0MacRISC\0Power Macintosh\0"; --#else -- "AAPL,PowerMac G3\0PowerMac G3\0MacRISC\0Power Macintosh\0"; - #endif - OF_env_t *OF_env; - OF_node_t *als, *opt, *chs, *pks; -@@ -1455,15 +1479,21 @@ - return -1; - } - OF_prop_string_new(OF_env, OF_node_root, "device_type", "bootrom"); --#if 0 -- OF_prop_string_new(OF_env, OF_node_root, -- "model", "PPC Open Hack'Ware " BIOS_VERSION); --#else -+ if (arch == ARCH_HEATHROW) { -+ const unsigned char compat_str[] = -+ "PowerMac1,1\0MacRISC\0Power Macintosh"; -+ OF_property_new(OF_env, OF_node_root, "compatible", -+ compat_str, sizeof(compat_str)); - OF_prop_string_new(OF_env, OF_node_root, -- "model", compat_str); --#endif -+ "model", "Power Macintosh"); -+ } else { -+ const unsigned char compat_str[] = -+ "PowerMac3,1\0MacRISC\0Power Macintosh"; - OF_property_new(OF_env, OF_node_root, "compatible", - compat_str, sizeof(compat_str)); -+ OF_prop_string_new(OF_env, OF_node_root, -+ "model", "PowerMac3,1"); -+ } - #if 0 - OF_prop_string_new(OF_env, OF_node_root, "copyright", copyright); - #else -@@ -1561,14 +1591,15 @@ - range.size = 0x00800000; - OF_property_new(OF_env, rom, "ranges", &range, sizeof(OF_range_t)); - OF_prop_int_new(OF_env, rom, "#address-cells", 1); -+ - /* "/rom/boot-rom@fff00000" node */ -- brom = OF_node_new(OF_env, OF_node_root, "boot-rom", 0xfff00000); -+ brom = OF_node_new(OF_env, rom, "boot-rom", 0xfff00000); - if (brom == NULL) { - ERROR("Cannot create 'boot-rom'\n"); - return -1; - } - regs.address = 0xFFF00000; -- regs.size = 0x00010000; -+ regs.size = 0x00100000; - OF_property_new(OF_env, brom, "reg", ®s, sizeof(OF_regprop_t)); - OF_prop_string_new(OF_env, brom, "write-characteristic", "flash"); - OF_prop_string_new(OF_env, brom, "BootROM-build-date", -@@ -1577,7 +1608,7 @@ - OF_prop_string_new(OF_env, brom, "copyright", copyright); - OF_prop_string_new(OF_env, brom, "model", BIOS_str); - OF_prop_int_new(OF_env, brom, "result", 0); --#if 0 -+#if 1 - { - /* Hack taken 'as-is' from PearPC */ - unsigned char info[] = { -@@ -1596,7 +1627,9 @@ - OF_node_put(OF_env, brom); - OF_node_put(OF_env, rom); - } -+#if 0 - /* From here, hardcoded hacks to get a Mac-like machine */ -+ /* XXX: Core99 does not seem to like this NVRAM tree */ - /* "/nvram@fff04000" node */ - { - OF_regprop_t regs; -@@ -1617,6 +1650,7 @@ - OF_prop_int_new(OF_env, chs, "nvram", OF_pack_handle(OF_env, nvr)); - OF_node_put(OF_env, nvr); - } -+#endif - /* "/pseudo-hid" : hid emulation as Apple does */ - { - OF_node_t *hid; -@@ -1663,7 +1697,27 @@ - } - OF_node_put(OF_env, hid); - } -+ if (arch == ARCH_MAC99) { -+ OF_node_t *unin; -+ OF_regprop_t regs; - -+ unin = OF_node_new(OF_env, OF_node_root, -+ "uni-n", 0xf8000000); -+ if (unin == NULL) { -+ ERROR("Cannot create 'uni-n'\n"); -+ return -1; -+ } -+ OF_prop_string_new(OF_env, unin, "device-type", "memory-controller"); -+ OF_prop_string_new(OF_env, unin, "model", "AAPL,UniNorth"); -+ OF_prop_string_new(OF_env, unin, "compatible", "uni-north"); -+ regs.address = 0xf8000000; -+ regs.size = 0x01000000; -+ OF_property_new(OF_env, unin, "reg", ®s, sizeof(regs)); -+ OF_prop_int_new(OF_env, unin, "#address-cells", 1); -+ OF_prop_int_new(OF_env, unin, "#size-cells", 1); -+ OF_prop_int_new(OF_env, unin, "device-rev", 3); -+ OF_node_put(OF_env, unin); -+ } - - #if 1 /* This is mandatory for claim to work - * but I don't know where it should really be (in cpu ?) -@@ -1693,7 +1747,9 @@ - - /* "/options/boot-args" node */ - { -- const unsigned char *args = "-v rootdev cdrom"; -+ // const unsigned char *args = "-v rootdev cdrom"; -+ //const unsigned char *args = "-v io=0xffffffff"; -+ const unsigned char *args = "-v"; - /* Ask MacOS X to print debug messages */ - // OF_prop_string_new(OF_env, chs, "machargs", args); - // OF_prop_string_new(OF_env, opt, "boot-command", args); -@@ -2013,17 +2069,17 @@ - OF_prop_int_new(OF_env, node, "min-grant", min_grant); - OF_prop_int_new(OF_env, node, "max-latency", max_latency); - if (dev->type != NULL) -- OF_prop_string_new(OF_env, node, "device_type", dev->type); -+ OF_prop_string_new1(OF_env, node, "device_type", dev->type); - if (dev->compat != NULL) -- OF_prop_string_new(OF_env, node, "compatible", dev->compat); -+ OF_prop_string_new1(OF_env, node, "compatible", dev->compat); - if (dev->model != NULL) -- OF_prop_string_new(OF_env, node, "model", dev->model); -+ OF_prop_string_new1(OF_env, node, "model", dev->model); - if (dev->acells != 0) - OF_prop_int_new(OF_env, node, "#address-cells", dev->acells); - if (dev->scells != 0) -- OF_prop_int_new(OF_env, node, "#interrupt-cells", dev->acells); -+ OF_prop_int_new(OF_env, node, "#size-cells", dev->scells); - if (dev->icells != 0) -- OF_prop_int_new(OF_env, node, "#size-cells", dev->acells); -+ OF_prop_int_new(OF_env, node, "#interrupt-cells", dev->icells); - dprintf("Done %p %p\n", parent, node); - - return node; -@@ -2040,8 +2096,9 @@ - OF_env_t *OF_env; - pci_range_t ranges[3]; - OF_regprop_t regs[1]; -- OF_node_t *pci_host; -+ OF_node_t *pci_host, *als; - int nranges; -+ unsigned char buffer[OF_NAMELEN_MAX]; - - OF_env = OF_env_main; - dprintf("register PCI host '%s' '%s' '%s' '%s'\n", -@@ -2052,6 +2109,17 @@ - ERROR("Cannot create pci host\n"); - return NULL; - } -+ -+ als = OF_node_get(OF_env, "aliases"); -+ if (als == NULL) { -+ ERROR("Cannot get 'aliases'\n"); -+ return NULL; -+ } -+ sprintf(buffer, "/%s", dev->name); -+ OF_prop_string_set(OF_env, als, "pci", buffer); -+ OF_node_put(OF_env, als); -+ -+ - regs[0].address = cfg_base; - regs[0].size = cfg_len; - OF_property_new(OF_env, pci_host, "reg", regs, sizeof(OF_regprop_t)); -@@ -2136,6 +2204,11 @@ - return pci_dev; - } - -+/* XXX: suppress that, used for interrupt map init */ -+OF_node_t *pci_host_node; -+uint32_t pci_host_interrupt_map[7 * 32]; -+int pci_host_interrupt_map_len = 0; -+ - void OF_finalize_pci_host (void *dev, int first_bus, int nb_busses) - { - OF_env_t *OF_env; -@@ -2145,10 +2218,12 @@ - regs[0].address = first_bus; - regs[0].size = nb_busses; - OF_property_new(OF_env, dev, "bus-range", regs, sizeof(OF_regprop_t)); -+ pci_host_node = dev; - } - - void OF_finalize_pci_device (void *dev, uint8_t bus, uint8_t devfn, -- uint32_t *regions, uint32_t *sizes) -+ uint32_t *regions, uint32_t *sizes, -+ int irq_line) - { - OF_env_t *OF_env; - pci_reg_prop_t pregs[6], rregs[6]; -@@ -2156,6 +2231,7 @@ - int i, j, k; - - OF_env = OF_env_main; -+ /* XXX: only useful for VGA card in fact */ - if (regions[0] != 0x00000000) - OF_prop_int_set(OF_env, dev, "address", regions[0] & ~0x0000000F); - for (i = 0, j = 0, k = 0; i < 6; i++) { -@@ -2222,7 +2298,22 @@ - } else { - OF_property_new(OF_env, dev, "assigned-addresses", NULL, 0); - } --#if 0 -+ if (irq_line >= 0) { -+ int i; -+ OF_prop_int_new(OF_env, dev, "interrupts", 1); -+ i = pci_host_interrupt_map_len; -+ pci_host_interrupt_map[i++] = (devfn << 8) & 0xf800; -+ pci_host_interrupt_map[i++] = 0; -+ pci_host_interrupt_map[i++] = 0; -+ pci_host_interrupt_map[i++] = 0; -+ pci_host_interrupt_map[i++] = 0; /* pic handle will be patched later */ -+ pci_host_interrupt_map[i++] = irq_line; -+ if (arch != ARCH_HEATHROW) { -+ pci_host_interrupt_map[i++] = 1; -+ } -+ pci_host_interrupt_map_len = i; -+ } -+#if 1 - { - OF_prop_t *prop_name = ((OF_node_t *)dev)->prop_name; - -@@ -2390,6 +2481,54 @@ - return 0; - } - -+static void keylargo_ata(OF_node_t *mio, uint32_t base_address, -+ uint32_t base, int irq1, int irq2, -+ uint16_t pic_phandle) -+{ -+ OF_env_t *OF_env = OF_env_main; -+ OF_node_t *ata; -+ OF_regprop_t regs[2]; -+ -+ ata = OF_node_new(OF_env, mio, "ata-4", base); -+ if (ata == NULL) { -+ ERROR("Cannot create 'ata-4'\n"); -+ return; -+ } -+ OF_prop_string_new(OF_env, ata, "device_type", "ata"); -+#if 1 -+ OF_prop_string_new(OF_env, ata, "compatible", "key2largo-ata"); -+ OF_prop_string_new(OF_env, ata, "model", "ata-4"); -+ OF_prop_string_new(OF_env, ata, "cable-type", "80-conductor"); -+#else -+ OF_prop_string_new(OF_env, ata, "compatible", "cmd646-ata"); -+ OF_prop_string_new(OF_env, ata, "model", "ata-4"); -+#endif -+ OF_prop_int_new(OF_env, ata, "#address-cells", 1); -+ OF_prop_int_new(OF_env, ata, "#size-cells", 0); -+ regs[0].address = base; -+ regs[0].size = 0x00001000; -+#if 0 // HACK: Don't set up DMA registers -+ regs[1].address = 0x00008A00; -+ regs[1].size = 0x00001000; -+ OF_property_new(OF_env, ata, "reg", -+ regs, 2 * sizeof(OF_regprop_t)); -+#else -+ OF_property_new(OF_env, ata, "reg", -+ regs, sizeof(OF_regprop_t)); -+#endif -+ OF_prop_int_new(OF_env, ata, "interrupt-parent", pic_phandle); -+ regs[0].address = irq1; -+ regs[0].size = 0x00000001; -+ regs[1].address = irq2; -+ regs[1].size = 0x00000000; -+ OF_property_new(OF_env, ata, "interrupts", -+ regs, 2 * sizeof(OF_regprop_t)); -+ if (base == 0x1f000) -+ ide_pci_pmac_register(base_address + base, 0x00000000, ata); -+ else -+ ide_pci_pmac_register(0x00000000, base_address + base, ata); -+} -+ - void OF_finalize_pci_macio (void *dev, uint32_t base_address, uint32_t size, - void *private_data) - { -@@ -2398,6 +2537,8 @@ - pci_reg_prop_t pregs[2]; - OF_node_t *mio, *chs, *als; - uint16_t pic_phandle; -+ int rec_len; -+ OF_prop_t *mio_reg; - - OF_DPRINTF("mac-io: %p\n", dev); - OF_env = OF_env_main; -@@ -2416,10 +2557,14 @@ - mio = dev; - mio->private_data = private_data; - pregs[0].addr.hi = 0x00000000; -- pregs[0].addr.mid = 0x82013810; -+ pregs[0].addr.mid = 0x00000000; - pregs[0].addr.lo = 0x00000000; - pregs[0].size_hi = base_address; - pregs[0].size_lo = size; -+ mio_reg = OF_property_get(OF_env, mio, "reg"); -+ if (mio_reg && mio_reg->vlen >= 5 * 4) { -+ pregs[0].addr.mid = ((pci_reg_prop_t *)mio_reg->value)->addr.hi; -+ } - OF_property_new(OF_env, mio, "ranges", - &pregs, sizeof(pci_reg_prop_t)); - #if 0 -@@ -2431,8 +2576,32 @@ - OF_property_new(OF_env, mio, "assigned-addresses", - &pregs, sizeof(pci_reg_prop_t)); - #endif -+ -+ if (arch == ARCH_HEATHROW) { -+ /* Heathrow PIC */ -+ OF_regprop_t regs; -+ OF_node_t *mpic; -+ const char compat_str[] = "heathrow\0mac-risc"; -+ -+ mpic = OF_node_new(OF_env, mio, "interrupt-controller", 0x10); -+ if (mpic == NULL) { -+ ERROR("Cannot create 'mpic'\n"); -+ goto out; -+ } -+ OF_prop_string_new(OF_env, mpic, "device_type", "interrupt-controller"); -+ OF_property_new(OF_env, mpic, "compatible", compat_str, sizeof(compat_str)); -+ OF_prop_int_new(OF_env, mpic, "#interrupt-cells", 1); -+ regs.address = 0x10; -+ regs.size = 0x20; -+ OF_property_new(OF_env, mpic, "reg", -+ ®s, sizeof(regs)); -+ OF_property_new(OF_env, mpic, "interrupt-controller", NULL, 0); -+ pic_phandle = OF_pack_handle(OF_env, mpic); -+ OF_prop_int_new(OF_env, chs, "interrupt-controller", pic_phandle); -+ OF_node_put(OF_env, mpic); -+ rec_len = 6; -+ } else { - /* OpenPIC */ -- { - OF_regprop_t regs[4]; - OF_node_t *mpic; - mpic = OF_node_new(OF_env, mio, "interrupt-controller", 0x40000); -@@ -2455,8 +2624,37 @@ - pic_phandle = OF_pack_handle(OF_env, mpic); - OF_prop_int_new(OF_env, chs, "interrupt-controller", pic_phandle); - OF_node_put(OF_env, mpic); -+ rec_len = 7; - } --#if 1 -+ -+ /* patch pci host table */ -+ /* XXX: do it after the PCI init */ -+ { -+ int i; -+ uint32_t tab[4]; -+ -+ for(i = 0; i < pci_host_interrupt_map_len; i += rec_len) -+ pci_host_interrupt_map[i + 4] = pic_phandle; -+#if 0 -+ dprintf("interrupt-map:\n"); -+ for(i = 0; i < pci_host_interrupt_map_len; i++) { -+ dprintf(" %08x", pci_host_interrupt_map[i]); -+ if ((i % rec_len) == (rec_len - 1)) -+ dprintf("\n"); -+ } -+ dprintf("\n"); -+#endif -+ OF_property_new(OF_env, pci_host_node, "interrupt-map", -+ pci_host_interrupt_map, -+ pci_host_interrupt_map_len * sizeof(uint32_t)); -+ tab[0] = 0xf800; -+ tab[1] = 0; -+ tab[2] = 0; -+ tab[3] = 0; -+ OF_property_new(OF_env, pci_host_node, "interrupt-map-mask", -+ tab, 4 * sizeof(uint32_t)); -+ } -+#if 0 - /* escc is useful to get MacOS X debug messages */ - { - OF_regprop_t regs[8]; -@@ -2645,85 +2843,12 @@ - OF_node_put(OF_env, scc); - } - #endif -- /* IDE controller */ -- { -- OF_node_t *ata; -- OF_regprop_t regs[2]; -- ata = OF_node_new(OF_env, mio, "ata-4", 0x1f000); -- if (ata == NULL) { -- ERROR("Cannot create 'ata-4'\n"); -- goto out; -- } -- OF_prop_string_new(OF_env, ata, "device_type", "ata"); --#if 1 -- OF_prop_string_new(OF_env, ata, "compatible", "keylargo-ata"); -- OF_prop_string_new(OF_env, ata, "model", "ata-4"); --#else -- OF_prop_string_new(OF_env, ata, "compatible", "cmd646-ata"); -- OF_prop_string_new(OF_env, ata, "model", "ata-4"); --#endif -- OF_prop_int_new(OF_env, ata, "#address-cells", 1); -- OF_prop_int_new(OF_env, ata, "#size-cells", 0); -- regs[0].address = 0x0001F000; -- regs[0].size = 0x00001000; --#if 0 // HACK: Don't set up DMA registers -- regs[1].address = 0x00008A00; -- regs[1].size = 0x00001000; -- OF_property_new(OF_env, ata, "reg", -- regs, 2 * sizeof(OF_regprop_t)); --#else -- OF_property_new(OF_env, ata, "reg", -- regs, sizeof(OF_regprop_t)); --#endif -- OF_prop_int_new(OF_env, ata, "interrupt-parent", pic_phandle); -- regs[0].address = 0x00000013; -- regs[0].size = 0x00000001; -- regs[1].address = 0x0000000B; -- regs[1].size = 0x00000000; -- OF_property_new(OF_env, ata, "interrupts", -- regs, 2 * sizeof(OF_regprop_t)); -- ide_pci_pmac_register(base_address + 0x1f000, 0x00000000, ata); -- -- } -- { -- OF_node_t *ata; -- OF_regprop_t regs[2]; -- ata = OF_node_new(OF_env, mio, "ata-4", 0x20000); -- if (ata == NULL) { -- ERROR("Cannot create 'ata-4'\n"); -- goto out; -- } -- OF_prop_string_new(OF_env, ata, "device_type", "ata"); --#if 1 -- OF_prop_string_new(OF_env, ata, "compatible", "keylargo-ata"); -- OF_prop_string_new(OF_env, ata, "model", "ata-4"); --#else -- OF_prop_string_new(OF_env, ata, "compatible", "cmd646-ata"); -- OF_prop_string_new(OF_env, ata, "model", "ata-4"); --#endif -- OF_prop_int_new(OF_env, ata, "#address-cells", 1); -- OF_prop_int_new(OF_env, ata, "#size-cells", 0); -- regs[0].address = 0x00020000; -- regs[0].size = 0x00001000; --#if 0 // HACK: Don't set up DMA registers -- regs[1].address = 0x00008A00; -- regs[1].size = 0x00001000; -- OF_property_new(OF_env, ata, "reg", -- regs, 2 * sizeof(OF_regprop_t)); --#else -- OF_property_new(OF_env, ata, "reg", -- regs, sizeof(OF_regprop_t)); --#endif -- OF_prop_int_new(OF_env, ata, "interrupt-parent", pic_phandle); -- regs[0].address = 0x00000014; -- regs[0].size = 0x00000001; -- regs[1].address = 0x0000000B; -- regs[1].size = 0x00000000; -- OF_property_new(OF_env, ata, "interrupts", -- regs, 2 * sizeof(OF_regprop_t)); -- ide_pci_pmac_register(0x00000000, base_address + 0x20000, ata); -- -+ /* Keylargo IDE controller: need some work (DMA problem ?) */ -+ if (arch == ARCH_MAC99) { -+ keylargo_ata(mio, base_address, 0x1f000, 0x13, 0xb, pic_phandle); -+ keylargo_ata(mio, base_address, 0x20000, 0x14, 0xb, pic_phandle); - } -+#if 0 - /* Timer */ - { - OF_node_t *tmr; -@@ -2746,10 +2871,11 @@ - regs, sizeof(OF_regprop_t)); - OF_node_put(OF_env, tmr); - } -+#endif - /* VIA-PMU */ - { - /* Controls adb, RTC and power-mgt (forget it !) */ -- OF_node_t *via, *adb, *rtc; -+ OF_node_t *via, *adb; - OF_regprop_t regs[1]; - #if 0 // THIS IS A HACK AND IS COMPLETELY ABSURD ! - // (but needed has Qemu doesn't emulate via-pmu). -@@ -2773,14 +2899,21 @@ - regs[0].size = 0x00002000; - OF_property_new(OF_env, via, "reg", regs, sizeof(OF_regprop_t)); - OF_prop_int_new(OF_env, via, "interrupt-parent", pic_phandle); -+ if (arch == ARCH_HEATHROW) { -+ OF_prop_int_new(OF_env, via, "interrupts", 0x12); -+ } else { - regs[0].address = 0x00000019; - regs[0].size = 0x00000001; - OF_property_new(OF_env, via, "interrupts", - regs, sizeof(OF_regprop_t)); -+ } -+ /* force usage of OF bus speeds */ -+ OF_prop_int_new(OF_env, via, "BusSpeedCorrect", 1); - #if 0 - OF_prop_int_new(OF_env, via, "pmu-version", 0x00D0740C); - #endif --#if 1 -+ { -+ OF_node_t *kbd, *mouse; - /* ADB pseudo-device */ - adb = OF_node_new(OF_env, via, "adb", OF_ADDRESS_NONE); - if (adb == NULL) { -@@ -2797,9 +2930,26 @@ - OF_prop_int_new(OF_env, adb, "#size-cells", 0); - OF_pack_get_path(OF_env, tmp, 512, adb); - OF_prop_string_new(OF_env, als, "adb", tmp); -- /* XXX: add "keyboard@2" and "mouse@3" */ -- OF_node_put(OF_env, adb); --#endif -+ -+ kbd = OF_node_new(OF_env, adb, "keyboard", 2); -+ if (kbd == NULL) { -+ ERROR("Cannot create 'kbd'\n"); -+ goto out; -+ } -+ OF_prop_string_new(OF_env, kbd, "device_type", "keyboard"); -+ OF_prop_int_new(OF_env, kbd, "reg", 2); -+ -+ mouse = OF_node_new(OF_env, adb, "mouse", 3); -+ if (mouse == NULL) { -+ ERROR("Cannot create 'mouse'\n"); -+ goto out; -+ } -+ OF_prop_string_new(OF_env, mouse, "device_type", "mouse"); -+ OF_prop_int_new(OF_env, mouse, "reg", 3); -+ OF_prop_int_new(OF_env, mouse, "#buttons", 3); -+ } -+ { -+ OF_node_t *rtc; - - rtc = OF_node_new(OF_env, via, "rtc", OF_ADDRESS_NONE); - if (rtc == NULL) { -@@ -2813,14 +2963,68 @@ - OF_prop_string_new(OF_env, rtc, "compatible", "rtc"); - #endif - OF_node_put(OF_env, rtc); -- OF_node_put(OF_env, via); - } -+ // OF_node_put(OF_env, via); -+ } -+ { -+ OF_node_t *pmgt; -+ pmgt = OF_node_new(OF_env, mio, "power-mgt", OF_ADDRESS_NONE); -+ OF_prop_string_new(OF_env, pmgt, "device_type", "power-mgt"); -+ OF_prop_string_new(OF_env, pmgt, "compatible", "cuda"); -+ OF_prop_string_new(OF_env, pmgt, "mgt-kind", "min-consumption-pwm-led"); -+ OF_node_put(OF_env, pmgt); -+ } -+ -+ if (arch == ARCH_HEATHROW) { -+ /* NVRAM */ -+ OF_node_t *nvr; -+ OF_regprop_t regs; -+ nvr = OF_node_new(OF_env, mio, "nvram", 0x60000); -+ OF_prop_string_new(OF_env, nvr, "device_type", "nvram"); -+ regs.address = 0x60000; -+ regs.size = 0x00020000; -+ OF_property_new(OF_env, nvr, "reg", ®s, sizeof(regs)); -+ OF_prop_int_new(OF_env, nvr, "#bytes", 0x2000); -+ OF_node_put(OF_env, nvr); -+ } -+ - out: - // OF_node_put(OF_env, mio); - OF_node_put(OF_env, chs); - OF_node_put(OF_env, als); - } - -+void OF_finalize_pci_ide (void *dev, -+ uint32_t io_base0, uint32_t io_base1, -+ uint32_t io_base2, uint32_t io_base3) -+{ -+ OF_env_t *OF_env = OF_env_main; -+ OF_node_t *pci_ata = dev; -+ OF_node_t *ata, *atas[2]; -+ int i; -+ -+ OF_prop_int_new(OF_env, pci_ata, "#address-cells", 1); -+ OF_prop_int_new(OF_env, pci_ata, "#size-cells", 0); -+ -+ /* XXX: Darwin handles only one device */ -+ for(i = 0; i < 1; i++) { -+ ata = OF_node_new(OF_env, pci_ata, "ata-4", i); -+ if (ata == NULL) { -+ ERROR("Cannot create 'ata-4'\n"); -+ return; -+ } -+ OF_prop_string_new(OF_env, ata, "device_type", "ata"); -+ OF_prop_string_new(OF_env, ata, "compatible", "cmd646-ata"); -+ OF_prop_string_new(OF_env, ata, "model", "ata-4"); -+ OF_prop_int_new(OF_env, ata, "#address-cells", 1); -+ OF_prop_int_new(OF_env, ata, "#size-cells", 0); -+ OF_prop_int_new(OF_env, ata, "reg", i); -+ atas[i] = ata; -+ } -+ ide_pci_pc_register(io_base0, io_base1, io_base2, io_base3, -+ atas[0], atas[1]); -+} -+ - /*****************************************************************************/ - /* Fake package */ - static void OF_method_fake (OF_env_t *OF_env) -@@ -2862,11 +3066,11 @@ - /* As we get a 1:1 mapping, do nothing */ - ihandle = popd(OF_env); - args = (void *)popd(OF_env); -- address = popd(OF_env); -- virt = popd(OF_env); -- size = popd(OF_env); - popd(OF_env); -- OF_DPRINTF("Translate address %0x %0x %0x %0x\n", ihandle, address, -+ size = popd(OF_env); -+ virt = popd(OF_env); -+ address = popd(OF_env); -+ OF_DPRINTF("Map %0x %0x %0x %0x\n", ihandle, address, - virt, size); - pushd(OF_env, 0); - } -@@ -3270,7 +3474,7 @@ - OF_prop_string_new(OF_env, dsk, "device_type", "block"); - OF_prop_string_new(OF_env, dsk, "category", type); - OF_prop_int_new(OF_env, dsk, "device_id", devnum); -- OF_prop_int_new(OF_env, dsk, "reg", 0); -+ OF_prop_int_new(OF_env, dsk, "reg", devnum); - OF_method_new(OF_env, dsk, "open", &OF_blockdev_open); - OF_method_new(OF_env, dsk, "seek", &OF_blockdev_seek); - OF_method_new(OF_env, dsk, "read", &OF_blockdev_read); -@@ -3432,7 +3636,8 @@ - } - - void OF_vga_register (const unsigned char *name, unused uint32_t address, -- int width, int height, int depth) -+ int width, int height, int depth, -+ unsigned long vga_bios_addr, unsigned long vga_bios_size) - { - OF_env_t *OF_env; - unsigned char tmp[OF_NAMELEN_MAX]; -@@ -3504,6 +3709,18 @@ - OF_prop_string_new(OF_env, als, "display", tmp); - OF_node_put(OF_env, als); - /* XXX: may also need read-rectangle */ -+ -+ if (vga_bios_size >= 8) { -+ const uint8_t *p; -+ int size; -+ /* check the QEMU VGA BIOS header */ -+ p = (const uint8_t *)vga_bios_addr; -+ if (p[0] == 'N' && p[1] == 'D' && p[2] == 'R' && p[3] == 'V') { -+ size = *(uint32_t *)(p + 4); -+ OF_property_new(OF_env, disp, "driver,AAPL,MacOS,PowerPC", -+ p + 8, size); -+ } -+ } - out: - OF_node_put(OF_env, disp); - } -@@ -4451,7 +4668,10 @@ - break; - case 0x233441d3: /* MacOS X 10.2 and OpenDarwin 1.41 */ - /* Create "memory-map" pseudo device */ -- popd(OF_env); -+ { -+ OF_node_t *map; -+ uint32_t phandle; -+ - /* Find "/packages" */ - chs = OF_pack_find_by_name(OF_env, OF_node_root, "/chosen"); - if (chs == NULL) { -@@ -4459,10 +4679,6 @@ - ERROR("Cannot get '/chosen'\n"); - break; - } -- { --#if 1 -- OF_node_t *map; -- uint32_t phandle; - map = OF_node_new(OF_env, chs, "memory-map", OF_ADDRESS_NONE); - if (map == NULL) { - pushd(OF_env, -1); -@@ -4473,11 +4689,8 @@ - OF_node_put(OF_env, map); - OF_node_put(OF_env, chs); - pushd(OF_env, phandle); -- } --#else -- pushd(OF_env, 0); --#endif - pushd(OF_env, 0); -+ } - break; - case 0x32a2d18e: /* MacOS X 10.2 and OpenDarwin 6.02 */ - /* Return screen ihandle */ -@@ -4540,9 +4753,10 @@ - case 0x4ad41f2d: - /* Yaboot: wait 10 ms: sure ! */ - break; -+ - default: - /* ERROR */ -- printf("Script:\n%s\n", FString); -+ printf("Script: len=%d\n%s\n", (int)strlen(FString), FString); - printf("Call %0x NOT IMPLEMENTED !\n", crc); - bug(); - break; -@@ -4581,6 +4795,7 @@ - { - OF_CHECK_NBARGS(OF_env, 0); - /* Should free all OF resources */ -+ bd_reset_all(); - #if defined (DEBUG_BIOS) - { - uint16_t loglevel = 0x02 | 0x10 | 0x80; -diff -wruN --exclude '*~' --exclude '*.o' --exclude '*.bin' --exclude '*.out' --exclude mkdiff OpenHackWare-release-0.4.org/src/pci.c OpenHackWare-release-0.4/src/pci.c ---- OpenHackWare-release-0.4.org/src/pci.c 2005-03-31 09:23:33.000000000 +0200 -+++ OpenHackWare-release-0.4/src/pci.c 2005-07-07 23:27:37.000000000 +0200 -@@ -99,8 +99,8 @@ - uint16_t min_grant; - uint16_t max_latency; - uint8_t irq_line; -- uint32_t regions[6]; -- uint32_t sizes[6]; -+ uint32_t regions[7]; /* the region 6 is the PCI ROM */ -+ uint32_t sizes[7]; - pci_device_t *next; - }; - -@@ -158,6 +158,7 @@ - - /* IRQ numbers assigned to PCI IRQs */ - static uint8_t prep_pci_irqs[4] = { 9, 11, 9, 11 }; -+static uint8_t heathrow_pci_irqs[4] = { 0x15, 0x16, 0x17, 0x18 }; - static uint8_t pmac_pci_irqs[4] = { 8, 9, 10, 11 }; - - /* PREP PCI host */ -@@ -399,6 +400,79 @@ - &uninorth_config_readl, &uninorth_config_writel, - }; - -+/* Grackle PCI host */ -+ -+static uint32_t grackle_cfg_address (pci_bridge_t *bridge, -+ uint8_t bus, uint8_t devfn, -+ uint8_t offset) -+{ -+ uint32_t addr; -+ addr = 0x80000000 | (bus << 16) | (devfn << 8) | (offset & 0xfc); -+ stswap32((uint32_t *)bridge->cfg_addr, addr); -+ return bridge->cfg_data + (offset & 3); -+} -+ -+static uint8_t grackle_config_readb (pci_bridge_t *bridge, -+ uint8_t bus, uint8_t devfn, -+ uint8_t offset) -+{ -+ uint32_t addr; -+ addr = grackle_cfg_address(bridge, bus, devfn, offset); -+ return *((uint8_t *)addr); -+} -+ -+static void grackle_config_writeb (pci_bridge_t *bridge, -+ uint8_t bus, uint8_t devfn, -+ uint8_t offset, uint8_t val) -+{ -+ uint32_t addr; -+ addr = grackle_cfg_address(bridge, bus, devfn, offset); -+ *((uint8_t *)addr) = val; -+} -+ -+static uint16_t grackle_config_readw (pci_bridge_t *bridge, -+ uint8_t bus, uint8_t devfn, -+ uint8_t offset) -+{ -+ uint32_t addr; -+ addr = grackle_cfg_address(bridge, bus, devfn, offset); -+ return ldswap16((uint16_t *)addr); -+} -+ -+static void grackle_config_writew (pci_bridge_t *bridge, -+ uint8_t bus, uint8_t devfn, -+ uint8_t offset, uint16_t val) -+{ -+ uint32_t addr; -+ addr = grackle_cfg_address(bridge, bus, devfn, offset); -+ stswap16((uint16_t *)addr, val); -+} -+ -+static uint32_t grackle_config_readl (pci_bridge_t *bridge, -+ uint8_t bus, uint8_t devfn, -+ uint8_t offset) -+{ -+ uint32_t addr; -+ addr = grackle_cfg_address(bridge, bus, devfn, offset); -+ return ldswap32((uint32_t *)addr); -+} -+ -+static void grackle_config_writel (pci_bridge_t *bridge, -+ uint8_t bus, uint8_t devfn, -+ uint8_t offset, uint32_t val) -+{ -+ uint32_t addr; -+ -+ addr = grackle_cfg_address(bridge, bus, devfn, offset); -+ stswap32((uint32_t *)addr, val); -+} -+ -+static pci_ops_t grackle_pci_ops = { -+ &grackle_config_readb, &grackle_config_writeb, -+ &grackle_config_readw, &grackle_config_writew, -+ &grackle_config_readl, &grackle_config_writel, -+}; -+ - static inline uint8_t pci_config_readb (pci_bridge_t *bridge, - uint8_t bus, uint8_t devfn, - uint8_t offset) -@@ -466,12 +540,22 @@ - }, - }; - -+static int ide_config_cb2 (pci_device_t *device) -+{ -+ OF_finalize_pci_ide(device->common.OF_private, -+ device->regions[0] & ~0x0000000F, -+ device->regions[1] & ~0x0000000F, -+ device->regions[2] & ~0x0000000F, -+ device->regions[3] & ~0x0000000F); -+ return 0; -+} -+ - static pci_dev_t ide_devices[] = { - { -- 0x8086, 0x0100, -- NULL, "Qemu IDE", "Qemu IDE", "ide", -+ 0x1095, 0x0646, /* CMD646 IDE controller */ -+ "pci-ide", "pci-ata", NULL, NULL, - 0, 0, 0, -- NULL, NULL, -+ ide_config_cb2, NULL, - }, - { - 0xFFFF, 0xFFFF, -@@ -481,7 +565,9 @@ - }, - }; - --static int ide_config_cb (pci_device_t *device) -+#if 0 -+/* should base it on PCI ID, not on arch */ -+static int ide_config_cb (unused pci_device_t *device) - { - printf("Register IDE controller\n"); - switch (arch) { -@@ -491,14 +577,8 @@ - device->common.OF_private); - break; - default: -- ide_pci_pc_register(device->regions[0] & ~0x0000000F, -- device->regions[1] & ~0x0000000F, -- device->regions[2] & ~0x0000000F, -- device->regions[3] & ~0x0000000F, -- device->common.OF_private); - break; - } -- - return 0; - } - -@@ -512,16 +592,12 @@ - device->common.OF_private); - break; - default: -- ide_pci_pc_register(device->regions[0] & ~0x0000000F, -- device->regions[1] & ~0x0000000F, -- device->regions[2] & ~0x0000000F, -- device->regions[3] & ~0x0000000F, -- device->common.OF_private); - break; - } - - return 0; - } -+#endif - - static pci_subclass_t mass_subclass[] = { - { -@@ -530,7 +606,7 @@ - }, - { - 0x01, "IDE controller", "ide", ide_devices, NULL, -- &ide_config_cb, NULL, -+ NULL, NULL, - }, - { - 0x02, "Floppy disk controller", NULL, NULL, NULL, -@@ -546,7 +622,7 @@ - }, - { - 0x05, "ATA controller", "ata", NULL, NULL, -- &ata_config_cb, NULL, -+ NULL, NULL, - }, - { - 0x80, "misc mass-storage controller", NULL, NULL, NULL, -@@ -646,7 +722,9 @@ - /* VGA 640x480x16 */ - OF_vga_register(device->common.device->name, - device->regions[0] & ~0x0000000F, -- vga_width, vga_height, vga_depth); -+ vga_width, vga_height, vga_depth, -+ device->regions[6] & ~0x0000000F, -+ device->sizes[6]); - } - vga_console_register(); - -@@ -750,6 +828,13 @@ - NULL, &PREP_pci_ops, - }; - -+pci_dev_t grackle_fake_bridge = { -+ 0xFFFF, 0xFFFF, -+ "pci", "pci-bridge", "DEC,21154", "DEC,21154.pci-bridge", -+ -1, -1, -1, -+ NULL, &grackle_pci_ops, -+}; -+ - static pci_dev_t hbrg_devices[] = { - { - 0x106B, 0x0020, NULL, -@@ -758,8 +843,8 @@ - NULL, &uninorth_agp_fake_bridge, - }, - { -- 0x106B, 0x001F, -- NULL, "pci", "AAPL,UniNorth", "uni-north", -+ 0x106B, 0x001F, NULL, -+ "pci", "AAPL,UniNorth", "uni-north", - 3, 2, 1, - NULL, &uninorth_fake_bridge, - }, -@@ -770,10 +855,10 @@ - NULL, &uninorth_fake_bridge, - }, - { -- 0x1011, 0x0026, NULL, -- "pci-bridge", NULL, NULL, -+ 0x1057, 0x0002, "pci", -+ "pci", "MOT,MPC106", "grackle", - 3, 2, 1, -- NULL, &PREP_pci_ops, -+ NULL, &grackle_fake_bridge, - }, - { - 0x1057, 0x4801, NULL, -@@ -1443,7 +1528,14 @@ - } - - static const pci_dev_t misc_pci[] = { -- /* Apple Mac-io controller */ -+ /* Paddington Mac I/O */ -+ { -+ 0x106B, 0x0017, -+ "mac-io", "mac-io", "AAPL,343S1211", "paddington\1heathrow", -+ 1, 1, 1, -+ &macio_config_cb, NULL, -+ }, -+ /* KeyLargo Mac I/O */ - { - 0x106B, 0x0022, - "mac-io", "mac-io", "AAPL,Keylargo", "Keylargo", -@@ -1599,7 +1691,7 @@ - uint8_t min_grant, uint8_t max_latency, - int irq_line) - { -- uint32_t cmd; -+ uint32_t cmd, addr; - int i; - - device->min_grant = min_grant; -@@ -1611,22 +1703,28 @@ - printf("MAP PCI device %d:%d to IRQ %d\n", - device->bus, device->devfn, irq_line); - } -- for (i = 0; i < 6; i++) { -+ for (i = 0; i < 7; i++) { - if ((device->regions[i] & ~0xF) != 0x00000000 && - (device->regions[i] & ~0xF) != 0xFFFFFFF0) { - printf("Map PCI device %d:%d %d to %0x %0x (%s)\n", - device->bus, device->devfn, i, - device->regions[i], device->sizes[i], -- device->regions[i] & 0x00000001 ? "I/O" : "memory"); -+ (device->regions[i] & 0x00000001) && i != 6 ? "I/O" : -+ "memory"); -+ if (i != 6) { - cmd = pci_config_readl(bridge, device->bus, device->devfn, 0x04); - if (device->regions[i] & 0x00000001) - cmd |= 0x00000001; - else - cmd |= 0x00000002; - pci_config_writel(bridge, device->bus, device->devfn, 0x04, cmd); -+ } -+ if (i == 6) -+ addr = 0x30; /* PCI ROM */ -+ else -+ addr = 0x10 + (i * sizeof(uint32_t)); - pci_config_writel(bridge, device->bus, device->devfn, -- 0x10 + (i * sizeof(uint32_t)), -- device->regions[i]); -+ addr, device->regions[i]); - } - } - } -@@ -1900,7 +1998,7 @@ - goto out; - } - ret = (pci_u_t *)newd; -- max_areas = 6; -+ max_areas = 7; - /* register PCI device in OF tree */ - if (bridge->dev.common.type == PCI_FAKE_BRIDGE) { - newd->common.OF_private = -@@ -1927,6 +2025,9 @@ - /* Handle 64 bits memory mapping */ - continue; - } -+ if (i == 6) -+ addr = 0x30; /* PCI ROM */ -+ else - addr = 0x10 + (i * sizeof(uint32_t)); - /* Get region size - * Note: we assume it's always a power of 2 -@@ -1935,7 +2036,7 @@ - smask = pci_config_readl(bridge, bus, devfn, addr); - if (smask == 0x00000000 || smask == 0xFFFFFFFF) - continue; -- if (smask & 0x00000001) { -+ if ((smask & 0x00000001) != 0 && i != 6) { - /* I/O space */ - base = io_base; - /* Align to a minimum of 256 bytes (arbitrary) */ -@@ -1947,6 +2048,8 @@ - /* Align to a minimum of 64 kB (arbitrary) */ - min_align = 1 << 16; - amask = 0x0000000F; -+ if (i == 6) -+ smask |= 1; /* PCI ROM enable */ - } - omask = smask & amask; - smask &= ~amask; -@@ -1980,7 +2083,10 @@ - if (irq_pin > 0) { - /* assign the IRQ */ - irq_pin = ((devfn >> 3) + irq_pin - 1) & 3; -- if (arch == ARCH_PREP) { -+ /* XXX: should base it on the PCI bridge type, not the arch */ -+ switch(arch) { -+ case ARCH_PREP: -+ { - int elcr_port, val; - irq_line = prep_pci_irqs[irq_pin]; - /* set the IRQ to level-sensitive */ -@@ -1988,14 +2094,22 @@ - val = inb(elcr_port); - val |= 1 << (irq_line & 7); - outb(elcr_port, val); -- } else { -+ } -+ break; -+ case ARCH_MAC99: - irq_line = pmac_pci_irqs[irq_pin]; -+ break; -+ case ARCH_HEATHROW: -+ irq_line = heathrow_pci_irqs[irq_pin]; -+ break; -+ default: -+ break; - } - } - update_device: - pci_update_device(bridge, newd, min_grant, max_latency, irq_line); - OF_finalize_pci_device(newd->common.OF_private, bus, devfn, -- newd->regions, newd->sizes); -+ newd->regions, newd->sizes, irq_line); - /* Call special inits if needed */ - if (dev->config_cb != NULL) - (*dev->config_cb)(newd); -@@ -2049,6 +2163,32 @@ - case ARCH_CHRP: - /* TODO */ - break; -+ case ARCH_HEATHROW: -+ dev = pci_find_device(0x06, 0x00, 0xFF, checkv, checkp); -+ if (dev == NULL) -+ return -1; -+ fake_host = pci_add_host(hostp, dev, -+ (0x06 << 24) | (0x00 << 16) | (0xFF << 8)); -+ if (fake_host == NULL) -+ return -1; -+ fake_host->dev.common.type = PCI_FAKE_HOST; -+ dev = &grackle_fake_bridge; -+ if (dev == NULL) -+ goto free_fake_host; -+ fake_bridge = pci_add_bridge(fake_host, 0, 0, dev, -+ (0x06 << 24) | (0x04 << 16) | (0xFF << 8), -+ cfg_base, cfg_len, -+ cfg_base + 0x7ec00000, -+ cfg_base + 0x7ee00000, -+ mem_base, mem_len, -+ io_base, io_len, -+ rbase, rlen, -+ 0, -+ &grackle_pci_ops); -+ if (fake_bridge == NULL) -+ goto free_fake_host; -+ fake_bridge->dev.common.type = PCI_FAKE_BRIDGE; -+ break; - case ARCH_MAC99: - dev = pci_find_device(0x06, 0x00, 0xFF, checkv, checkp); - if (dev == NULL) -@@ -2167,6 +2307,30 @@ - case ARCH_CHRP: - /* TODO */ - break; -+ case ARCH_HEATHROW: -+ cfg_base = 0x80000000; -+ cfg_len = 0x7f000000; -+ mem_base = 0x80000000; -+ mem_len = 0x01000000; -+ io_base = 0xfe000000; -+ io_len = 0x00800000; -+#if 1 -+ rbase = 0xfd000000; -+ rlen = 0x01000000; -+#else -+ rbase = 0x00000000; -+ rlen = 0x01000000; -+#endif -+ if (pci_check_host(&pci_main, cfg_base, cfg_len, -+ mem_base, mem_len, io_base, io_len, rbase, rlen, -+ 0x1057, 0x0002) == 0) { -+ isa_io_base = io_base; -+ busnum++; -+ } -+ for (curh = pci_main; curh->next != NULL; curh = curh->next) -+ continue; -+ pci_check_devices(curh); -+ break; - case ARCH_MAC99: - /* We are supposed to have 3 host bridges: - * - the uninorth AGP bridge at 0xF0000000 diff --git a/pc-bios/openbios-ppc b/pc-bios/openbios-ppc Binary files differindex f4a3a39..8a21389 100644 --- a/pc-bios/openbios-ppc +++ b/pc-bios/openbios-ppc diff --git a/pc-bios/openbios-sparc32 b/pc-bios/openbios-sparc32 Binary files differindex bb7cdfb..d4d00e5 100644 --- a/pc-bios/openbios-sparc32 +++ b/pc-bios/openbios-sparc32 diff --git a/pc-bios/openbios-sparc64 b/pc-bios/openbios-sparc64 Binary files differindex 46b4fdd..4182052 100644 --- a/pc-bios/openbios-sparc64 +++ b/pc-bios/openbios-sparc64 diff --git a/pc-bios/ppc_rom.bin b/pc-bios/ppc_rom.bin Binary files differindex 0ad0282..e7f7693 100644 --- a/pc-bios/ppc_rom.bin +++ b/pc-bios/ppc_rom.bin diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin Binary files differindex 92a9831..a742bff 100644 --- a/pc-bios/slof.bin +++ b/pc-bios/slof.bin diff --git a/qapi-schema.json b/qapi-schema.json index 6c381b7..b68cd44 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -883,6 +883,35 @@ { 'command': 'query-cpus', 'returns': ['CpuInfo'] } ## +# @IOThreadInfo: +# +# Information about an iothread +# +# @id: the identifier of the iothread +# +# @thread-id: ID of the underlying host thread +# +# Since: 2.0 +## +{ 'type': 'IOThreadInfo', + 'data': {'id': 'str', 'thread-id': 'int'} } + +## +# @query-iothreads: +# +# Returns a list of information about each iothread. +# +# Note this list excludes the QEMU main loop thread, which is not declared +# using the -object iothread command-line option. It is always the main thread +# of the process. +# +# Returns: a list of @IOThreadInfo for each iothread +# +# Since: 2.0 +## +{ 'command': 'query-iothreads', 'returns': ['IOThreadInfo'] } + +## # @BlockDeviceInfo: # # Information about the backing device for a block device. @@ -4249,6 +4278,18 @@ '*no-flush': 'bool' } } ## +# @BlockdevDriver +# +# Drivers that are supported in block device operations. +# +# Since: 2.0 +## +{ 'enum': 'BlockdevDriver', + 'data': [ 'file', 'http', 'https', 'ftp', 'ftps', 'tftp', 'vvfat', 'blkdebug', + 'blkverify', 'bochs', 'cloop', 'cow', 'dmg', 'parallels', 'qcow', + 'qcow2', 'qed', 'raw', 'vdi', 'vhdx', 'vmdk', 'vpc', 'quorum' ] } + +## # @BlockdevOptionsBase # # Options that are available for all block devices, independent of the block @@ -4272,7 +4313,7 @@ # Since: 1.7 ## { 'type': 'BlockdevOptionsBase', - 'data': { 'driver': 'str', + 'data': { 'driver': 'BlockdevDriver', '*id': 'str', '*node-name': 'str', '*discard': 'BlockdevDiscardOptions', diff --git a/qdev-monitor.c b/qdev-monitor.c index 6673e3c..9268c87 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -522,7 +522,7 @@ DeviceState *qdev_device_add(QemuOpts *opts) return NULL; } - /* create device, set properties */ + /* create device */ dev = DEVICE(object_new(driver)); if (bus) { @@ -533,11 +533,7 @@ DeviceState *qdev_device_add(QemuOpts *opts) if (id) { dev->id = id; } - if (qemu_opt_foreach(opts, set_property, dev, 1) != 0) { - object_unparent(OBJECT(dev)); - object_unref(OBJECT(dev)); - return NULL; - } + if (dev->id) { object_property_add_child(qdev_get_peripheral(), dev->id, OBJECT(dev), NULL); @@ -549,6 +545,13 @@ DeviceState *qdev_device_add(QemuOpts *opts) g_free(name); } + /* set properties */ + if (qemu_opt_foreach(opts, set_property, dev, 1) != 0) { + object_unparent(OBJECT(dev)); + object_unref(OBJECT(dev)); + return NULL; + } + dev->opts = opts; object_property_set_bool(OBJECT(dev), true, "realized", &err); if (err != NULL) { diff --git a/qemu-char.c b/qemu-char.c index 4d50838..54ed244 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -213,7 +213,7 @@ void qemu_chr_add_handlers(CharDriverState *s, s->chr_read = fd_read; s->chr_event = fd_event; s->handler_opaque = opaque; - if (s->chr_update_read_handler) + if (fe_open && s->chr_update_read_handler) s->chr_update_read_handler(s); if (!s->explicit_fe_open) { @@ -1136,13 +1136,14 @@ static void pty_chr_state(CharDriverState *chr, int connected) if (!s->connected) { s->connected = 1; qemu_chr_be_generic_open(chr); + } + if (!chr->fd_in_tag) { chr->fd_in_tag = io_add_watch_poll(s->fd, pty_chr_read_poll, pty_chr_read, chr); } } } - static void pty_chr_close(struct CharDriverState *chr) { PtyCharDriver *s = chr->opaque; @@ -2509,6 +2510,17 @@ static void tcp_chr_connect(void *opaque) qemu_chr_be_generic_open(chr); } +static void tcp_chr_update_read_handler(CharDriverState *chr) +{ + TCPCharDriver *s = chr->opaque; + + remove_fd_in_watch(chr); + if (s->chan) { + chr->fd_in_tag = io_add_watch_poll(s->chan, tcp_chr_read_poll, + tcp_chr_read, chr); + } +} + #define IACSET(x,a,b,c) x[0] = a; x[1] = b; x[2] = c; static void tcp_chr_telnet_init(int fd) { @@ -2664,6 +2676,7 @@ static CharDriverState *qemu_chr_open_socket_fd(int fd, bool do_nodelay, chr->get_msgfd = tcp_get_msgfd; chr->chr_add_client = tcp_chr_add_client; chr->chr_add_watch = tcp_chr_add_watch; + chr->chr_update_read_handler = tcp_chr_update_read_handler; /* be isn't opened until we get a connection */ chr->explicit_be_open = true; diff --git a/qemu-file.c b/qemu-file.c index f074af1..e5ec798 100644 --- a/qemu-file.c +++ b/qemu-file.c @@ -105,7 +105,7 @@ static int stdio_put_buffer(void *opaque, const uint8_t *buf, int64_t pos, res = fwrite(buf, 1, size, s->stdio_file); if (res != size) { - return -EIO; /* fake errno value */ + return -errno; } return res; } diff --git a/qemu-io-cmds.c b/qemu-io-cmds.c index f1de24c..60c1ceb 100644 --- a/qemu-io-cmds.c +++ b/qemu-io-cmds.c @@ -16,7 +16,7 @@ #define CMD_NOFILE_OK 0x01 -int qemuio_misalign; +bool qemuio_misalign; static cmdinfo_t *cmdtab; static int ncmds; @@ -1087,7 +1087,7 @@ writev_help(void) " writes a range of bytes from the given offset source from multiple buffers\n" "\n" " Example:\n" -" 'write 512 1k 1k' - writes 2 kilobytes at 512 bytes into the open file\n" +" 'writev 512 1k 1k' - writes 2 kilobytes at 512 bytes into the open file\n" "\n" " Writes into a segment of the currently open file, using a buffer\n" " filled with a set pattern (0xcdcdcdcd).\n" @@ -24,10 +24,9 @@ #define CMD_NOFILE_OK 0x01 -char *progname; +static char *progname; -BlockDriverState *qemuio_bs; -extern int qemuio_misalign; +static BlockDriverState *qemuio_bs; /* qemu-io commands passed using -c */ static int ncmdline; @@ -194,10 +193,11 @@ static const cmdinfo_t quit_cmd = { static void usage(const char *name) { printf( -"Usage: %s [-h] [-V] [-rsnm] [-c cmd] ... [file]\n" +"Usage: %s [-h] [-V] [-rsnm] [-c STRING] ... [file]\n" "QEMU Disk exerciser\n" "\n" -" -c, --cmd command to execute\n" +" -c, --cmd STRING execute command with its arguments\n" +" from the given string\n" " -r, --read-only export read-only\n" " -s, --snapshot use snapshot file\n" " -n, --nocache disable host cache\n" @@ -208,8 +208,10 @@ static void usage(const char *name) " -T, --trace FILE enable trace events listed in the given file\n" " -h, --help display this help and exit\n" " -V, --version output version information and exit\n" +"\n" +"See '%s -c help' for information on available commands." "\n", - name); + name, name); } static char *get_prompt(void) @@ -408,7 +410,7 @@ int main(int argc, char **argv) readonly = 1; break; case 'm': - qemuio_misalign = 1; + qemuio_misalign = true; break; case 'g': growable = 1; @@ -288,19 +288,19 @@ static void *nbd_client_thread(void *arg) ret = nbd_receive_negotiate(sock, NULL, &nbdflags, &size, &blocksize); if (ret < 0) { - goto out; + goto out_socket; } fd = open(device, O_RDWR); if (fd < 0) { /* Linux-only, we can use %m in printf. */ fprintf(stderr, "Failed to open %s: %m", device); - goto out; + goto out_socket; } ret = nbd_init(fd, sock, nbdflags, size, blocksize); if (ret < 0) { - goto out; + goto out_fd; } /* update partition table */ @@ -316,12 +316,16 @@ static void *nbd_client_thread(void *arg) ret = nbd_client(fd); if (ret) { - goto out; + goto out_fd; } close(fd); kill(getpid(), SIGTERM); return (void *) EXIT_SUCCESS; +out_fd: + close(fd); +out_socket: + closesocket(sock); out: kill(getpid(), SIGTERM); return (void *) EXIT_FAILURE; @@ -355,6 +359,11 @@ static void nbd_accept(void *opaque) socklen_t addr_len = sizeof(addr); int fd = accept(server_fd, (struct sockaddr *)&addr, &addr_len); + if (fd < 0) { + perror("accept"); + return; + } + if (state >= TERMINATE) { close(fd); return; diff --git a/qemu-options.hx b/qemu-options.hx index 068da2d..ee5437b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -810,6 +810,7 @@ ETEXI DEF("display", HAS_ARG, QEMU_OPTION_display, "-display sdl[,frame=on|off][,alt_grab=on|off][,ctrl_grab=on|off]\n" " [,window_close=on|off]|curses|none|\n" + " gtk[,grab_on_hover=on|off]|\n" " vnc=<display>[,<optargs>]\n" " select display type\n", QEMU_ARCH_ALL) STEXI @@ -833,6 +834,10 @@ graphics card, but its output will not be displayed to the QEMU user. This option differs from the -nographic option in that it only affects what is done with video output; -nographic also changes the destination of the serial and parallel port data. +@item gtk +Display video output in a GTK window. This interface provides drop-down +menus and other UI elements to configure and control the VM during +runtime. @item vnc Start a VNC server on display <arg> @end table @@ -22,7 +22,9 @@ mech_list: digest-md5 # Some older builds of MIT kerberos on Linux ignore this option & # instead need KRB5_KTNAME env var. # For modern Linux, and other OS, this should be sufficient -keytab: /etc/qemu/krb5.tab +# +# There is no default value here, uncomment if you need this +#keytab: /etc/qemu/krb5.tab # If using digest-md5 for username/passwds, then this is the file # containing the passwds. Use 'saslpasswd2 -a qemu [username]' diff --git a/qmp-commands.hx b/qmp-commands.hx index d982cd6..a22621f 100644 --- a/qmp-commands.hx +++ b/qmp-commands.hx @@ -2327,6 +2327,45 @@ EQMP }, SQMP +query-iothreads +--------------- + +Returns a list of information about each iothread. + +Note this list excludes the QEMU main loop thread, which is not declared +using the -object iothread command-line option. It is always the main thread +of the process. + +Return a json-array. Each iothread is represented by a json-object, which contains: + +- "id": name of iothread (json-str) +- "thread-id": ID of the underlying host thread (json-int) + +Example: + +-> { "execute": "query-iothreads" } +<- { + "return":[ + { + "id":"iothread0", + "thread-id":3134 + }, + { + "id":"iothread1", + "thread-id":3135 + } + ] + } + +EQMP + + { + .name = "query-iothreads", + .args_type = "", + .mhandler.cmd_new = qmp_marshal_input_query_iothreads, + }, + +SQMP query-pci --------- @@ -114,8 +114,11 @@ void qmp_cpu(int64_t index, Error **errp) void qmp_cpu_add(int64_t id, Error **errp) { - if (current_machine->hot_add_cpu) { - current_machine->hot_add_cpu(id, errp); + MachineClass *mc; + + mc = MACHINE_GET_CLASS(current_machine); + if (mc->qemu_machine->hot_add_cpu) { + mc->qemu_machine->hot_add_cpu(id, errp); } else { error_setg(errp, "Not supported"); } @@ -1,7 +1,7 @@ /* * QEMU CPU model * - * Copyright (c) 2012 SUSE LINUX Products GmbH + * Copyright (c) 2012-2014 SUSE LINUX Products GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -23,6 +23,7 @@ #include "sysemu/kvm.h" #include "qemu/notify.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "sysemu/sysemu.h" bool cpu_exists(int64_t id) @@ -39,6 +40,46 @@ bool cpu_exists(int64_t id) return false; } +CPUState *cpu_generic_init(const char *typename, const char *cpu_model) +{ + char *str, *name, *featurestr; + CPUState *cpu; + ObjectClass *oc; + CPUClass *cc; + Error *err = NULL; + + str = g_strdup(cpu_model); + name = strtok(str, ","); + + oc = cpu_class_by_name(typename, name); + if (oc == NULL) { + g_free(str); + return NULL; + } + + cpu = CPU(object_new(object_class_get_name(oc))); + cc = CPU_GET_CLASS(cpu); + + featurestr = strtok(NULL, ","); + cc->parse_features(cpu, featurestr, &err); + g_free(str); + if (err != NULL) { + goto out; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + +out: + if (err != NULL) { + error_report("%s", error_get_pretty(err)); + error_free(err); + object_unref(OBJECT(cpu)); + return NULL; + } + + return cpu; +} + bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc = CPU_GET_CLASS(cpu); @@ -195,10 +236,20 @@ static void cpu_common_reset(CPUState *cpu) log_cpu_state(cpu, cc->reset_dump_flags); } - cpu->exit_request = 0; cpu->interrupt_request = 0; cpu->current_tb = NULL; cpu->halted = 0; + cpu->mem_io_pc = 0; + cpu->mem_io_vaddr = 0; + cpu->icount_extra = 0; + cpu->icount_decr.u32 = 0; + cpu->can_do_io = 0; + memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *)); +} + +static bool cpu_common_has_work(CPUState *cs) +{ + return false; } ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) @@ -213,6 +264,34 @@ static ObjectClass *cpu_common_class_by_name(const char *cpu_model) return NULL; } +static void cpu_common_parse_features(CPUState *cpu, char *features, + Error **errp) +{ + char *featurestr; /* Single "key=value" string being parsed */ + char *val; + Error *err = NULL; + + featurestr = features ? strtok(features, ",") : NULL; + + while (featurestr) { + val = strchr(featurestr, '='); + if (val) { + *val = 0; + val++; + object_property_parse(OBJECT(cpu), val, featurestr, &err); + if (err) { + error_propagate(errp, err); + return; + } + } else { + error_setg(errp, "Expected key=value format, found %s.", + featurestr); + return; + } + featurestr = strtok(NULL, ","); + } +} + static void cpu_common_realizefn(DeviceState *dev, Error **errp) { CPUState *cpu = CPU(dev); @@ -243,8 +322,10 @@ static void cpu_class_init(ObjectClass *klass, void *data) CPUClass *k = CPU_CLASS(klass); k->class_by_name = cpu_common_class_by_name; + k->parse_features = cpu_common_parse_features; k->reset = cpu_common_reset; k->get_arch_id = cpu_common_get_arch_id; + k->has_work = cpu_common_has_work; k->get_paging_enabled = cpu_common_get_paging_enabled; k->get_memory_mapping = cpu_common_get_memory_mapping; k->write_elf32_qemunote = cpu_common_write_elf32_qemunote; diff --git a/qom/object.c b/qom/object.c index 660859c..f4de619 100644 --- a/qom/object.c +++ b/qom/object.c @@ -1023,10 +1023,23 @@ out: g_free(type); } +void object_property_allow_set_link(Object *obj, const char *name, + Object *val, Error **errp) +{ + /* Allow the link to be set, always */ +} + +typedef struct { + Object **child; + void (*check)(Object *, const char *, Object *, Error **); + ObjectPropertyLinkFlags flags; +} LinkProperty; + static void object_get_link_property(Object *obj, Visitor *v, void *opaque, const char *name, Error **errp) { - Object **child = opaque; + LinkProperty *lprop = opaque; + Object **child = lprop->child; gchar *path; if (*child) { @@ -1039,102 +1052,166 @@ static void object_get_link_property(Object *obj, Visitor *v, void *opaque, } } -static void object_set_link_property(Object *obj, Visitor *v, void *opaque, - const char *name, Error **errp) +/* + * object_resolve_link: + * + * Lookup an object and ensure its type matches the link property type. This + * is similar to object_resolve_path() except type verification against the + * link property is performed. + * + * Returns: The matched object or NULL on path lookup failures. + */ +static Object *object_resolve_link(Object *obj, const char *name, + const char *path, Error **errp) { - Object **child = opaque; - Object *old_target; - bool ambiguous = false; const char *type; - char *path; gchar *target_type; + bool ambiguous = false; + Object *target; + /* Go from link<FOO> to FOO. */ type = object_property_get_type(obj, name, NULL); + target_type = g_strndup(&type[5], strlen(type) - 6); + target = object_resolve_path_type(path, target_type, &ambiguous); + + if (ambiguous) { + error_set(errp, QERR_AMBIGUOUS_PATH, path); + } else if (!target) { + target = object_resolve_path(path, &ambiguous); + if (target || ambiguous) { + error_set(errp, QERR_INVALID_PARAMETER_TYPE, name, target_type); + } else { + error_set(errp, QERR_DEVICE_NOT_FOUND, path); + } + target = NULL; + } + g_free(target_type); - visit_type_str(v, &path, name, errp); - - old_target = *child; - *child = NULL; + return target; +} - if (strcmp(path, "") != 0) { - Object *target; +static void object_set_link_property(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + Error *local_err = NULL; + LinkProperty *prop = opaque; + Object **child = prop->child; + Object *old_target = *child; + Object *new_target = NULL; + char *path = NULL; - /* Go from link<FOO> to FOO. */ - target_type = g_strndup(&type[5], strlen(type) - 6); - target = object_resolve_path_type(path, target_type, &ambiguous); + visit_type_str(v, &path, name, &local_err); - if (ambiguous) { - error_set(errp, QERR_AMBIGUOUS_PATH, path); - } else if (target) { - object_ref(target); - *child = target; - } else { - target = object_resolve_path(path, &ambiguous); - if (target || ambiguous) { - error_set(errp, QERR_INVALID_PARAMETER_TYPE, name, target_type); - } else { - error_set(errp, QERR_DEVICE_NOT_FOUND, path); - } - } - g_free(target_type); + if (!local_err && strcmp(path, "") != 0) { + new_target = object_resolve_link(obj, name, path, &local_err); } g_free(path); + if (local_err) { + error_propagate(errp, local_err); + return; + } + prop->check(obj, name, new_target, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (new_target) { + object_ref(new_target); + } + *child = new_target; if (old_target != NULL) { object_unref(old_target); } } +static void object_release_link_property(Object *obj, const char *name, + void *opaque) +{ + LinkProperty *prop = opaque; + + if ((prop->flags & OBJ_PROP_LINK_UNREF_ON_RELEASE) && *prop->child) { + object_unref(*prop->child); + } + g_free(prop); +} + void object_property_add_link(Object *obj, const char *name, const char *type, Object **child, + void (*check)(Object *, const char *, + Object *, Error **), + ObjectPropertyLinkFlags flags, Error **errp) { + Error *local_err = NULL; + LinkProperty *prop = g_malloc(sizeof(*prop)); gchar *full_type; + prop->child = child; + prop->check = check; + prop->flags = flags; + full_type = g_strdup_printf("link<%s>", type); object_property_add(obj, name, full_type, object_get_link_property, - object_set_link_property, - NULL, child, errp); + check ? object_set_link_property : NULL, + object_release_link_property, + prop, + &local_err); + if (local_err) { + error_propagate(errp, local_err); + g_free(prop); + } g_free(full_type); } +gchar *object_get_canonical_path_component(Object *obj) +{ + ObjectProperty *prop = NULL; + + g_assert(obj); + g_assert(obj->parent != NULL); + + QTAILQ_FOREACH(prop, &obj->parent->properties, node) { + if (!object_property_is_child(prop)) { + continue; + } + + if (prop->opaque == obj) { + return g_strdup(prop->name); + } + } + + /* obj had a parent but was not a child, should never happen */ + g_assert_not_reached(); + return NULL; +} + gchar *object_get_canonical_path(Object *obj) { Object *root = object_get_root(); - char *newpath = NULL, *path = NULL; + char *newpath, *path = NULL; while (obj != root) { - ObjectProperty *prop = NULL; - - g_assert(obj->parent != NULL); - - QTAILQ_FOREACH(prop, &obj->parent->properties, node) { - if (!object_property_is_child(prop)) { - continue; - } + char *component = object_get_canonical_path_component(obj); - if (prop->opaque == obj) { - if (path) { - newpath = g_strdup_printf("%s/%s", prop->name, path); - g_free(path); - path = newpath; - } else { - path = g_strdup(prop->name); - } - break; - } + if (path) { + newpath = g_strdup_printf("%s/%s", component, path); + g_free(component); + g_free(path); + path = newpath; + } else { + path = component; } - g_assert(prop != NULL); - obj = obj->parent; } - newpath = g_strdup_printf("/%s", path); + newpath = g_strdup_printf("/%s", path ? path : ""); g_free(path); return newpath; @@ -1293,6 +1370,7 @@ void object_property_add_str(Object *obj, const char *name, void (*set)(Object *, const char *, Error **), Error **errp) { + Error *local_err = NULL; StringProperty *prop = g_malloc0(sizeof(*prop)); prop->get = get; @@ -1302,7 +1380,11 @@ void object_property_add_str(Object *obj, const char *name, get ? property_get_str : NULL, set ? property_set_str : NULL, property_release_str, - prop, errp); + prop, &local_err); + if (local_err) { + error_propagate(errp, local_err); + g_free(prop); + } } typedef struct BoolProperty @@ -1349,6 +1431,7 @@ void object_property_add_bool(Object *obj, const char *name, void (*set)(Object *, bool, Error **), Error **errp) { + Error *local_err = NULL; BoolProperty *prop = g_malloc0(sizeof(*prop)); prop->get = get; @@ -1358,7 +1441,11 @@ void object_property_add_bool(Object *obj, const char *name, get ? property_get_bool : NULL, set ? property_set_bool : NULL, property_release_bool, - prop, errp); + prop, &local_err); + if (local_err) { + error_propagate(errp, local_err); + g_free(prop); + } } static char *qdev_get_type(Object *obj, Error **errp) diff --git a/roms/SLOF b/roms/SLOF -Subproject e2e8ac901e617573ea383f9cffd136146d0675a +Subproject af6b7bf5879b6cd6825de2a107cb0e3219fb1df diff --git a/roms/openbios b/roms/openbios -Subproject 888126272f92294b0da45158393f1b862742cf6 +Subproject 1ac3fb92c109f5545d373a0576b87750c53cce1 diff --git a/roms/openhackware b/roms/openhackware new file mode 160000 +Subproject 1af7e55425e58a6dcb5133b092fcf16f8c654fb @@ -23,8 +23,8 @@ QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(*D)/$(*F).d QEMU_INCLUDES += -I$(<D) -I$(@D) maybe-add = $(filter-out $1, $2) $1 -extract-libs = $(strip $(sort $(foreach o,$1,$($o-libs)) \ - $(foreach o,$(call expand-objs,$1),$($o-libs)))) +extract-libs = $(strip $(sort $(foreach o,$1,$($o-libs))) \ + $(foreach o,$(call expand-objs,$1),$($o-libs))) expand-objs = $(strip $(sort $(filter %.o,$1)) \ $(foreach o,$(filter %.mo,$1),$($o-objs)) \ $(filter-out %.o %.mo,$1)) @@ -527,13 +527,13 @@ int qemu_savevm_state_iterate(QEMUFile *f) if (qemu_file_rate_limit(f)) { return 0; } - trace_savevm_section_start(); + trace_savevm_section_start(se->idstr, se->section_id); /* Section type */ qemu_put_byte(f, QEMU_VM_SECTION_PART); qemu_put_be32(f, se->section_id); ret = se->ops->save_live_iterate(f, se->opaque); - trace_savevm_section_end(se->section_id); + trace_savevm_section_end(se->idstr, se->section_id); if (ret < 0) { qemu_file_set_error(f, ret); @@ -565,13 +565,13 @@ void qemu_savevm_state_complete(QEMUFile *f) continue; } } - trace_savevm_section_start(); + trace_savevm_section_start(se->idstr, se->section_id); /* Section type */ qemu_put_byte(f, QEMU_VM_SECTION_END); qemu_put_be32(f, se->section_id); ret = se->ops->save_live_complete(f, se->opaque); - trace_savevm_section_end(se->section_id); + trace_savevm_section_end(se->idstr, se->section_id); if (ret < 0) { qemu_file_set_error(f, ret); return; @@ -584,7 +584,7 @@ void qemu_savevm_state_complete(QEMUFile *f) if ((!se->ops || !se->ops->save_state) && !se->vmsd) { continue; } - trace_savevm_section_start(); + trace_savevm_section_start(se->idstr, se->section_id); /* Section type */ qemu_put_byte(f, QEMU_VM_SECTION_FULL); qemu_put_be32(f, se->section_id); @@ -598,7 +598,7 @@ void qemu_savevm_state_complete(QEMUFile *f) qemu_put_be32(f, se->version_id); vmstate_save(f, se); - trace_savevm_section_end(se->section_id); + trace_savevm_section_end(se->idstr, se->section_id); } qemu_put_byte(f, QEMU_VM_EOF); diff --git a/scripts/make-release b/scripts/make-release index 196c755..186358d 100755 --- a/scripts/make-release +++ b/scripts/make-release @@ -18,7 +18,7 @@ git clone "${src}" ${destination} pushd ${destination} git checkout "v${version}" git submodule update --init -rm -rf .git roms/*/.git +rm -rf .git roms/*/.git dtc/.git pixman/.git popd tar cfj ${destination}.tar.bz2 ${destination} rm -rf ${destination} diff --git a/scripts/qapi-types.py b/scripts/qapi-types.py index 2c6e0dc..10864ef 100644 --- a/scripts/qapi-types.py +++ b/scripts/qapi-types.py @@ -127,16 +127,6 @@ const char *%(name)s_lookup[] = { ''') return ret -def generate_enum_name(name): - if name.isupper(): - return c_fun(name, False) - new_name = '' - for c in c_fun(name, False): - if c.isupper(): - new_name += '_' - new_name += c - return new_name.lstrip('_').upper() - def generate_enum(name, values): lookup_decl = mcgen(''' extern const char *%(name)s_lookup[]; @@ -154,11 +144,11 @@ typedef enum %(name)s i = 0 for value in enum_values: + enum_full_value = generate_enum_full_value(name, value) enum_decl += mcgen(''' - %(abbrev)s_%(value)s = %(i)d, + %(enum_full_value)s = %(i)d, ''', - abbrev=de_camel_case(name).upper(), - value=generate_enum_name(value), + enum_full_value = enum_full_value, i=i) i += 1 @@ -211,14 +201,21 @@ def generate_union(expr): base = expr.get('base') discriminator = expr.get('discriminator') + enum_define = discriminator_find_enum_define(expr) + if enum_define: + discriminator_type_name = enum_define['enum_name'] + else: + discriminator_type_name = '%sKind' % (name) + ret = mcgen(''' struct %(name)s { - %(name)sKind kind; + %(discriminator_type_name)s kind; union { void *data; ''', - name=name) + name=name, + discriminator_type_name=discriminator_type_name) for key in typeinfo: ret += mcgen(''' @@ -399,8 +396,11 @@ for expr in exprs: fdef.write(generate_enum_lookup(expr['enum'], expr['data'])) elif expr.has_key('union'): ret += generate_fwd_struct(expr['union'], expr['data']) + "\n" - ret += generate_enum('%sKind' % expr['union'], expr['data'].keys()) - fdef.write(generate_enum_lookup('%sKind' % expr['union'], expr['data'].keys())) + enum_define = discriminator_find_enum_define(expr) + if not enum_define: + ret += generate_enum('%sKind' % expr['union'], expr['data'].keys()) + fdef.write(generate_enum_lookup('%sKind' % expr['union'], + expr['data'].keys())) if expr.get('discriminator') == {}: fdef.write(generate_anon_union_qtypes(expr)) else: diff --git a/scripts/qapi-visit.py b/scripts/qapi-visit.py index c6de9ae..45ce3a9 100644 --- a/scripts/qapi-visit.py +++ b/scripts/qapi-visit.py @@ -214,18 +214,22 @@ void visit_type_%(name)s(Visitor *m, %(name)s ** obj, const char *name, Error ** ''', name=name) + # For anon union, always use the default enum type automatically generated + # as "'%sKind' % (name)" + disc_type = '%sKind' % (name) + for key in members: assert (members[key] in builtin_types or find_struct(members[key]) or find_union(members[key])), "Invalid anonymous union member" + enum_full_value = generate_enum_full_value(disc_type, key) ret += mcgen(''' - case %(abbrev)s_KIND_%(enum)s: + case %(enum_full_value)s: visit_type_%(c_type)s(m, &(*obj)->%(c_name)s, name, &err); break; ''', - abbrev = de_camel_case(name).upper(), - enum = c_fun(de_camel_case(key),False).upper(), + enum_full_value = enum_full_value, c_type = type_name(members[key]), c_name = c_fun(key)) @@ -255,7 +259,16 @@ def generate_visit_union(expr): assert not base return generate_visit_anon_union(name, members) - ret = generate_visit_enum('%sKind' % name, members.keys()) + enum_define = discriminator_find_enum_define(expr) + if enum_define: + # Use the enum type as discriminator + ret = "" + disc_type = enum_define['enum_name'] + else: + # There will always be a discriminator in the C switch code, by default it + # is an enum type generated silently as "'%sKind' % (name)" + ret = generate_visit_enum('%sKind' % name, members.keys()) + disc_type = '%sKind' % (name) if base: base_fields = find_struct(base)['data'] @@ -291,15 +304,16 @@ void visit_type_%(name)s(Visitor *m, %(name)s ** obj, const char *name, Error ** pop_indent() if not discriminator: - desc_type = "type" + disc_key = "type" else: - desc_type = discriminator + disc_key = discriminator ret += mcgen(''' - visit_type_%(name)sKind(m, &(*obj)->kind, "%(type)s", &err); + visit_type_%(disc_type)s(m, &(*obj)->kind, "%(disc_key)s", &err); if (!err) { switch ((*obj)->kind) { ''', - name=name, type=desc_type) + disc_type = disc_type, + disc_key = disc_key) for key in members: if not discriminator: @@ -313,13 +327,13 @@ void visit_type_%(name)s(Visitor *m, %(name)s ** obj, const char *name, Error ** visit_end_implicit_struct(m, &err); }''' + enum_full_value = generate_enum_full_value(disc_type, key) ret += mcgen(''' - case %(abbrev)s_KIND_%(enum)s: + case %(enum_full_value)s: ''' + fmt + ''' break; ''', - abbrev = de_camel_case(name).upper(), - enum = c_fun(de_camel_case(key),False).upper(), + enum_full_value = enum_full_value, c_type=type_name(members[key]), c_name=c_fun(key)) @@ -510,7 +524,11 @@ for expr in exprs: ret += generate_visit_list(expr['union'], expr['data']) fdef.write(ret) - ret = generate_decl_enum('%sKind' % expr['union'], expr['data'].keys()) + enum_define = discriminator_find_enum_define(expr) + ret = "" + if not enum_define: + ret = generate_decl_enum('%sKind' % expr['union'], + expr['data'].keys()) ret += generate_declaration(expr['union'], expr['data']) fdecl.write(ret) elif expr.has_key('enum'): diff --git a/scripts/qapi.py b/scripts/qapi.py index f3c2a20..b474c39 100644 --- a/scripts/qapi.py +++ b/scripts/qapi.py @@ -39,12 +39,10 @@ class QAPISchemaError(Exception): def __init__(self, schema, msg): self.fp = schema.fp self.msg = msg - self.line = self.col = 1 - for ch in schema.src[0:schema.pos]: - if ch == '\n': - self.line += 1 - self.col = 1 - elif ch == '\t': + self.col = 1 + self.line = schema.line + for ch in schema.src[schema.line_pos:schema.pos]: + if ch == '\t': self.col = (self.col + 7) % 8 + 1 else: self.col += 1 @@ -52,6 +50,15 @@ class QAPISchemaError(Exception): def __str__(self): return "%s:%s:%s: %s" % (self.fp.name, self.line, self.col, self.msg) +class QAPIExprError(Exception): + def __init__(self, expr_info, msg): + self.fp = expr_info['fp'] + self.line = expr_info['line'] + self.msg = msg + + def __str__(self): + return "%s:%s: %s" % (self.fp.name, self.line, self.msg) + class QAPISchema: def __init__(self, fp): @@ -60,11 +67,16 @@ class QAPISchema: if self.src == '' or self.src[-1] != '\n': self.src += '\n' self.cursor = 0 + self.line = 1 + self.line_pos = 0 self.exprs = [] self.accept() while self.tok != None: - self.exprs.append(self.get_expr(False)) + expr_info = {'fp': fp, 'line': self.line} + expr_elem = {'expr': self.get_expr(False), + 'info': expr_info} + self.exprs.append(expr_elem) def accept(self): while True: @@ -100,6 +112,8 @@ class QAPISchema: if self.cursor == len(self.src): self.tok = None return + self.line += 1 + self.line_pos = self.cursor elif not self.tok.isspace(): raise QAPISchemaError(self, 'Stray "%s"' % self.tok) @@ -116,6 +130,8 @@ class QAPISchema: if self.tok != ':': raise QAPISchemaError(self, 'Expected ":"') self.accept() + if key in expr: + raise QAPISchemaError(self, 'Duplicate key "%s"' % key) expr[key] = self.get_expr(True) if self.tok == '}': self.accept() @@ -158,6 +174,95 @@ class QAPISchema: raise QAPISchemaError(self, 'Expected "{", "[" or string') return expr +def find_base_fields(base): + base_struct_define = find_struct(base) + if not base_struct_define: + return None + return base_struct_define['data'] + +# Return the discriminator enum define if discriminator is specified as an +# enum type, otherwise return None. +def discriminator_find_enum_define(expr): + base = expr.get('base') + discriminator = expr.get('discriminator') + + if not (discriminator and base): + return None + + base_fields = find_base_fields(base) + if not base_fields: + return None + + discriminator_type = base_fields.get(discriminator) + if not discriminator_type: + return None + + return find_enum(discriminator_type) + +def check_union(expr, expr_info): + name = expr['union'] + base = expr.get('base') + discriminator = expr.get('discriminator') + members = expr['data'] + + # If the object has a member 'base', its value must name a complex type. + if base: + base_fields = find_base_fields(base) + if not base_fields: + raise QAPIExprError(expr_info, + "Base '%s' is not a valid type" + % base) + + # If the union object has no member 'discriminator', it's an + # ordinary union. + if not discriminator: + enum_define = None + + # Else if the value of member 'discriminator' is {}, it's an + # anonymous union. + elif discriminator == {}: + enum_define = None + + # Else, it's a flat union. + else: + # The object must have a member 'base'. + if not base: + raise QAPIExprError(expr_info, + "Flat union '%s' must have a base field" + % name) + # The value of member 'discriminator' must name a member of the + # base type. + discriminator_type = base_fields.get(discriminator) + if not discriminator_type: + raise QAPIExprError(expr_info, + "Discriminator '%s' is not a member of base " + "type '%s'" + % (discriminator, base)) + enum_define = find_enum(discriminator_type) + # Do not allow string discriminator + if not enum_define: + raise QAPIExprError(expr_info, + "Discriminator '%s' must be of enumeration " + "type" % discriminator) + + # Check every branch + for (key, value) in members.items(): + # If this named member's value names an enum type, then all members + # of 'data' must also be members of the enum type. + if enum_define and not key in enum_define['enum_values']: + raise QAPIExprError(expr_info, + "Discriminator value '%s' is not found in " + "enum '%s'" % + (key, enum_define["enum_name"])) + # Todo: add checking for values. Key is checked as above, value can be + # also checked here, but we need more functions to handle array case. + +def check_exprs(schema): + for expr_elem in schema.exprs: + expr = expr_elem['expr'] + if expr.has_key('union'): + check_union(expr, expr_elem['info']) + def parse_schema(fp): try: schema = QAPISchema(fp) @@ -167,16 +272,29 @@ def parse_schema(fp): exprs = [] - for expr in schema.exprs: + for expr_elem in schema.exprs: + expr = expr_elem['expr'] if expr.has_key('enum'): - add_enum(expr['enum']) + add_enum(expr['enum'], expr['data']) elif expr.has_key('union'): add_union(expr) - add_enum('%sKind' % expr['union']) elif expr.has_key('type'): add_struct(expr) exprs.append(expr) + # Try again for hidden UnionKind enum + for expr_elem in schema.exprs: + expr = expr_elem['expr'] + if expr.has_key('union'): + if not discriminator_find_enum_define(expr): + add_enum('%sKind' % expr['union']) + + try: + check_exprs(schema) + except QAPIExprError, e: + print >>sys.stderr, e + exit(1) + return exprs def parse_args(typeinfo): @@ -289,13 +407,19 @@ def find_union(name): return union return None -def add_enum(name): +def add_enum(name, enum_values = None): global enum_types - enum_types.append(name) + enum_types.append({"enum_name": name, "enum_values": enum_values}) -def is_enum(name): +def find_enum(name): global enum_types - return (name in enum_types) + for enum in enum_types: + if enum['enum_name'] == name: + return enum + return None + +def is_enum(name): + return find_enum(name) != None def c_type(name): if name == 'str': @@ -373,3 +497,30 @@ def guardend(name): ''', name=guardname(name)) + +# ENUMName -> ENUM_NAME, EnumName1 -> ENUM_NAME1 +# ENUM_NAME -> ENUM_NAME, ENUM_NAME1 -> ENUM_NAME1, ENUM_Name2 -> ENUM_NAME2 +# ENUM24_Name -> ENUM24_NAME +def _generate_enum_string(value): + c_fun_str = c_fun(value, False) + if value.isupper(): + return c_fun_str + + new_name = '' + l = len(c_fun_str) + for i in range(l): + c = c_fun_str[i] + # When c is upper and no "_" appears before, do more checks + if c.isupper() and (i > 0) and c_fun_str[i - 1] != "_": + # Case 1: next string is lower + # Case 2: previous string is digit + if (i < (l - 1) and c_fun_str[i + 1].islower()) or \ + c_fun_str[i - 1].isdigit(): + new_name += '_' + new_name += c + return new_name.lstrip('_').upper() + +def generate_enum_full_value(enum_name, enum_value): + abbrev_string = _generate_enum_string(enum_name) + value_string = _generate_enum_string(enum_value) + return "%s_%s" % (abbrev_string, value_string) diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 0da2618..289b1a3 100644 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -41,6 +41,9 @@ if [ $cpu != "arm" ] ; then echo ':arm:M::\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x28\x00:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff:/usr/local/bin/qemu-arm:' > /proc/sys/fs/binfmt_misc/register echo ':armeb:M::\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x28:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff:/usr/local/bin/qemu-armeb:' > /proc/sys/fs/binfmt_misc/register fi +if [ $cpu != "aarch64" ] ; then + echo ':aarch64:M::\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xb7\x00:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff:/usr/local/bin/qemu-aarch64:' > /proc/sys/fs/binfmt_misc/register +fi if [ $cpu != "sparc" ] ; then echo ':sparc:M::\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x02:\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff:/usr/local/bin/qemu-sparc:' > /proc/sys/fs/binfmt_misc/register fi diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs index df3aa7a..5ed1d38 100644 --- a/stubs/Makefile.objs +++ b/stubs/Makefile.objs @@ -18,7 +18,9 @@ stub-obj-y += mon-print-filename.o stub-obj-y += mon-protocol-event.o stub-obj-y += mon-set-error.o stub-obj-y += pci-drive-hot-add.o +stub-obj-y += qtest.o stub-obj-y += reset.o +stub-obj-y += runstate-check.o stub-obj-y += set-fd-handler.o stub-obj-y += slirp.o stub-obj-y += sysbus.o diff --git a/stubs/qtest.c b/stubs/qtest.c new file mode 100644 index 0000000..e671ed8 --- /dev/null +++ b/stubs/qtest.c @@ -0,0 +1,14 @@ +/* + * qtest stubs + * + * Copyright (c) 2014 Linaro Limited + * Written by Peter Maydell + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu-common.h" + +/* Needed for qtest_allowed() */ +bool qtest_allowed; diff --git a/stubs/runstate-check.c b/stubs/runstate-check.c new file mode 100644 index 0000000..bd2e375 --- /dev/null +++ b/stubs/runstate-check.c @@ -0,0 +1,6 @@ +#include "sysemu/sysemu.h" + +bool runstate_check(RunState state) +{ + return state == RUN_STATE_PRELAUNCH; +} diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index a0d5d5b..7ec46b9 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -31,6 +31,21 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +static bool alpha_cpu_has_work(CPUState *cs) +{ + /* Here we are checking to see if the CPU should wake up from HALT. + We will have gotten into this state only for WTINT from PALmode. */ + /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU + asleep even if (some) interrupts have been asserted. For now, + assume that if a CPU really wants to stay asleep, it will mask + interrupts at the chipset level, which will prevent these bits + from being set in the first place. */ + return cs->interrupt_request & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); +} + static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -243,7 +258,7 @@ static void alpha_cpu_initfn(Object *obj) cs->env_ptr = env; cpu_exec_init(env); - tlb_flush(env, 1); + tlb_flush(cs, 1); alpha_translate_init(); @@ -267,12 +282,15 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) dc->realize = alpha_cpu_realizefn; cc->class_by_name = alpha_cpu_class_by_name; + cc->has_work = alpha_cpu_has_work; cc->do_interrupt = alpha_cpu_do_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; cc->gdb_write_register = alpha_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault; +#else cc->do_unassigned_access = alpha_cpu_unassigned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; dc->vmsd = &vmstate_alpha_cpu; diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index c85dc6e..07d9f63 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -446,9 +446,8 @@ int cpu_alpha_exec(CPUAlphaState *s); is returned if the signal was handled by the virtual CPU. */ int cpu_alpha_signal_handler(int host_signum, void *pinfo, void *puc); -int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw, - int mmu_idx); -#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault +int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); void do_restore_state(CPUAlphaState *, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); @@ -498,21 +497,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, *pflags = flags; } -static inline bool cpu_has_work(CPUState *cpu) -{ - /* Here we are checking to see if the CPU should wake up from HALT. - We will have gotten into this state only for WTINT from PALmode. */ - /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU - asleep even if (some) interrupts have been asserted. For now, - assume that if a CPU really wants to stay asleep, it will mask - interrupts at the chipset level, which will prevent these bits - from being set in the first place. */ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD - | CPU_INTERRUPT_TIMER - | CPU_INTERRUPT_SMP - | CPU_INTERRUPT_MCHK); -} - #include "exec/exec-all.h" #endif /* !defined (__CPU_ALPHA_H__) */ diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 025fdaf..cbd03c4 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -168,11 +168,13 @@ void helper_store_fpcr(CPUAlphaState *env, uint64_t val) } #if defined(CONFIG_USER_ONLY) -int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong address, +int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - env->exception_index = EXCP_MMFAULT; - env->trap_arg0 = address; + AlphaCPU *cpu = ALPHA_CPU(cs); + + cs->exception_index = EXCP_MMFAULT; + cpu->env.trap_arg0 = address; return 1; } #else @@ -213,7 +215,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, target_ulong *pphys, int *pprot) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); target_long saddr = addr; target_ulong phys = 0; target_ulong L1pte, L2pte, L3pte; @@ -326,22 +328,24 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return (fail >= 0 ? -1 : phys); } -int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, int rw, +int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw, int mmu_idx) { + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; target_ulong phys; int prot, fail; fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot); if (unlikely(fail >= 0)) { - env->exception_index = EXCP_MMFAULT; + cs->exception_index = EXCP_MMFAULT; env->trap_arg0 = addr; env->trap_arg1 = fail; env->trap_arg2 = (rw == 2 ? -1 : rw); return 1; } - tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } @@ -351,7 +355,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; - int i = env->exception_index; + int i = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; @@ -402,7 +406,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) ++count, name, env->error_code, env->pc, env->ir[IR_SP]); } - env->exception_index = -1; + cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) switch (i) { @@ -448,7 +452,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) } break; default: - cpu_abort(env, "Unhandled CPU exception"); + cpu_abort(cs, "Unhandled CPU exception"); } /* Remember where the exception happened. Emulate real hardware in @@ -504,21 +508,27 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, We expect that ENV->PC has already been updated. */ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) { - env->exception_index = excp; + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; env->error_code = error; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* This may be called from any of the helpers to set up EXCEPTION_INDEX. */ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, int excp, int error) { - env->exception_index = excp; + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; env->error_code = error; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr, diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index ea58704..5964bdc 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -26,45 +26,45 @@ uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); return (int32_t)ldl_phys(cs->as, p); } uint64_t helper_ldq_phys(CPUAlphaState *env, uint64_t p) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); return ldq_phys(cs->as, p); } uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); env->lock_addr = p; return env->lock_value = (int32_t)ldl_phys(cs->as, p); } uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); env->lock_addr = p; return env->lock_value = ldq_phys(cs->as, p); } void helper_stl_phys(CPUAlphaState *env, uint64_t p, uint64_t v) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); stl_phys(cs->as, p, v); } void helper_stq_phys(CPUAlphaState *env, uint64_t p, uint64_t v) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); stq_phys(cs->as, p, v); } uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); uint64_t ret = 0; if (p == env->lock_addr) { @@ -81,7 +81,7 @@ uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(alpha_env_get_cpu(env)); uint64_t ret = 0; if (p == env->lock_addr) { @@ -99,11 +99,13 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); uint64_t pc; uint32_t insn; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } pc = env->pc; @@ -112,9 +114,9 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, env->trap_arg0 = addr; env->trap_arg1 = insn >> 26; /* opcode */ env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ - env->exception_index = EXCP_UNALIGN; + cs->exception_index = EXCP_UNALIGN; env->error_code = 0; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, @@ -150,18 +152,18 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Exception index and error code are already set */ - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index 035810c..187ccf7 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -64,12 +64,12 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs) void helper_tbia(CPUAlphaState *env) { - tlb_flush(env, 1); + tlb_flush(CPU(alpha_env_get_cpu(env)), 1); } void helper_tbis(CPUAlphaState *env, uint64_t p) { - tlb_flush_page(env, p); + tlb_flush_page(CPU(alpha_env_get_cpu(env)), p); } void helper_tb_flush(CPUAlphaState *env) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 4c94bed..e7e319b 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1927,6 +1927,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) else { tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); + } } } break; @@ -1991,7 +1992,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) } else { if (islit) tcg_gen_movi_i64(cpu_ir[rc], -lit); - else + else { tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); } @@ -3463,8 +3464,8 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { gen_excp(&ctx, EXCP_DEBUG, 0); break; diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index ee469c4..ebb5235 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c @@ -127,7 +127,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #endif if (ret == (target_ulong)-1) { @@ -164,7 +164,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0); env->regs[0] = be32_to_cpu(size); #ifdef CONFIG_USER_ONLY - ((TaskState *)env->opaque)->swi_errno = err; + ((TaskState *)cs->opaque)->swi_errno = err; #else syscall_err = err; #endif @@ -183,6 +183,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) uint32_t do_arm_semihosting(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -190,7 +191,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) uint32_t ret; uint32_t len; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #else CPUARMState *ts = env; #endif @@ -554,7 +555,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) exit(0); default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); + cpu_dump_state(cs, stderr, fprintf, 0); abort(); } } diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1ce8a9b..c32d8c4 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -36,6 +36,12 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.regs[15] = value; } +static bool arm_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ @@ -76,7 +82,7 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); - memset(env, 0, offsetof(CPUARMState, breakpoints)); + memset(env, 0, offsetof(CPUARMState, features)); g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; @@ -143,7 +149,7 @@ static void arm_cpu_reset(CPUState *s) &env->vfp.fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status); - tlb_flush(env, 1); + tlb_flush(s, 1); /* Reset is a state change for some CPUARMState fields which we * bake assumptions about into translated code, so we need to * tb_flush(). @@ -1001,12 +1007,15 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->reset = arm_cpu_reset; cc->class_by_name = arm_cpu_class_by_name; + cc->has_work = arm_cpu_has_work; cc->do_interrupt = arm_cpu_do_interrupt; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->gdb_read_register = arm_cpu_gdb_read_register; cc->gdb_write_register = arm_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; cc->vmsd = &vmstate_arm_cpu; #endif diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 49fef3f..bf37cd6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -222,6 +222,10 @@ typedef struct CPUARMState { uint64_t dbgbcr[16]; /* breakpoint control registers */ uint64_t dbgwvr[16]; /* watchpoint value registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */ + /* If the counter is enabled, this stores the last time the counter + * was reset. Otherwise it stores the counter value + */ + uint32_t c15_ccnt; } cp15; struct { @@ -335,9 +339,8 @@ static inline bool is_a64(CPUARMState *env) is returned if the signal was handled by the virtual CPU. */ int cpu_arm_signal_handler(int host_signum, void *pinfo, void *puc); -int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, - int mmu_idx); -#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault +int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants @@ -1162,12 +1165,6 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *cs_base = 0; } -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & - (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); -} - #include "exec/exec-all.h" static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index c2ce33e..ec02582 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -60,6 +60,11 @@ uint32_t HELPER(cls32)(uint32_t x) return clrsb32(x); } +uint32_t HELPER(clz32)(uint32_t x) +{ + return clz32(x); +} + uint64_t HELPER(rbit64)(uint64_t x) { /* assign the correct byte position */ @@ -180,6 +185,36 @@ uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices, return result; } +/* Helper function for 64 bit polynomial multiply case: + * perform PolynomialMult(op1, op2) and return either the top or + * bottom half of the 128 bit result. + */ +uint64_t HELPER(neon_pmull_64_lo)(uint64_t op1, uint64_t op2) +{ + int bitnum; + uint64_t res = 0; + + for (bitnum = 0; bitnum < 64; bitnum++) { + if (op1 & (1ULL << bitnum)) { + res ^= op2 << bitnum; + } + } + return res; +} +uint64_t HELPER(neon_pmull_64_hi)(uint64_t op1, uint64_t op2) +{ + int bitnum; + uint64_t res = 0; + + /* bit 0 of op1 can't influence the high 64 bits at all */ + for (bitnum = 1; bitnum < 64; bitnum++) { + if (op1 & (1ULL << bitnum)) { + res ^= op2 >> (64 - bitnum); + } + } + return res; +} + /* 64bit/double versions of the neon float compare functions */ uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) { @@ -258,3 +293,146 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp) } return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst); } + +/* Pairwise long add: add pairs of adjacent elements into + * double-width elements in the result (eg _s8 is an 8x8->16 op) + */ +uint64_t HELPER(neon_addlp_s8)(uint64_t a) +{ + uint64_t nsignmask = 0x0080008000800080ULL; + uint64_t wsignmask = 0x8000800080008000ULL; + uint64_t elementmask = 0x00ff00ff00ff00ffULL; + uint64_t tmp1, tmp2; + uint64_t res, signres; + + /* Extract odd elements, sign extend each to a 16 bit field */ + tmp1 = a & elementmask; + tmp1 ^= nsignmask; + tmp1 |= wsignmask; + tmp1 = (tmp1 - nsignmask) ^ wsignmask; + /* Ditto for the even elements */ + tmp2 = (a >> 8) & elementmask; + tmp2 ^= nsignmask; + tmp2 |= wsignmask; + tmp2 = (tmp2 - nsignmask) ^ wsignmask; + + /* calculate the result by summing bits 0..14, 16..22, etc, + * and then adjusting the sign bits 15, 23, etc manually. + * This ensures the addition can't overflow the 16 bit field. + */ + signres = (tmp1 ^ tmp2) & wsignmask; + res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask); + res ^= signres; + + return res; +} + +uint64_t HELPER(neon_addlp_u8)(uint64_t a) +{ + uint64_t tmp; + + tmp = a & 0x00ff00ff00ff00ffULL; + tmp += (a >> 8) & 0x00ff00ff00ff00ffULL; + return tmp; +} + +uint64_t HELPER(neon_addlp_s16)(uint64_t a) +{ + int32_t reslo, reshi; + + reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16); + reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48); + + return (uint32_t)reslo | (((uint64_t)reshi) << 32); +} + +uint64_t HELPER(neon_addlp_u16)(uint64_t a) +{ + uint64_t tmp; + + tmp = a & 0x0000ffff0000ffffULL; + tmp += (a >> 16) & 0x0000ffff0000ffffULL; + return tmp; +} + +/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ +float32 HELPER(frecpx_f32)(float32 a, void *fpstp) +{ + float_status *fpst = fpstp; + uint32_t val32, sbit; + int32_t exp; + + if (float32_is_any_nan(a)) { + float32 nan = a; + if (float32_is_signaling_nan(a)) { + float_raise(float_flag_invalid, fpst); + nan = float32_maybe_silence_nan(a); + } + if (fpst->default_nan_mode) { + nan = float32_default_nan; + } + return nan; + } + + val32 = float32_val(a); + sbit = 0x80000000ULL & val32; + exp = extract32(val32, 23, 8); + + if (exp == 0) { + return make_float32(sbit | (0xfe << 23)); + } else { + return make_float32(sbit | (~exp & 0xff) << 23); + } +} + +float64 HELPER(frecpx_f64)(float64 a, void *fpstp) +{ + float_status *fpst = fpstp; + uint64_t val64, sbit; + int64_t exp; + + if (float64_is_any_nan(a)) { + float64 nan = a; + if (float64_is_signaling_nan(a)) { + float_raise(float_flag_invalid, fpst); + nan = float64_maybe_silence_nan(a); + } + if (fpst->default_nan_mode) { + nan = float64_default_nan; + } + return nan; + } + + val64 = float64_val(a); + sbit = 0x8000000000000000ULL & val64; + exp = extract64(float64_val(a), 52, 11); + + if (exp == 0) { + return make_float64(sbit | (0x7feULL << 52)); + } else { + return make_float64(sbit | (~exp & 0x7ffULL) << 52); + } +} + +float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) +{ + /* Von Neumann rounding is implemented by using round-to-zero + * and then setting the LSB of the result if Inexact was raised. + */ + float32 r; + float_status *fpst = &env->vfp.fp_status; + float_status tstat = *fpst; + int exflags; + + set_float_rounding_mode(float_round_to_zero, &tstat); + set_float_exception_flags(0, &tstat); + r = float64_to_float32(a, &tstat); + r = float32_maybe_silence_nan(r); + exflags = get_float_exception_flags(&tstat); + if (exflags & float_flag_inexact) { + r = make_float32(float32_val(r) | 1); + } + exflags |= get_float_exception_flags(fpst); + set_float_exception_flags(exflags, fpst); + return r; +} diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index ab9933c..3f05bed 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -21,12 +21,15 @@ DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(cls64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(cls32, TCG_CALL_NO_RWG_SE, i32, i32) +DEF_HELPER_FLAGS_1(clz32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr) DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32) +DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) @@ -36,3 +39,10 @@ DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) +DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(neon_addlp_u8, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) diff --git a/target-arm/helper.c b/target-arm/helper.c index 90f85f1..55077ed 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -13,6 +13,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address, int access_type, int is_user, hwaddr *phys_ptr, int *prot, target_ulong *page_size); + +/* Definitions for the PMCCNTR and PMCR registers */ +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 #endif static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) @@ -298,17 +303,21 @@ void init_cpreg_list(ARMCPU *cpu) static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + env->cp15.c3 = value; - tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ + tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ } static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (env->cp15.c13_fcse != value) { /* Unlike real hardware the qemu TLB uses virtual addresses, * not modified virtual addresses, so this causes a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); env->cp15.c13_fcse = value; } } @@ -316,12 +325,14 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) { /* For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } env->cp15.c13_context = value; } @@ -330,28 +341,36 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - tlb_flush(env, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - tlb_flush_page(env, value & TARGET_PAGE_MASK); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - tlb_flush(env, value == 0); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), value == 0); } static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - tlb_flush_page(env, value & TARGET_PAGE_MASK); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } static const ARMCPRegInfo cp_reginfo[] = { @@ -469,7 +488,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) { - /* Perfomance monitor registers user accessibility is controlled + /* Performance monitor registers user accessibility is controlled * by PMUSERENR. */ if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { @@ -478,13 +497,84 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) return CP_ACCESS_OK; } +#ifndef CONFIG_USER_ONLY static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + /* Don't computer the number of ticks in user mode */ + uint32_t temp_ticks; + + temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRE) { + /* If the counter is enabled */ + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; + } else { + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } + } + + if (value & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt = 0; + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &= ~0x39; env->cp15.c9_pmcr |= (value & 0x39); + + if (env->cp15.c9_pmcr & PMCRE) { + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + temp_ticks /= 64; + } + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } +} + +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t total_ticks; + + if (!(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, do not change value */ + return env->cp15.c15_ccnt; + } + + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /= 64; + } + return total_ticks - env->cp15.c15_ccnt; +} + +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t total_ticks; + + if (!(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, set the absolute value */ + env->cp15.c15_ccnt = value; + return; + } + + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /= 64; + } + env->cp15.c15_ccnt = total_ticks - value; } +#endif static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -604,10 +694,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, .accessfn = pmreg_access }, - /* Unimplemented, RAZ/WI. */ +#ifndef CONFIG_USER_ONLY { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, + .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, + .readfn = pmccntr_read, .writefn = pmccntr_write, .accessfn = pmreg_access }, +#endif { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), @@ -1270,11 +1362,13 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } vmsa_ttbcr_raw_write(env, ri, value); } @@ -1289,8 +1383,10 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); env->cp15.c2_control = value; } @@ -1301,7 +1397,9 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, * must flush the TLB. */ if (cpreg_field_is_64bit(ri)) { - tlb_flush(env, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } raw_write(env, ri, value); } @@ -1608,24 +1706,27 @@ static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); uint64_t pageaddr = value << 12; - tlb_flush_page(env, pageaddr); + tlb_flush_page(CPU(cpu), pageaddr); } static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA, all ASIDs (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); uint64_t pageaddr = value << 12; - tlb_flush_page(env, pageaddr); + tlb_flush_page(CPU(cpu), pageaddr); } static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); int asid = extract64(value, 48, 16); - tlb_flush(env, asid == 0); + tlb_flush(CPU(cpu), asid == 0); } static const ARMCPRegInfo v8_cp_reginfo[] = { @@ -1751,10 +1852,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + env->cp15.c1_sys = value; /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) @@ -1873,21 +1976,25 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement no event counters. + * field as main ID register, and we implement only the cycle + * count register. */ +#ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr = { .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000, + .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), .accessfn = pmreg_access, .writefn = pmcr_write, .raw_writefn = raw_write, }; + define_one_arm_cp_reg(cpu, &pmcr); +#endif ARMCPRegInfo clidr = { .name = "CLIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr }; - define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); } else { @@ -2105,19 +2212,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPU *cpu_arm_init(const char *cpu_model) { - ARMCPU *cpu; - ObjectClass *oc; - - oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); - if (!oc) { - return NULL; - } - cpu = ARM_CPU(object_new(object_class_get_name(oc))); - - /* TODO this should be set centrally, once possible */ - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); } void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) @@ -2478,7 +2573,7 @@ uint32_t cpsr_read(CPUARMState *env) (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | ((env->condexec_bits & 0xfc) << 8) - | (env->GE << 16) | env->daif; + | (env->GE << 16) | (env->daif & CPSR_AIF); } void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) @@ -2580,20 +2675,20 @@ uint32_t HELPER(rbit)(uint32_t x) void arm_cpu_do_interrupt(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } -int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, - int mmu_idx) +int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (rw == 2) { - env->exception_index = EXCP_PREFETCH_ABORT; + cs->exception_index = EXCP_PREFETCH_ABORT; env->cp15.c6_insn = address; } else { - env->exception_index = EXCP_DATA_ABORT; + cs->exception_index = EXCP_DATA_ABORT; env->cp15.c6_data = address; } return 1; @@ -2602,29 +2697,40 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { - cpu_abort(env, "v7m_mrs %d\n", reg); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); } uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - cpu_abort(env, "v7m_mrs %d\n", reg); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); return 0; } void switch_mode(CPUARMState *env, int mode) { - if (mode != ARM_CPU_MODE_USR) - cpu_abort(env, "Tried to switch out of user mode\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + if (mode != ARM_CPU_MODE_USR) { + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); + } } void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) { - cpu_abort(env, "banked r13 write\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "banked r13 write\n"); } uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) { - cpu_abort(env, "banked r13 read\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "banked r13 read\n"); return 0; } @@ -2681,15 +2787,17 @@ void switch_mode(CPUARMState *env, int mode) static void v7m_push(CPUARMState *env, uint32_t val) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(arm_env_get_cpu(env)); + env->regs[13] -= 4; stl_phys(cs->as, env->regs[13], val); } static uint32_t v7m_pop(CPUARMState *env) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(arm_env_get_cpu(env)); uint32_t val; + val = ldl_phys(cs->as, env->regs[13]); env->regs[13] += 4; return val; @@ -2777,7 +2885,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) uint32_t lr; uint32_t addr; - arm_log_exception(env->exception_index); + arm_log_exception(cs->exception_index); lr = 0xfffffff1; if (env->v7m.current_sp) @@ -2789,7 +2897,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) handle it. */ /* TODO: Need to escalate if the current priority is higher than the one we're raising. */ - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); return; @@ -2821,7 +2929,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) do_v7m_exception_exit(env); return; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } @@ -2862,10 +2970,10 @@ void arm_cpu_do_interrupt(CPUState *cs) assert(!IS_M(env)); - arm_log_exception(env->exception_index); + arm_log_exception(cs->exception_index); /* TODO: Vectored interrupt controller. */ - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_UDEF: new_mode = ARM_CPU_MODE_UND; addr = 0x04; @@ -2946,7 +3054,7 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } /* High vectors. */ @@ -3053,7 +3161,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, int is_user, hwaddr *phys_ptr, int *prot, target_ulong *page_size) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(arm_env_get_cpu(env)); int code; uint32_t table; uint32_t desc; @@ -3149,7 +3257,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, int is_user, hwaddr *phys_ptr, int *prot, target_ulong *page_size) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(arm_env_get_cpu(env)); int code; uint32_t table; uint32_t desc; @@ -3272,7 +3380,7 @@ static int get_phys_addr_lpae(CPUARMState *env, uint32_t address, hwaddr *phys_ptr, int *prot, target_ulong *page_size_ptr) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(arm_env_get_cpu(env)); /* Read an LPAE long-descriptor translation table. */ MMUFaultType fault_type = translation_fault; uint32_t level = 1; @@ -3552,9 +3660,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address, } } -int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, - int access_type, int mmu_idx) +int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, + int access_type, int mmu_idx) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; hwaddr phys_addr; target_ulong page_size; int prot; @@ -3567,20 +3677,20 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, /* Map a single [sub]page. */ phys_addr &= ~(hwaddr)0x3ff; address &= ~(uint32_t)0x3ff; - tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); return 0; } if (access_type == 2) { env->cp15.c5_insn = ret; env->cp15.c6_insn = address; - env->exception_index = EXCP_PREFETCH_ABORT; + cs->exception_index = EXCP_PREFETCH_ABORT; } else { env->cp15.c5_data = ret; if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) env->cp15.c5_data |= (1 << 11); env->cp15.c6_data = address; - env->exception_index = EXCP_DATA_ABORT; + cs->exception_index = EXCP_DATA_ABORT; } return 1; } @@ -3622,6 +3732,8 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { + ARMCPU *cpu = arm_env_get_cpu(env); + switch (reg) { case 0: /* APSR */ return xpsr_read(env) & 0xf8000000; @@ -3652,13 +3764,15 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return env->v7m.control; default: /* ??? For debugging only. */ - cpu_abort(env, "Unimplemented system register read (%d)\n", reg); + cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); return 0; } } void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { + ARMCPU *cpu = arm_env_get_cpu(env); + switch (reg) { case 0: /* APSR */ xpsr_write(env, val, 0xf8000000); @@ -3721,7 +3835,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) break; default: /* ??? For debugging only. */ - cpu_abort(env, "Unimplemented system register write (%d)\n", reg); + cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); return; } } @@ -4406,16 +4520,21 @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) * int->float conversions at run-time. */ #define float64_256 make_float64(0x4070000000000000LL) #define float64_512 make_float64(0x4080000000000000LL) +#define float32_maxnorm make_float32(0x7f7fffff) +#define float64_maxnorm make_float64(0x7fefffffffffffffLL) -/* The algorithm that must be used to calculate the estimate - * is specified by the ARM ARM. +/* Reciprocal functions + * + * The algorithm that must be used to calculate the estimate + * is specified by the ARM ARM, see FPRecipEstimate() */ -static float64 recip_estimate(float64 a, CPUARMState *env) + +static float64 recip_estimate(float64 a, float_status *real_fp_status) { /* These calculations mustn't set any fp exception flags, * so we use a local copy of the fp_status. */ - float_status dummy_status = env->vfp.standard_fp_status; + float_status dummy_status = *real_fp_status; float_status *s = &dummy_status; /* q = (int)(a * 512.0) */ float64 q = float64_mul(float64_512, a, s); @@ -4436,56 +4555,178 @@ static float64 recip_estimate(float64 a, CPUARMState *env) return float64_div(int64_to_float64(q_int, s), float64_256, s); } -float32 HELPER(recpe_f32)(float32 a, CPUARMState *env) +/* Common wrapper to call recip_estimate */ +static float64 call_recip_estimate(float64 num, int off, float_status *fpst) { - float_status *s = &env->vfp.standard_fp_status; - float64 f64; - uint32_t val32 = float32_val(a); + uint64_t val64 = float64_val(num); + uint64_t frac = extract64(val64, 0, 52); + int64_t exp = extract64(val64, 52, 11); + uint64_t sbit; + float64 scaled, estimate; - int result_exp; - int a_exp = (val32 & 0x7f800000) >> 23; - int sign = val32 & 0x80000000; + /* Generate the scaled number for the estimate function */ + if (exp == 0) { + if (extract64(frac, 51, 1) == 0) { + exp = -1; + frac = extract64(frac, 0, 50) << 2; + } else { + frac = extract64(frac, 0, 51) << 1; + } + } - if (float32_is_any_nan(a)) { - if (float32_is_signaling_nan(a)) { - float_raise(float_flag_invalid, s); + /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ + scaled = make_float64((0x3feULL << 52) + | extract64(frac, 44, 8) << 44); + + estimate = recip_estimate(scaled, fpst); + + /* Build new result */ + val64 = float64_val(estimate); + sbit = 0x8000000000000000ULL & val64; + exp = off - exp; + frac = extract64(val64, 0, 52); + + if (exp == 0) { + frac = 1ULL << 51 | extract64(frac, 1, 51); + } else if (exp == -1) { + frac = 1ULL << 50 | extract64(frac, 2, 50); + exp = 0; + } + + return make_float64(sbit | (exp << 52) | frac); +} + +static bool round_to_inf(float_status *fpst, bool sign_bit) +{ + switch (fpst->float_rounding_mode) { + case float_round_nearest_even: /* Round to Nearest */ + return true; + case float_round_up: /* Round to +Inf */ + return !sign_bit; + case float_round_down: /* Round to -Inf */ + return sign_bit; + case float_round_to_zero: /* Round to Zero */ + return false; + } + + g_assert_not_reached(); +} + +float32 HELPER(recpe_f32)(float32 input, void *fpstp) +{ + float_status *fpst = fpstp; + float32 f32 = float32_squash_input_denormal(input, fpst); + uint32_t f32_val = float32_val(f32); + uint32_t f32_sbit = 0x80000000ULL & f32_val; + int32_t f32_exp = extract32(f32_val, 23, 8); + uint32_t f32_frac = extract32(f32_val, 0, 23); + float64 f64, r64; + uint64_t r64_val; + int64_t r64_exp; + uint64_t r64_frac; + + if (float32_is_any_nan(f32)) { + float32 nan = f32; + if (float32_is_signaling_nan(f32)) { + float_raise(float_flag_invalid, fpst); + nan = float32_maybe_silence_nan(f32); } - return float32_default_nan; - } else if (float32_is_infinity(a)) { - return float32_set_sign(float32_zero, float32_is_neg(a)); - } else if (float32_is_zero_or_denormal(a)) { - if (!float32_is_zero(a)) { - float_raise(float_flag_input_denormal, s); + if (fpst->default_nan_mode) { + nan = float32_default_nan; } - float_raise(float_flag_divbyzero, s); - return float32_set_sign(float32_infinity, float32_is_neg(a)); - } else if (a_exp >= 253) { - float_raise(float_flag_underflow, s); - return float32_set_sign(float32_zero, float32_is_neg(a)); + return nan; + } else if (float32_is_infinity(f32)) { + return float32_set_sign(float32_zero, float32_is_neg(f32)); + } else if (float32_is_zero(f32)) { + float_raise(float_flag_divbyzero, fpst); + return float32_set_sign(float32_infinity, float32_is_neg(f32)); + } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { + /* Abs(value) < 2.0^-128 */ + float_raise(float_flag_overflow | float_flag_inexact, fpst); + if (round_to_inf(fpst, f32_sbit)) { + return float32_set_sign(float32_infinity, float32_is_neg(f32)); + } else { + return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); + } + } else if (f32_exp >= 253 && fpst->flush_to_zero) { + float_raise(float_flag_underflow, fpst); + return float32_set_sign(float32_zero, float32_is_neg(f32)); } - f64 = make_float64((0x3feULL << 52) - | ((int64_t)(val32 & 0x7fffff) << 29)); - result_exp = 253 - a_exp; + f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); + r64 = call_recip_estimate(f64, 253, fpst); + r64_val = float64_val(r64); + r64_exp = extract64(r64_val, 52, 11); + r64_frac = extract64(r64_val, 0, 52); - f64 = recip_estimate(f64, env); + /* result = sign : result_exp<7:0> : fraction<51:29>; */ + return make_float32(f32_sbit | + (r64_exp & 0xff) << 23 | + extract64(r64_frac, 29, 24)); +} - val32 = sign - | ((result_exp & 0xff) << 23) - | ((float64_val(f64) >> 29) & 0x7fffff); - return make_float32(val32); +float64 HELPER(recpe_f64)(float64 input, void *fpstp) +{ + float_status *fpst = fpstp; + float64 f64 = float64_squash_input_denormal(input, fpst); + uint64_t f64_val = float64_val(f64); + uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; + int64_t f64_exp = extract64(f64_val, 52, 11); + float64 r64; + uint64_t r64_val; + int64_t r64_exp; + uint64_t r64_frac; + + /* Deal with any special cases */ + if (float64_is_any_nan(f64)) { + float64 nan = f64; + if (float64_is_signaling_nan(f64)) { + float_raise(float_flag_invalid, fpst); + nan = float64_maybe_silence_nan(f64); + } + if (fpst->default_nan_mode) { + nan = float64_default_nan; + } + return nan; + } else if (float64_is_infinity(f64)) { + return float64_set_sign(float64_zero, float64_is_neg(f64)); + } else if (float64_is_zero(f64)) { + float_raise(float_flag_divbyzero, fpst); + return float64_set_sign(float64_infinity, float64_is_neg(f64)); + } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { + /* Abs(value) < 2.0^-1024 */ + float_raise(float_flag_overflow | float_flag_inexact, fpst); + if (round_to_inf(fpst, f64_sbit)) { + return float64_set_sign(float64_infinity, float64_is_neg(f64)); + } else { + return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); + } + } else if (f64_exp >= 1023 && fpst->flush_to_zero) { + float_raise(float_flag_underflow, fpst); + return float64_set_sign(float64_zero, float64_is_neg(f64)); + } + + r64 = call_recip_estimate(f64, 2045, fpst); + r64_val = float64_val(r64); + r64_exp = extract64(r64_val, 52, 11); + r64_frac = extract64(r64_val, 0, 52); + + /* result = sign : result_exp<10:0> : fraction<51:0> */ + return make_float64(f64_sbit | + ((r64_exp & 0x7ff) << 52) | + r64_frac); } /* The algorithm that must be used to calculate the estimate * is specified by the ARM ARM. */ -static float64 recip_sqrt_estimate(float64 a, CPUARMState *env) +static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) { /* These calculations mustn't set any fp exception flags, * so we use a local copy of the fp_status. */ - float_status dummy_status = env->vfp.standard_fp_status; + float_status dummy_status = *real_fp_status; float_status *s = &dummy_status; float64 q; int64_t q_int; @@ -4532,49 +4773,64 @@ static float64 recip_sqrt_estimate(float64 a, CPUARMState *env) return float64_div(int64_to_float64(q_int, s), float64_256, s); } -float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env) +float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) { - float_status *s = &env->vfp.standard_fp_status; + float_status *s = fpstp; + float32 f32 = float32_squash_input_denormal(input, s); + uint32_t val = float32_val(f32); + uint32_t f32_sbit = 0x80000000 & val; + int32_t f32_exp = extract32(val, 23, 8); + uint32_t f32_frac = extract32(val, 0, 23); + uint64_t f64_frac; + uint64_t val64; int result_exp; float64 f64; - uint32_t val; - uint64_t val64; - val = float32_val(a); - - if (float32_is_any_nan(a)) { - if (float32_is_signaling_nan(a)) { + if (float32_is_any_nan(f32)) { + float32 nan = f32; + if (float32_is_signaling_nan(f32)) { float_raise(float_flag_invalid, s); + nan = float32_maybe_silence_nan(f32); } - return float32_default_nan; - } else if (float32_is_zero_or_denormal(a)) { - if (!float32_is_zero(a)) { - float_raise(float_flag_input_denormal, s); + if (s->default_nan_mode) { + nan = float32_default_nan; } + return nan; + } else if (float32_is_zero(f32)) { float_raise(float_flag_divbyzero, s); - return float32_set_sign(float32_infinity, float32_is_neg(a)); - } else if (float32_is_neg(a)) { + return float32_set_sign(float32_infinity, float32_is_neg(f32)); + } else if (float32_is_neg(f32)) { float_raise(float_flag_invalid, s); return float32_default_nan; - } else if (float32_is_infinity(a)) { + } else if (float32_is_infinity(f32)) { return float32_zero; } - /* Normalize to a double-precision value between 0.25 and 1.0, + /* Scale and normalize to a double-precision value between 0.25 and 1.0, * preserving the parity of the exponent. */ - if ((val & 0x800000) == 0) { - f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) + + f64_frac = ((uint64_t) f32_frac) << 29; + if (f32_exp == 0) { + while (extract64(f64_frac, 51, 1) == 0) { + f64_frac = f64_frac << 1; + f32_exp = f32_exp-1; + } + f64_frac = extract64(f64_frac, 0, 51) << 1; + } + + if (extract64(f32_exp, 0, 1) == 0) { + f64 = make_float64(((uint64_t) f32_sbit) << 32 | (0x3feULL << 52) - | ((uint64_t)(val & 0x7fffff) << 29)); + | f64_frac); } else { - f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) + f64 = make_float64(((uint64_t) f32_sbit) << 32 | (0x3fdULL << 52) - | ((uint64_t)(val & 0x7fffff) << 29)); + | f64_frac); } - result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2; + result_exp = (380 - f32_exp) / 2; - f64 = recip_sqrt_estimate(f64, env); + f64 = recip_sqrt_estimate(f64, s); val64 = float64_val(f64); @@ -4583,8 +4839,72 @@ float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env) return make_float32(val); } -uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env) +float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) { + float_status *s = fpstp; + float64 f64 = float64_squash_input_denormal(input, s); + uint64_t val = float64_val(f64); + uint64_t f64_sbit = 0x8000000000000000ULL & val; + int64_t f64_exp = extract64(val, 52, 11); + uint64_t f64_frac = extract64(val, 0, 52); + int64_t result_exp; + uint64_t result_frac; + + if (float64_is_any_nan(f64)) { + float64 nan = f64; + if (float64_is_signaling_nan(f64)) { + float_raise(float_flag_invalid, s); + nan = float64_maybe_silence_nan(f64); + } + if (s->default_nan_mode) { + nan = float64_default_nan; + } + return nan; + } else if (float64_is_zero(f64)) { + float_raise(float_flag_divbyzero, s); + return float64_set_sign(float64_infinity, float64_is_neg(f64)); + } else if (float64_is_neg(f64)) { + float_raise(float_flag_invalid, s); + return float64_default_nan; + } else if (float64_is_infinity(f64)) { + return float64_zero; + } + + /* Scale and normalize to a double-precision value between 0.25 and 1.0, + * preserving the parity of the exponent. */ + + if (f64_exp == 0) { + while (extract64(f64_frac, 51, 1) == 0) { + f64_frac = f64_frac << 1; + f64_exp = f64_exp - 1; + } + f64_frac = extract64(f64_frac, 0, 51) << 1; + } + + if (extract64(f64_exp, 0, 1) == 0) { + f64 = make_float64(f64_sbit + | (0x3feULL << 52) + | f64_frac); + } else { + f64 = make_float64(f64_sbit + | (0x3fdULL << 52) + | f64_frac); + } + + result_exp = (3068 - f64_exp) / 2; + + f64 = recip_sqrt_estimate(f64, s); + + result_frac = extract64(float64_val(f64), 0, 52); + + return make_float64(f64_sbit | + ((result_exp & 0x7ff) << 52) | + result_frac); +} + +uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) +{ + float_status *s = fpstp; float64 f64; if ((a & 0x80000000) == 0) { @@ -4594,13 +4914,14 @@ uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env) f64 = make_float64((0x3feULL << 52) | ((int64_t)(a & 0x7fffffff) << 21)); - f64 = recip_estimate (f64, env); + f64 = recip_estimate(f64, s); return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); } -uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env) +uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) { + float_status *fpst = fpstp; float64 f64; if ((a & 0xc0000000) == 0) { @@ -4615,7 +4936,7 @@ uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env) | ((uint64_t)(a & 0x3fffffff) << 22)); } - f64 = recip_sqrt_estimate(f64, env); + f64 = recip_sqrt_estimate(f64, fpst); return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); } diff --git a/target-arm/helper.h b/target-arm/helper.h index 276f3a9..366c1b3 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -50,6 +50,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception, void, env, i32) DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(wfe, void, env) DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_1(cpsr_read, i32, env) @@ -166,10 +167,12 @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) DEF_HELPER_3(recps_f32, f32, f32, f32, env) DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) -DEF_HELPER_2(recpe_f32, f32, f32, env) -DEF_HELPER_2(rsqrte_f32, f32, f32, env) -DEF_HELPER_2(recpe_u32, i32, i32, env) -DEF_HELPER_2(rsqrte_u32, i32, i32, env) +DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_2(recpe_u32, i32, i32, ptr) +DEF_HELPER_FLAGS_2(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32) DEF_HELPER_3(shl_cc, i32, env, i32, i32) @@ -183,12 +186,20 @@ DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) /* neon_helper.c */ -DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qadd_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qadd_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qadd_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qadd_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qadd_s32, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s64, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(neon_sqadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u64, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32) DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32) DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32) @@ -372,12 +383,14 @@ DEF_HELPER_2(neon_mull_s16, i64, i32, i32) DEF_HELPER_1(neon_negl_u16, i64, i64) DEF_HELPER_1(neon_negl_u32, i64, i64) -DEF_HELPER_2(neon_qabs_s8, i32, env, i32) -DEF_HELPER_2(neon_qabs_s16, i32, env, i32) -DEF_HELPER_2(neon_qabs_s32, i32, env, i32) -DEF_HELPER_2(neon_qneg_s8, i32, env, i32) -DEF_HELPER_2(neon_qneg_s16, i32, env, i32) -DEF_HELPER_2(neon_qneg_s32, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_3(neon_abd_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr) diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c index 13752ba..8d6f9a9 100644 --- a/target-arm/neon_helper.c +++ b/target-arm/neon_helper.c @@ -236,6 +236,171 @@ uint64_t HELPER(neon_qadd_s64)(CPUARMState *env, uint64_t src1, uint64_t src2) return res; } +/* Unsigned saturating accumulate of signed value + * + * Op1/Rn is treated as signed + * Op2/Rd is treated as unsigned + * + * Explicit casting is used to ensure the correct sign extension of + * inputs. The result is treated as a unsigned value and saturated as such. + * + * We use a macro for the 8/16 bit cases which expects signed integers of va, + * vb, and vr for interim calculation and an unsigned 32 bit result value r. + */ + +#define USATACC(bits, shift) \ + do { \ + va = sextract32(a, shift, bits); \ + vb = extract32(b, shift, bits); \ + vr = va + vb; \ + if (vr > UINT##bits##_MAX) { \ + SET_QC(); \ + vr = UINT##bits##_MAX; \ + } else if (vr < 0) { \ + SET_QC(); \ + vr = 0; \ + } \ + r = deposit32(r, shift, bits, vr); \ + } while (0) + +uint32_t HELPER(neon_uqadd_s8)(CPUARMState *env, uint32_t a, uint32_t b) +{ + int16_t va, vb, vr; + uint32_t r = 0; + + USATACC(8, 0); + USATACC(8, 8); + USATACC(8, 16); + USATACC(8, 24); + return r; +} + +uint32_t HELPER(neon_uqadd_s16)(CPUARMState *env, uint32_t a, uint32_t b) +{ + int32_t va, vb, vr; + uint64_t r = 0; + + USATACC(16, 0); + USATACC(16, 16); + return r; +} + +#undef USATACC + +uint32_t HELPER(neon_uqadd_s32)(CPUARMState *env, uint32_t a, uint32_t b) +{ + int64_t va = (int32_t)a; + int64_t vb = (uint32_t)b; + int64_t vr = va + vb; + if (vr > UINT32_MAX) { + SET_QC(); + vr = UINT32_MAX; + } else if (vr < 0) { + SET_QC(); + vr = 0; + } + return vr; +} + +uint64_t HELPER(neon_uqadd_s64)(CPUARMState *env, uint64_t a, uint64_t b) +{ + uint64_t res; + res = a + b; + /* We only need to look at the pattern of SIGN bits to detect + * +ve/-ve saturation + */ + if (~a & b & ~res & SIGNBIT64) { + SET_QC(); + res = UINT64_MAX; + } else if (a & ~b & res & SIGNBIT64) { + SET_QC(); + res = 0; + } + return res; +} + +/* Signed saturating accumulate of unsigned value + * + * Op1/Rn is treated as unsigned + * Op2/Rd is treated as signed + * + * The result is treated as a signed value and saturated as such + * + * We use a macro for the 8/16 bit cases which expects signed integers of va, + * vb, and vr for interim calculation and an unsigned 32 bit result value r. + */ + +#define SSATACC(bits, shift) \ + do { \ + va = extract32(a, shift, bits); \ + vb = sextract32(b, shift, bits); \ + vr = va + vb; \ + if (vr > INT##bits##_MAX) { \ + SET_QC(); \ + vr = INT##bits##_MAX; \ + } else if (vr < INT##bits##_MIN) { \ + SET_QC(); \ + vr = INT##bits##_MIN; \ + } \ + r = deposit32(r, shift, bits, vr); \ + } while (0) + +uint32_t HELPER(neon_sqadd_u8)(CPUARMState *env, uint32_t a, uint32_t b) +{ + int16_t va, vb, vr; + uint32_t r = 0; + + SSATACC(8, 0); + SSATACC(8, 8); + SSATACC(8, 16); + SSATACC(8, 24); + return r; +} + +uint32_t HELPER(neon_sqadd_u16)(CPUARMState *env, uint32_t a, uint32_t b) +{ + int32_t va, vb, vr; + uint32_t r = 0; + + SSATACC(16, 0); + SSATACC(16, 16); + + return r; +} + +#undef SSATACC + +uint32_t HELPER(neon_sqadd_u32)(CPUARMState *env, uint32_t a, uint32_t b) +{ + int64_t res; + int64_t op1 = (uint32_t)a; + int64_t op2 = (int32_t)b; + res = op1 + op2; + if (res > INT32_MAX) { + SET_QC(); + res = INT32_MAX; + } else if (res < INT32_MIN) { + SET_QC(); + res = INT32_MIN; + } + return res; +} + +uint64_t HELPER(neon_sqadd_u64)(CPUARMState *env, uint64_t a, uint64_t b) +{ + uint64_t res; + res = a + b; + /* We only need to look at the pattern of SIGN bits to detect an overflow */ + if (((a & res) + | (~b & res) + | (a & ~b)) & SIGNBIT64) { + SET_QC(); + res = INT64_MAX; + } + return res; +} + + #define NEON_USAT(dest, src1, src2, type) do { \ uint32_t tmp = (uint32_t)src1 - (uint32_t)src2; \ if (tmp != (type)tmp) { \ @@ -1776,6 +1941,28 @@ uint32_t HELPER(neon_qneg_s32)(CPUARMState *env, uint32_t x) return x; } +uint64_t HELPER(neon_qabs_s64)(CPUARMState *env, uint64_t x) +{ + if (x == SIGNBIT64) { + SET_QC(); + x = ~SIGNBIT64; + } else if ((int64_t)x < 0) { + x = -x; + } + return x; +} + +uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x) +{ + if (x == SIGNBIT64) { + SET_QC(); + x = ~SIGNBIT64; + } else { + x = -x; + } + return x; +} + /* NEON Float helpers. */ uint32_t HELPER(neon_abd_f32)(uint32_t a, uint32_t b, void *fpstp) { diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 7d06d2f..21ff58e 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -24,8 +24,11 @@ static void raise_exception(CPUARMState *env, int tt) { - env->exception_index = tt; - cpu_loop_exit(env); + ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = tt; + cpu_loop_exit(cs); } uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, @@ -69,20 +72,24 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, #include "exec/softmmu_template.h" /* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - raise_exception(env, env->exception_index); + raise_exception(env, cs->exception_index); } } #endif @@ -220,15 +227,28 @@ void HELPER(wfi)(CPUARMState *env) { CPUState *cs = CPU(arm_env_get_cpu(env)); - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cs->halted = 1; - cpu_loop_exit(env); + cpu_loop_exit(cs); +} + +void HELPER(wfe)(CPUARMState *env) +{ + CPUState *cs = CPU(arm_env_get_cpu(env)); + + /* Don't actually halt the CPU, just yield back to top + * level loop + */ + cs->exception_index = EXCP_YIELD; + cpu_loop_exit(cs); } void HELPER(exception)(CPUARMState *env, uint32_t excp) { - env->exception_index = excp; - cpu_loop_exit(env); + CPUState *cs = CPU(arm_env_get_cpu(env)); + + cs->exception_index = excp; + cpu_loop_exit(cs); } uint32_t HELPER(cpsr_read)(CPUARMState *env) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 08ac659..9f06450 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -73,14 +73,17 @@ typedef struct AArch64DecodeTable { } AArch64DecodeTable; /* Function prototype for gen_ functions for calling Neon helpers */ +typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); +typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); +typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); /* initialize TCG globals. */ void a64_translate_init(void) @@ -210,7 +213,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); - tcg_gen_exit_tb((tcg_target_long)tb + n); + tcg_gen_exit_tb((intptr_t)tb + n); s->is_jmp = DISAS_TB_JUMP; } else { gen_a64_set_pc_im(dest); @@ -3096,12 +3099,11 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) /* non-flag setting ops may use SP */ if (!setflags) { - tcg_rn = read_cpu_reg_sp(s, rn, sf); tcg_rd = cpu_reg_sp(s, rd); } else { - tcg_rn = read_cpu_reg(s, rn, sf); tcg_rd = cpu_reg(s, rd); } + tcg_rn = read_cpu_reg_sp(s, rn, sf); tcg_rm = read_cpu_reg(s, rm, sf); ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); @@ -5828,6 +5830,21 @@ static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, } } +/* SRI: shift right with insert */ +static void handle_shri_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, + int size, int shift) +{ + int esize = 8 << size; + + /* shift count same as element size is valid but does nothing; + * special case to avoid potential shift by 64. + */ + if (shift != esize) { + tcg_gen_shri_i64(tcg_src, tcg_src, shift); + tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, 0, esize - shift); + } +} + /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ static void handle_scalar_simd_shri(DisasContext *s, bool is_u, int immh, int immb, @@ -5838,6 +5855,7 @@ static void handle_scalar_simd_shri(DisasContext *s, int shift = 2 * (8 << size) - immhb; bool accumulate = false; bool round = false; + bool insert = false; TCGv_i64 tcg_rn; TCGv_i64 tcg_rd; TCGv_i64 tcg_round; @@ -5857,6 +5875,9 @@ static void handle_scalar_simd_shri(DisasContext *s, case 0x06: /* SRSRA / URSRA (accum + rounding) */ accumulate = round = true; break; + case 0x08: /* SRI */ + insert = true; + break; } if (round) { @@ -5867,10 +5888,14 @@ static void handle_scalar_simd_shri(DisasContext *s, } tcg_rn = read_fp_dreg(s, rn); - tcg_rd = accumulate ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); + tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); - handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, - accumulate, is_u, size, shift); + if (insert) { + handle_shri_with_ins(tcg_rd, tcg_rn, size, shift); + } else { + handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, + accumulate, is_u, size, shift); + } write_fp_dreg(s, rd, tcg_rd); @@ -5908,6 +5933,374 @@ static void handle_scalar_simd_shli(DisasContext *s, bool insert, tcg_temp_free_i64(tcg_rd); } +/* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with + * (signed/unsigned) narrowing */ +static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, + bool is_u_shift, bool is_u_narrow, + int immh, int immb, int opcode, + int rn, int rd) +{ + int immhb = immh << 3 | immb; + int size = 32 - clz32(immh) - 1; + int esize = 8 << size; + int shift = (2 * esize) - immhb; + int elements = is_scalar ? 1 : (64 / esize); + bool round = extract32(opcode, 0, 1); + TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); + TCGv_i64 tcg_rn, tcg_rd, tcg_round; + TCGv_i32 tcg_rd_narrowed; + TCGv_i64 tcg_final; + + static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { + { gen_helper_neon_narrow_sat_s8, + gen_helper_neon_unarrow_sat8 }, + { gen_helper_neon_narrow_sat_s16, + gen_helper_neon_unarrow_sat16 }, + { gen_helper_neon_narrow_sat_s32, + gen_helper_neon_unarrow_sat32 }, + { NULL, NULL }, + }; + static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { + gen_helper_neon_narrow_sat_u8, + gen_helper_neon_narrow_sat_u16, + gen_helper_neon_narrow_sat_u32, + NULL + }; + NeonGenNarrowEnvFn *narrowfn; + + int i; + + assert(size < 4); + + if (extract32(immh, 3, 1)) { + unallocated_encoding(s); + return; + } + + if (is_u_shift) { + narrowfn = unsigned_narrow_fns[size]; + } else { + narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; + } + + tcg_rn = tcg_temp_new_i64(); + tcg_rd = tcg_temp_new_i64(); + tcg_rd_narrowed = tcg_temp_new_i32(); + tcg_final = tcg_const_i64(0); + + if (round) { + uint64_t round_const = 1ULL << (shift - 1); + tcg_round = tcg_const_i64(round_const); + } else { + TCGV_UNUSED_I64(tcg_round); + } + + for (i = 0; i < elements; i++) { + read_vec_element(s, tcg_rn, rn, i, ldop); + handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, + false, is_u_shift, size+1, shift); + narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); + tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); + tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); + } + + if (!is_q) { + clear_vec_high(s, rd); + write_vec_element(s, tcg_final, rd, 0, MO_64); + } else { + write_vec_element(s, tcg_final, rd, 1, MO_64); + } + + if (round) { + tcg_temp_free_i64(tcg_round); + } + tcg_temp_free_i64(tcg_rn); + tcg_temp_free_i64(tcg_rd); + tcg_temp_free_i32(tcg_rd_narrowed); + tcg_temp_free_i64(tcg_final); + return; +} + +/* SQSHLU, UQSHL, SQSHL: saturating left shifts */ +static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, + bool src_unsigned, bool dst_unsigned, + int immh, int immb, int rn, int rd) +{ + int immhb = immh << 3 | immb; + int size = 32 - clz32(immh) - 1; + int shift = immhb - (8 << size); + int pass; + + assert(immh != 0); + assert(!(scalar && is_q)); + + if (!scalar) { + if (!is_q && extract32(immh, 3, 1)) { + unallocated_encoding(s); + return; + } + + /* Since we use the variable-shift helpers we must + * replicate the shift count into each element of + * the tcg_shift value. + */ + switch (size) { + case 0: + shift |= shift << 8; + /* fall through */ + case 1: + shift |= shift << 16; + break; + case 2: + case 3: + break; + default: + g_assert_not_reached(); + } + } + + if (size == 3) { + TCGv_i64 tcg_shift = tcg_const_i64(shift); + static NeonGenTwo64OpEnvFn * const fns[2][2] = { + { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, + { NULL, gen_helper_neon_qshl_u64 }, + }; + NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; + int maxpass = is_q ? 2 : 1; + + for (pass = 0; pass < maxpass; pass++) { + TCGv_i64 tcg_op = tcg_temp_new_i64(); + + read_vec_element(s, tcg_op, rn, pass, MO_64); + genfn(tcg_op, cpu_env, tcg_op, tcg_shift); + write_vec_element(s, tcg_op, rd, pass, MO_64); + + tcg_temp_free_i64(tcg_op); + } + tcg_temp_free_i64(tcg_shift); + + if (!is_q) { + clear_vec_high(s, rd); + } + } else { + TCGv_i32 tcg_shift = tcg_const_i32(shift); + static NeonGenTwoOpEnvFn * const fns[2][2][3] = { + { + { gen_helper_neon_qshl_s8, + gen_helper_neon_qshl_s16, + gen_helper_neon_qshl_s32 }, + { gen_helper_neon_qshlu_s8, + gen_helper_neon_qshlu_s16, + gen_helper_neon_qshlu_s32 } + }, { + { NULL, NULL, NULL }, + { gen_helper_neon_qshl_u8, + gen_helper_neon_qshl_u16, + gen_helper_neon_qshl_u32 } + } + }; + NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; + TCGMemOp memop = scalar ? size : MO_32; + int maxpass = scalar ? 1 : is_q ? 4 : 2; + + for (pass = 0; pass < maxpass; pass++) { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, memop); + genfn(tcg_op, cpu_env, tcg_op, tcg_shift); + if (scalar) { + switch (size) { + case 0: + tcg_gen_ext8u_i32(tcg_op, tcg_op); + break; + case 1: + tcg_gen_ext16u_i32(tcg_op, tcg_op); + break; + case 2: + break; + default: + g_assert_not_reached(); + } + write_fp_sreg(s, rd, tcg_op); + } else { + write_vec_element_i32(s, tcg_op, rd, pass, MO_32); + } + + tcg_temp_free_i32(tcg_op); + } + tcg_temp_free_i32(tcg_shift); + + if (!is_q && !scalar) { + clear_vec_high(s, rd); + } + } +} + +/* Common vector code for handling integer to FP conversion */ +static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, + int elements, int is_signed, + int fracbits, int size) +{ + bool is_double = size == 3 ? true : false; + TCGv_ptr tcg_fpst = get_fpstatus_ptr(); + TCGv_i32 tcg_shift = tcg_const_i32(fracbits); + TCGv_i64 tcg_int = tcg_temp_new_i64(); + TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); + int pass; + + for (pass = 0; pass < elements; pass++) { + read_vec_element(s, tcg_int, rn, pass, mop); + + if (is_double) { + TCGv_i64 tcg_double = tcg_temp_new_i64(); + if (is_signed) { + gen_helper_vfp_sqtod(tcg_double, tcg_int, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_uqtod(tcg_double, tcg_int, + tcg_shift, tcg_fpst); + } + if (elements == 1) { + write_fp_dreg(s, rd, tcg_double); + } else { + write_vec_element(s, tcg_double, rd, pass, MO_64); + } + tcg_temp_free_i64(tcg_double); + } else { + TCGv_i32 tcg_single = tcg_temp_new_i32(); + if (is_signed) { + gen_helper_vfp_sqtos(tcg_single, tcg_int, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_uqtos(tcg_single, tcg_int, + tcg_shift, tcg_fpst); + } + if (elements == 1) { + write_fp_sreg(s, rd, tcg_single); + } else { + write_vec_element_i32(s, tcg_single, rd, pass, MO_32); + } + tcg_temp_free_i32(tcg_single); + } + } + + if (!is_double && elements == 2) { + clear_vec_high(s, rd); + } + + tcg_temp_free_i64(tcg_int); + tcg_temp_free_ptr(tcg_fpst); + tcg_temp_free_i32(tcg_shift); +} + +/* UCVTF/SCVTF - Integer to FP conversion */ +static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, + bool is_q, bool is_u, + int immh, int immb, int opcode, + int rn, int rd) +{ + bool is_double = extract32(immh, 3, 1); + int size = is_double ? MO_64 : MO_32; + int elements; + int immhb = immh << 3 | immb; + int fracbits = (is_double ? 128 : 64) - immhb; + + if (!extract32(immh, 2, 2)) { + unallocated_encoding(s); + return; + } + + if (is_scalar) { + elements = 1; + } else { + elements = is_double ? 2 : is_q ? 4 : 2; + if (is_double && !is_q) { + unallocated_encoding(s); + return; + } + } + /* immh == 0 would be a failure of the decode logic */ + g_assert(immh); + + handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); +} + +/* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ +static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, + bool is_q, bool is_u, + int immh, int immb, int rn, int rd) +{ + bool is_double = extract32(immh, 3, 1); + int immhb = immh << 3 | immb; + int fracbits = (is_double ? 128 : 64) - immhb; + int pass; + TCGv_ptr tcg_fpstatus; + TCGv_i32 tcg_rmode, tcg_shift; + + if (!extract32(immh, 2, 2)) { + unallocated_encoding(s); + return; + } + + if (!is_scalar && !is_q && is_double) { + unallocated_encoding(s); + return; + } + + assert(!(is_scalar && is_q)); + + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_fpstatus = get_fpstatus_ptr(); + tcg_shift = tcg_const_i32(fracbits); + + if (is_double) { + int maxpass = is_scalar ? 1 : is_q ? 2 : 1; + + for (pass = 0; pass < maxpass; pass++) { + TCGv_i64 tcg_op = tcg_temp_new_i64(); + + read_vec_element(s, tcg_op, rn, pass, MO_64); + if (is_u) { + gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); + } + write_vec_element(s, tcg_op, rd, pass, MO_64); + tcg_temp_free_i64(tcg_op); + } + if (!is_q) { + clear_vec_high(s, rd); + } + } else { + int maxpass = is_scalar ? 1 : is_q ? 4 : 2; + for (pass = 0; pass < maxpass; pass++) { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, MO_32); + if (is_u) { + gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); + } + if (is_scalar) { + write_fp_sreg(s, rd, tcg_op); + } else { + write_vec_element_i32(s, tcg_op, rd, pass, MO_32); + } + tcg_temp_free_i32(tcg_op); + } + if (!is_q && !is_scalar) { + clear_vec_high(s, rd); + } + } + + tcg_temp_free_ptr(tcg_fpstatus); + tcg_temp_free_i32(tcg_shift); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); +} + /* C3.6.9 AdvSIMD scalar shift by immediate * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 * +-----+---+-------------+------+------+--------+---+------+------+ @@ -5925,7 +6318,18 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) int immh = extract32(insn, 19, 4); bool is_u = extract32(insn, 29, 1); + if (immh == 0) { + unallocated_encoding(s); + return; + } + switch (opcode) { + case 0x08: /* SRI */ + if (!is_u) { + unallocated_encoding(s); + return; + } + /* fall through */ case 0x00: /* SSHR / USHR */ case 0x02: /* SSRA / USRA */ case 0x04: /* SRSHR / URSHR */ @@ -5935,8 +6339,39 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) case 0x0a: /* SHL / SLI */ handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); break; + case 0x1c: /* SCVTF, UCVTF */ + handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, + opcode, rn, rd); + break; + case 0x10: /* SQSHRUN, SQSHRUN2 */ + case 0x11: /* SQRSHRUN, SQRSHRUN2 */ + if (!is_u) { + unallocated_encoding(s); + return; + } + handle_vec_simd_sqshrn(s, true, false, false, true, + immh, immb, opcode, rn, rd); + break; + case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ + case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ + handle_vec_simd_sqshrn(s, true, false, is_u, is_u, + immh, immb, opcode, rn, rd); + break; + case 0xc: /* SQSHLU */ + if (!is_u) { + unallocated_encoding(s); + return; + } + handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); + break; + case 0xe: /* SQSHL, UQSHL */ + handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); + break; + case 0x1f: /* FCVTZS, FCVTZU */ + handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); + break; default: - unsupported_encoding(s, insn); + unallocated_encoding(s); break; } } @@ -6483,21 +6918,38 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) } static void handle_2misc_64(DisasContext *s, int opcode, bool u, - TCGv_i64 tcg_rd, TCGv_i64 tcg_rn) + TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, + TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) { /* Handle 64->64 opcodes which are shared between the scalar and * vector 2-reg-misc groups. We cover every integer opcode where size == 3 * is valid in either group and also the double-precision fp ops. + * The caller only need provide tcg_rmode and tcg_fpstatus if the op + * requires them. */ TCGCond cond; switch (opcode) { + case 0x4: /* CLS, CLZ */ + if (u) { + gen_helper_clz64(tcg_rd, tcg_rn); + } else { + gen_helper_cls64(tcg_rd, tcg_rn); + } + break; case 0x5: /* NOT */ /* This opcode is shared with CNT and RBIT but we have earlier * enforced that size == 3 if and only if this is the NOT insn. */ tcg_gen_not_i64(tcg_rd, tcg_rn); break; + case 0x7: /* SQABS, SQNEG */ + if (u) { + gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); + } else { + gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); + } + break; case 0xa: /* CMLT */ /* 64 bit integer comparison against zero, result is * test ? (2^64 - 1) : 0. We implement via setcond(!test) and @@ -6531,6 +6983,42 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, case 0x6f: /* FNEG */ gen_helper_vfp_negd(tcg_rd, tcg_rn); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); + break; + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + { + TCGv_i32 tcg_shift = tcg_const_i32(0); + gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); + tcg_temp_free_i32(tcg_shift); + break; + } + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + { + TCGv_i32 tcg_shift = tcg_const_i32(0); + gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); + tcg_temp_free_i32(tcg_shift); + break; + } + case 0x18: /* FRINTN */ + case 0x19: /* FRINTM */ + case 0x38: /* FRINTP */ + case 0x39: /* FRINTZ */ + case 0x58: /* FRINTA */ + case 0x79: /* FRINTI */ + gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); + break; + case 0x59: /* FRINTX */ + gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -6645,6 +7133,289 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, tcg_temp_free_ptr(fpst); } +static void handle_2misc_reciprocal(DisasContext *s, int opcode, + bool is_scalar, bool is_u, bool is_q, + int size, int rn, int rd) +{ + bool is_double = (size == 3); + TCGv_ptr fpst = get_fpstatus_ptr(); + + if (is_double) { + TCGv_i64 tcg_op = tcg_temp_new_i64(); + TCGv_i64 tcg_res = tcg_temp_new_i64(); + int pass; + + for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { + read_vec_element(s, tcg_op, rn, pass, MO_64); + switch (opcode) { + case 0x3d: /* FRECPE */ + gen_helper_recpe_f64(tcg_res, tcg_op, fpst); + break; + case 0x3f: /* FRECPX */ + gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); + break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); + break; + default: + g_assert_not_reached(); + } + write_vec_element(s, tcg_res, rd, pass, MO_64); + } + if (is_scalar) { + clear_vec_high(s, rd); + } + + tcg_temp_free_i64(tcg_res); + tcg_temp_free_i64(tcg_op); + } else { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + int pass, maxpasses; + + if (is_scalar) { + maxpasses = 1; + } else { + maxpasses = is_q ? 4 : 2; + } + + for (pass = 0; pass < maxpasses; pass++) { + read_vec_element_i32(s, tcg_op, rn, pass, MO_32); + + switch (opcode) { + case 0x3c: /* URECPE */ + gen_helper_recpe_u32(tcg_res, tcg_op, fpst); + break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f32(tcg_res, tcg_op, fpst); + break; + case 0x3f: /* FRECPX */ + gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); + break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); + break; + default: + g_assert_not_reached(); + } + + if (is_scalar) { + write_fp_sreg(s, rd, tcg_res); + } else { + write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + } + } + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); + if (!is_q && !is_scalar) { + clear_vec_high(s, rd); + } + } + tcg_temp_free_ptr(fpst); +} + +static void handle_2misc_narrow(DisasContext *s, bool scalar, + int opcode, bool u, bool is_q, + int size, int rn, int rd) +{ + /* Handle 2-reg-misc ops which are narrowing (so each 2*size element + * in the source becomes a size element in the destination). + */ + int pass; + TCGv_i32 tcg_res[2]; + int destelt = is_q ? 2 : 0; + int passes = scalar ? 1 : 2; + + if (scalar) { + tcg_res[1] = tcg_const_i32(0); + } + + for (pass = 0; pass < passes; pass++) { + TCGv_i64 tcg_op = tcg_temp_new_i64(); + NeonGenNarrowFn *genfn = NULL; + NeonGenNarrowEnvFn *genenvfn = NULL; + + if (scalar) { + read_vec_element(s, tcg_op, rn, pass, size + 1); + } else { + read_vec_element(s, tcg_op, rn, pass, MO_64); + } + tcg_res[pass] = tcg_temp_new_i32(); + + switch (opcode) { + case 0x12: /* XTN, SQXTUN */ + { + static NeonGenNarrowFn * const xtnfns[3] = { + gen_helper_neon_narrow_u8, + gen_helper_neon_narrow_u16, + tcg_gen_trunc_i64_i32, + }; + static NeonGenNarrowEnvFn * const sqxtunfns[3] = { + gen_helper_neon_unarrow_sat8, + gen_helper_neon_unarrow_sat16, + gen_helper_neon_unarrow_sat32, + }; + if (u) { + genenvfn = sqxtunfns[size]; + } else { + genfn = xtnfns[size]; + } + break; + } + case 0x14: /* SQXTN, UQXTN */ + { + static NeonGenNarrowEnvFn * const fns[3][2] = { + { gen_helper_neon_narrow_sat_s8, + gen_helper_neon_narrow_sat_u8 }, + { gen_helper_neon_narrow_sat_s16, + gen_helper_neon_narrow_sat_u16 }, + { gen_helper_neon_narrow_sat_s32, + gen_helper_neon_narrow_sat_u32 }, + }; + genenvfn = fns[size][u]; + break; + } + case 0x16: /* FCVTN, FCVTN2 */ + /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ + if (size == 2) { + gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); + } else { + TCGv_i32 tcg_lo = tcg_temp_new_i32(); + TCGv_i32 tcg_hi = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(tcg_lo, tcg_op); + gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env); + tcg_gen_shri_i64(tcg_op, tcg_op, 32); + tcg_gen_trunc_i64_i32(tcg_hi, tcg_op); + gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env); + tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); + tcg_temp_free_i32(tcg_lo); + tcg_temp_free_i32(tcg_hi); + } + break; + case 0x56: /* FCVTXN, FCVTXN2 */ + /* 64 bit to 32 bit float conversion + * with von Neumann rounding (round to odd) + */ + assert(size == 2); + gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); + break; + default: + g_assert_not_reached(); + } + + if (genfn) { + genfn(tcg_res[pass], tcg_op); + } else if (genenvfn) { + genenvfn(tcg_res[pass], cpu_env, tcg_op); + } + + tcg_temp_free_i64(tcg_op); + } + + for (pass = 0; pass < 2; pass++) { + write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); + tcg_temp_free_i32(tcg_res[pass]); + } + if (!is_q) { + clear_vec_high(s, rd); + } +} + +/* Remaining saturating accumulating ops */ +static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, + bool is_q, int size, int rn, int rd) +{ + bool is_double = (size == 3); + + if (is_double) { + TCGv_i64 tcg_rn = tcg_temp_new_i64(); + TCGv_i64 tcg_rd = tcg_temp_new_i64(); + int pass; + + for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { + read_vec_element(s, tcg_rn, rn, pass, MO_64); + read_vec_element(s, tcg_rd, rd, pass, MO_64); + + if (is_u) { /* USQADD */ + gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); + } else { /* SUQADD */ + gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); + } + write_vec_element(s, tcg_rd, rd, pass, MO_64); + } + if (is_scalar) { + clear_vec_high(s, rd); + } + + tcg_temp_free_i64(tcg_rd); + tcg_temp_free_i64(tcg_rn); + } else { + TCGv_i32 tcg_rn = tcg_temp_new_i32(); + TCGv_i32 tcg_rd = tcg_temp_new_i32(); + int pass, maxpasses; + + if (is_scalar) { + maxpasses = 1; + } else { + maxpasses = is_q ? 4 : 2; + } + + for (pass = 0; pass < maxpasses; pass++) { + if (is_scalar) { + read_vec_element_i32(s, tcg_rn, rn, pass, size); + read_vec_element_i32(s, tcg_rd, rd, pass, size); + } else { + read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); + read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); + } + + if (is_u) { /* USQADD */ + switch (size) { + case 0: + gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); + break; + case 1: + gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); + break; + case 2: + gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); + break; + default: + g_assert_not_reached(); + } + } else { /* SUQADD */ + switch (size) { + case 0: + gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); + break; + case 1: + gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); + break; + case 2: + gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); + break; + default: + g_assert_not_reached(); + } + } + + if (is_scalar) { + TCGv_i64 tcg_zero = tcg_const_i64(0); + write_vec_element(s, tcg_zero, rd, 0, MO_64); + tcg_temp_free_i64(tcg_zero); + } + write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); + } + + if (!is_q) { + clear_vec_high(s, rd); + } + + tcg_temp_free_i32(tcg_rd); + tcg_temp_free_i32(tcg_rn); + } +} + /* C3.6.12 AdvSIMD scalar two reg misc * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +-----+---+-----------+------+-----------+--------+-----+------+------+ @@ -6658,8 +7429,17 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) int opcode = extract32(insn, 12, 5); int size = extract32(insn, 22, 2); bool u = extract32(insn, 29, 1); + bool is_fcvt = false; + int rmode; + TCGv_i32 tcg_rmode; + TCGv_ptr tcg_fpstatus; switch (opcode) { + case 0x3: /* USQADD / SUQADD*/ + handle_2misc_satacc(s, true, u, false, size, rn, rd); + return; + case 0x7: /* SQABS / SQNEG */ + break; case 0xa: /* CMLT */ if (u) { unallocated_encoding(s); @@ -6674,6 +7454,19 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) return; } break; + case 0x12: /* SQXTUN */ + if (u) { + unallocated_encoding(s); + return; + } + /* fall through */ + case 0x14: /* SQXTN, UQXTN */ + if (size == 3) { + unallocated_encoding(s); + return; + } + handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); + return; case 0xc ... 0xf: case 0x16 ... 0x1d: case 0x1f: @@ -6690,23 +7483,41 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) case 0x6d: /* FCMLE (zero) */ handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); return; + case 0x1d: /* SCVTF */ + case 0x5d: /* UCVTF */ + { + bool is_signed = (opcode == 0x1d); + handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); + return; + } + case 0x3d: /* FRECPE */ + case 0x3f: /* FRECPX */ + case 0x7d: /* FRSQRTE */ + handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); + return; case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ - case 0x1c: /* FCVTAS */ - case 0x1d: /* SCVTF */ case 0x3a: /* FCVTPS */ case 0x3b: /* FCVTZS */ - case 0x3d: /* FRECPE */ - case 0x3f: /* FRECPX */ - case 0x56: /* FCVTXN, FCVTXN2 */ case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ - case 0x5c: /* FCVTAU */ - case 0x5d: /* UCVTF */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ - case 0x7d: /* FRSQRTE */ - unsupported_encoding(s, insn); + is_fcvt = true; + rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); + break; + case 0x1c: /* FCVTAS */ + case 0x5c: /* FCVTAU */ + /* TIEAWAY doesn't fit in the usual rounding mode encoding */ + is_fcvt = true; + rmode = FPROUNDING_TIEAWAY; + break; + case 0x56: /* FCVTXN, FCVTXN2 */ + if (size == 2) { + unallocated_encoding(s); + return; + } + handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); return; default: unallocated_encoding(s); @@ -6714,26 +7525,81 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) } break; default: - /* Other categories of encoding in this class: - * + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64 - * + SQXTN/SQXTN2/SQXTUN/SQXTUN2/UQXTN/UQXTN2: - * narrowing saturate ops: size 64/32/16 -> 32/16/8 - */ - unsupported_encoding(s, insn); + unallocated_encoding(s); return; } + if (is_fcvt) { + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_fpstatus = get_fpstatus_ptr(); + } else { + TCGV_UNUSED_I32(tcg_rmode); + TCGV_UNUSED_PTR(tcg_fpstatus); + } + if (size == 3) { TCGv_i64 tcg_rn = read_fp_dreg(s, rn); TCGv_i64 tcg_rd = tcg_temp_new_i64(); - handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn); + handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); write_fp_dreg(s, rd, tcg_rd); tcg_temp_free_i64(tcg_rd); tcg_temp_free_i64(tcg_rn); } else { - /* the 'size might not be 64' ops aren't implemented yet */ - g_assert_not_reached(); + TCGv_i32 tcg_rn = tcg_temp_new_i32(); + TCGv_i32 tcg_rd = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_rn, rn, 0, size); + + switch (opcode) { + case 0x7: /* SQABS, SQNEG */ + { + NeonGenOneOpEnvFn *genfn; + static NeonGenOneOpEnvFn * const fns[3][2] = { + { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, + { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, + { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, + }; + genfn = fns[size][u]; + genfn(tcg_rd, cpu_env, tcg_rn); + break; + } + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + { + TCGv_i32 tcg_shift = tcg_const_i32(0); + gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); + tcg_temp_free_i32(tcg_shift); + break; + } + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + { + TCGv_i32 tcg_shift = tcg_const_i32(0); + gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); + tcg_temp_free_i32(tcg_shift); + break; + } + default: + g_assert_not_reached(); + } + + write_fp_sreg(s, rd, tcg_rd); + tcg_temp_free_i32(tcg_rd); + tcg_temp_free_i32(tcg_rn); + } + + if (is_fcvt) { + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_ptr(tcg_fpstatus); } } @@ -6746,6 +7612,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, int shift = 2 * (8 << size) - immhb; bool accumulate = false; bool round = false; + bool insert = false; int dsize = is_q ? 128 : 64; int esize = 8 << size; int elements = dsize/esize; @@ -6775,6 +7642,9 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, case 0x06: /* SRSRA / URSRA (accum + rounding) */ accumulate = round = true; break; + case 0x08: /* SRI */ + insert = true; + break; } if (round) { @@ -6786,12 +7656,16 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, for (i = 0; i < elements; i++) { read_vec_element(s, tcg_rn, rn, i, memop); - if (accumulate) { + if (accumulate || insert) { read_vec_element(s, tcg_rd, rd, i, memop); } - handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, - accumulate, is_u, size, shift); + if (insert) { + handle_shri_with_ins(tcg_rd, tcg_rn, size, shift); + } else { + handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, + accumulate, is_u, size, shift); + } write_vec_element(s, tcg_rd, rd, i, size); } @@ -6878,6 +7752,62 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, } } +/* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ +static void handle_vec_simd_shrn(DisasContext *s, bool is_q, + int immh, int immb, int opcode, int rn, int rd) +{ + int immhb = immh << 3 | immb; + int size = 32 - clz32(immh) - 1; + int dsize = 64; + int esize = 8 << size; + int elements = dsize/esize; + int shift = (2 * esize) - immhb; + bool round = extract32(opcode, 0, 1); + TCGv_i64 tcg_rn, tcg_rd, tcg_final; + TCGv_i64 tcg_round; + int i; + + if (extract32(immh, 3, 1)) { + unallocated_encoding(s); + return; + } + + tcg_rn = tcg_temp_new_i64(); + tcg_rd = tcg_temp_new_i64(); + tcg_final = tcg_temp_new_i64(); + read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); + + if (round) { + uint64_t round_const = 1ULL << (shift - 1); + tcg_round = tcg_const_i64(round_const); + } else { + TCGV_UNUSED_I64(tcg_round); + } + + for (i = 0; i < elements; i++) { + read_vec_element(s, tcg_rn, rn, i, size+1); + handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, + false, true, size+1, shift); + + tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); + } + + if (!is_q) { + clear_vec_high(s, rd); + write_vec_element(s, tcg_final, rd, 0, MO_64); + } else { + write_vec_element(s, tcg_final, rd, 1, MO_64); + } + + if (round) { + tcg_temp_free_i64(tcg_round); + } + tcg_temp_free_i64(tcg_rn); + tcg_temp_free_i64(tcg_rd); + tcg_temp_free_i64(tcg_final); + return; +} + /* C3.6.14 AdvSIMD shift by immediate * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 @@ -6896,6 +7826,12 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) bool is_q = extract32(insn, 30, 1); switch (opcode) { + case 0x08: /* SRI */ + if (!is_u) { + unallocated_encoding(s); + return; + } + /* fall through */ case 0x00: /* SSHR / USHR */ case 0x02: /* SSRA / USRA (accumulate) */ case 0x04: /* SRSHR / URSHR (rounding) */ @@ -6905,15 +7841,42 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) case 0x0a: /* SHL / SLI */ handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); break; + case 0x10: /* SHRN */ + case 0x11: /* RSHRN / SQRSHRUN */ + if (is_u) { + handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, + opcode, rn, rd); + } else { + handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); + } + break; + case 0x12: /* SQSHRN / UQSHRN */ + case 0x13: /* SQRSHRN / UQRSHRN */ + handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, + opcode, rn, rd); + break; case 0x14: /* SSHLL / USHLL */ handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); break; + case 0x1c: /* SCVTF / UCVTF */ + handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, + opcode, rn, rd); + break; + case 0xc: /* SQSHLU */ + if (!is_u) { + unallocated_encoding(s); + return; + } + handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); + break; + case 0xe: /* SQSHL, UQSHL */ + handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); + break; + case 0x1f: /* FCVTZS/ FCVTZU */ + handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); + return; default: - /* We don't currently implement any of the Narrow or saturating shifts; - * nor do we implement the fixed-point conversions in this - * encoding group (SCVTF, FCVTZS, UCVTF, FCVTZU). - */ - unsupported_encoding(s, insn); + unallocated_encoding(s); return; } } @@ -7124,6 +8087,10 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, tcg_passres, tcg_passres); break; + case 14: /* PMULL */ + assert(size == 0); + gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2); + break; default: g_assert_not_reached(); } @@ -7243,6 +8210,30 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, } } +static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm) +{ + /* PMULL of 64 x 64 -> 128 is an odd special case because it + * is the only three-reg-diff instruction which produces a + * 128-bit wide result from a single operation. However since + * it's possible to calculate the two halves more or less + * separately we just use two helper calls. + */ + TCGv_i64 tcg_op1 = tcg_temp_new_i64(); + TCGv_i64 tcg_op2 = tcg_temp_new_i64(); + TCGv_i64 tcg_res = tcg_temp_new_i64(); + + read_vec_element(s, tcg_op1, rn, is_q, MO_64); + read_vec_element(s, tcg_op2, rm, is_q, MO_64); + gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2); + write_vec_element(s, tcg_res, rd, 0, MO_64); + gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2); + write_vec_element(s, tcg_res, rd, 1, MO_64); + + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2); + tcg_temp_free_i64(tcg_res); +} + /* C3.6.15 AdvSIMD three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -7293,8 +8284,15 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - unsupported_encoding(s, insn); - break; + if (size == 3) { + if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)) { + unallocated_encoding(s); + return; + } + handle_pmull_64(s, is_q, rd, rn, rm); + return; + } + goto is_widening; case 9: /* SQDMLAL, SQDMLAL2 */ case 11: /* SQDMLSL, SQDMLSL2 */ case 13: /* SQDMULL, SQDMULL2 */ @@ -7315,6 +8313,7 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } + is_widening: handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); break; default: @@ -7991,76 +8990,48 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) } } -static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q, - int size, int rn, int rd) +static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, + int size, int rn, int rd) { - /* Handle 2-reg-misc ops which are narrowing (so each 2*size element - * in the source becomes a size element in the destination). + /* Handle 2-reg-misc ops which are widening (so each size element + * in the source becomes a 2*size element in the destination. + * The only instruction like this is FCVTL. */ int pass; - TCGv_i32 tcg_res[2]; - int destelt = is_q ? 2 : 0; - for (pass = 0; pass < 2; pass++) { - TCGv_i64 tcg_op = tcg_temp_new_i64(); - NeonGenNarrowFn *genfn = NULL; - NeonGenNarrowEnvFn *genenvfn = NULL; + if (size == 3) { + /* 32 -> 64 bit fp conversion */ + TCGv_i64 tcg_res[2]; + int srcelt = is_q ? 2 : 0; - read_vec_element(s, tcg_op, rn, pass, MO_64); - tcg_res[pass] = tcg_temp_new_i32(); + for (pass = 0; pass < 2; pass++) { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + tcg_res[pass] = tcg_temp_new_i64(); - switch (opcode) { - case 0x12: /* XTN, SQXTUN */ - { - static NeonGenNarrowFn * const xtnfns[3] = { - gen_helper_neon_narrow_u8, - gen_helper_neon_narrow_u16, - tcg_gen_trunc_i64_i32, - }; - static NeonGenNarrowEnvFn * const sqxtunfns[3] = { - gen_helper_neon_unarrow_sat8, - gen_helper_neon_unarrow_sat16, - gen_helper_neon_unarrow_sat32, - }; - if (u) { - genenvfn = sqxtunfns[size]; - } else { - genfn = xtnfns[size]; - } - break; - } - case 0x14: /* SQXTN, UQXTN */ - { - static NeonGenNarrowEnvFn * const fns[3][2] = { - { gen_helper_neon_narrow_sat_s8, - gen_helper_neon_narrow_sat_u8 }, - { gen_helper_neon_narrow_sat_s16, - gen_helper_neon_narrow_sat_u16 }, - { gen_helper_neon_narrow_sat_s32, - gen_helper_neon_narrow_sat_u32 }, - }; - genenvfn = fns[size][u]; - break; - } - default: - g_assert_not_reached(); + read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); + gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); + tcg_temp_free_i32(tcg_op); } - - if (genfn) { - genfn(tcg_res[pass], tcg_op); - } else { - genenvfn(tcg_res[pass], cpu_env, tcg_op); + for (pass = 0; pass < 2; pass++) { + write_vec_element(s, tcg_res[pass], rd, pass, MO_64); + tcg_temp_free_i64(tcg_res[pass]); } + } else { + /* 16 -> 32 bit fp conversion */ + int srcelt = is_q ? 4 : 0; + TCGv_i32 tcg_res[4]; - tcg_temp_free_i64(tcg_op); - } + for (pass = 0; pass < 4; pass++) { + tcg_res[pass] = tcg_temp_new_i32(); - for (pass = 0; pass < 2; pass++) { - write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); - tcg_temp_free_i32(tcg_res[pass]); - } - if (!is_q) { - clear_vec_high(s, rd); + read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); + gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], + cpu_env); + } + for (pass = 0; pass < 4; pass++) { + write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); + tcg_temp_free_i32(tcg_res[pass]); + } } } @@ -8133,6 +9104,108 @@ static void handle_rev(DisasContext *s, int opcode, bool u, } } +static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, + bool is_q, int size, int rn, int rd) +{ + /* Implement the pairwise operations from 2-misc: + * SADDLP, UADDLP, SADALP, UADALP. + * These all add pairs of elements in the input to produce a + * double-width result element in the output (possibly accumulating). + */ + bool accum = (opcode == 0x6); + int maxpass = is_q ? 2 : 1; + int pass; + TCGv_i64 tcg_res[2]; + + if (size == 2) { + /* 32 + 32 -> 64 op */ + TCGMemOp memop = size + (u ? 0 : MO_SIGN); + + for (pass = 0; pass < maxpass; pass++) { + TCGv_i64 tcg_op1 = tcg_temp_new_i64(); + TCGv_i64 tcg_op2 = tcg_temp_new_i64(); + + tcg_res[pass] = tcg_temp_new_i64(); + + read_vec_element(s, tcg_op1, rn, pass * 2, memop); + read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); + tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); + if (accum) { + read_vec_element(s, tcg_op1, rd, pass, MO_64); + tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + } + + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2); + } + } else { + for (pass = 0; pass < maxpass; pass++) { + TCGv_i64 tcg_op = tcg_temp_new_i64(); + NeonGenOneOpFn *genfn; + static NeonGenOneOpFn * const fns[2][2] = { + { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, + { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, + }; + + genfn = fns[size][u]; + + tcg_res[pass] = tcg_temp_new_i64(); + + read_vec_element(s, tcg_op, rn, pass, MO_64); + genfn(tcg_res[pass], tcg_op); + + if (accum) { + read_vec_element(s, tcg_op, rd, pass, MO_64); + if (size == 0) { + gen_helper_neon_addl_u16(tcg_res[pass], + tcg_res[pass], tcg_op); + } else { + gen_helper_neon_addl_u32(tcg_res[pass], + tcg_res[pass], tcg_op); + } + } + tcg_temp_free_i64(tcg_op); + } + } + if (!is_q) { + tcg_res[1] = tcg_const_i64(0); + } + for (pass = 0; pass < 2; pass++) { + write_vec_element(s, tcg_res[pass], rd, pass, MO_64); + tcg_temp_free_i64(tcg_res[pass]); + } +} + +static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) +{ + /* Implement SHLL and SHLL2 */ + int pass; + int part = is_q ? 2 : 0; + TCGv_i64 tcg_res[2]; + + for (pass = 0; pass < 2; pass++) { + static NeonGenWidenFn * const widenfns[3] = { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + }; + NeonGenWidenFn *widenfn = widenfns[size]; + TCGv_i32 tcg_op = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); + tcg_res[pass] = tcg_temp_new_i64(); + widenfn(tcg_res[pass], tcg_op); + tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); + + tcg_temp_free_i32(tcg_op); + } + + for (pass = 0; pass < 2; pass++) { + write_vec_element(s, tcg_res[pass], rd, pass, MO_64); + tcg_temp_free_i64(tcg_res[pass]); + } +} + /* C3.6.17 AdvSIMD two reg misc * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +---+---+---+-----------+------+-----------+--------+-----+------+------+ @@ -8147,6 +9220,11 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) bool is_q = extract32(insn, 30, 1); int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); + bool need_fpstatus = false; + bool need_rmode = false; + int rmode = -1; + TCGv_i32 tcg_rmode; + TCGv_ptr tcg_fpstatus; switch (opcode) { case 0x0: /* REV64, REV32 */ @@ -8173,23 +9251,28 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - handle_2misc_narrow(s, opcode, u, is_q, size, rn, rd); + handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); return; - case 0x2: /* SADDLP, UADDLP */ case 0x4: /* CLS, CLZ */ + if (size == 3) { + unallocated_encoding(s); + return; + } + break; + case 0x2: /* SADDLP, UADDLP */ case 0x6: /* SADALP, UADALP */ if (size == 3) { unallocated_encoding(s); return; } - unsupported_encoding(s, insn); + handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); return; case 0x13: /* SHLL, SHLL2 */ if (u == 0 || size == 3) { unallocated_encoding(s); return; } - unsupported_encoding(s, insn); + handle_shll(s, is_q, size, rn, rd); return; case 0xa: /* CMLT */ if (u == 1) { @@ -8206,13 +9289,18 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } break; case 0x3: /* SUQADD, USQADD */ - case 0x7: /* SQABS, SQNEG */ if (size == 3 && !is_q) { unallocated_encoding(s); return; } - unsupported_encoding(s, insn); + handle_2misc_satacc(s, false, u, is_q, size, rn, rd); return; + case 0x7: /* SQABS, SQNEG */ + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; case 0xc ... 0xf: case 0x16 ... 0x1d: case 0x1f: @@ -8220,8 +9308,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) /* Floating point: U, size[1] and opcode indicate operation; * size[0] indicates single or double precision. */ + int is_double = extract32(size, 0, 1); opcode |= (extract32(size, 1, 1) << 5) | (u << 6); - size = extract32(size, 0, 1) ? 3 : 2; + size = is_double ? 3 : 2; switch (opcode) { case 0x2f: /* FABS */ case 0x6f: /* FNEG */ @@ -8230,6 +9319,18 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) return; } break; + case 0x1d: /* SCVTF */ + case 0x5d: /* UCVTF */ + { + bool is_signed = (opcode == 0x1d) ? true : false; + int elements = is_double ? 2 : is_q ? 4 : 2; + if (is_double && !is_q) { + unallocated_encoding(s); + return; + } + handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); + return; + } case 0x2c: /* FCMGT (zero) */ case 0x2d: /* FCMEQ (zero) */ case 0x2e: /* FCMLT (zero) */ @@ -8241,35 +9342,98 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); return; - case 0x16: /* FCVTN, FCVTN2 */ - case 0x17: /* FCVTL, FCVTL2 */ - case 0x18: /* FRINTN */ - case 0x19: /* FRINTM */ + case 0x7f: /* FSQRT */ + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ - case 0x1c: /* FCVTAS */ - case 0x1d: /* SCVTF */ - case 0x38: /* FRINTP */ - case 0x39: /* FRINTZ */ case 0x3a: /* FCVTPS */ case 0x3b: /* FCVTZS */ - case 0x3c: /* URECPE */ - case 0x3d: /* FRECPE */ - case 0x56: /* FCVTXN, FCVTXN2 */ - case 0x58: /* FRINTA */ - case 0x59: /* FRINTX */ case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ - case 0x5c: /* FCVTAU */ - case 0x5d: /* UCVTF */ - case 0x79: /* FRINTI */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ - case 0x7c: /* URSQRTE */ + need_fpstatus = true; + need_rmode = true; + rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; + case 0x5c: /* FCVTAU */ + case 0x1c: /* FCVTAS */ + need_fpstatus = true; + need_rmode = true; + rmode = FPROUNDING_TIEAWAY; + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; + case 0x3c: /* URECPE */ + if (size == 3) { + unallocated_encoding(s); + return; + } + /* fall through */ + case 0x3d: /* FRECPE */ case 0x7d: /* FRSQRTE */ - case 0x7f: /* FSQRT */ - unsupported_encoding(s, insn); + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); return; + case 0x56: /* FCVTXN, FCVTXN2 */ + if (size == 2) { + unallocated_encoding(s); + return; + } + /* fall through */ + case 0x16: /* FCVTN, FCVTN2 */ + /* handle_2misc_narrow does a 2*size -> size operation, but these + * instructions encode the source size rather than dest size. + */ + handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); + return; + case 0x17: /* FCVTL, FCVTL2 */ + handle_2misc_widening(s, opcode, is_q, size, rn, rd); + return; + case 0x18: /* FRINTN */ + case 0x19: /* FRINTM */ + case 0x38: /* FRINTP */ + case 0x39: /* FRINTZ */ + need_rmode = true; + rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); + /* fall through */ + case 0x59: /* FRINTX */ + case 0x79: /* FRINTI */ + need_fpstatus = true; + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; + case 0x58: /* FRINTA */ + need_rmode = true; + rmode = FPROUNDING_TIEAWAY; + need_fpstatus = true; + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; + case 0x7c: /* URSQRTE */ + if (size == 3) { + unallocated_encoding(s); + return; + } + need_fpstatus = true; + break; default: unallocated_encoding(s); return; @@ -8281,6 +9445,18 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) return; } + if (need_fpstatus) { + tcg_fpstatus = get_fpstatus_ptr(); + } else { + TCGV_UNUSED_PTR(tcg_fpstatus); + } + if (need_rmode) { + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + } else { + TCGV_UNUSED_I32(tcg_rmode); + } + if (size == 3) { /* All 64-bit element operations can be shared with scalar 2misc */ int pass; @@ -8291,7 +9467,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) read_vec_element(s, tcg_op, rn, pass, MO_64); - handle_2misc_64(s, opcode, u, tcg_res, tcg_op); + handle_2misc_64(s, opcode, u, tcg_res, tcg_op, + tcg_rmode, tcg_fpstatus); write_vec_element(s, tcg_res, rd, pass, MO_64); @@ -8327,6 +9504,20 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x9: /* CMEQ, CMLE */ cond = u ? TCG_COND_LE : TCG_COND_EQ; goto do_cmop; + case 0x4: /* CLS */ + if (u) { + gen_helper_clz32(tcg_res, tcg_op); + } else { + gen_helper_cls32(tcg_res, tcg_op); + } + break; + case 0x7: /* SQABS, SQNEG */ + if (u) { + gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); + } else { + gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); + } + break; case 0xb: /* ABS, NEG */ if (u) { tcg_gen_neg_i32(tcg_res, tcg_op); @@ -8344,6 +9535,47 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ gen_helper_vfp_negs(tcg_res, tcg_op); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); + break; + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + { + TCGv_i32 tcg_shift = tcg_const_i32(0); + gen_helper_vfp_tosls(tcg_res, tcg_op, + tcg_shift, tcg_fpstatus); + tcg_temp_free_i32(tcg_shift); + break; + } + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + { + TCGv_i32 tcg_shift = tcg_const_i32(0); + gen_helper_vfp_touls(tcg_res, tcg_op, + tcg_shift, tcg_fpstatus); + tcg_temp_free_i32(tcg_shift); + break; + } + case 0x18: /* FRINTN */ + case 0x19: /* FRINTM */ + case 0x38: /* FRINTP */ + case 0x39: /* FRINTZ */ + case 0x58: /* FRINTA */ + case 0x79: /* FRINTI */ + gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x59: /* FRINTX */ + gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x7c: /* URSQRTE */ + gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -8360,6 +9592,17 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) gen_helper_neon_cnt_u8(tcg_res, tcg_op); } break; + case 0x7: /* SQABS, SQNEG */ + { + NeonGenOneOpEnvFn *genfn; + static NeonGenOneOpEnvFn * const fns[2][2] = { + { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, + { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, + }; + genfn = fns[size][u]; + genfn(tcg_res, cpu_env, tcg_op); + break; + } case 0x8: /* CMGT, CMGE */ case 0x9: /* CMEQ, CMLE */ case 0xa: /* CMLT */ @@ -8407,6 +9650,21 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } } break; + case 0x4: /* CLS, CLZ */ + if (u) { + if (size == 0) { + gen_helper_neon_clz_u8(tcg_res, tcg_op); + } else { + gen_helper_neon_clz_u16(tcg_res, tcg_op); + } + } else { + if (size == 0) { + gen_helper_neon_cls_s8(tcg_res, tcg_op); + } else { + gen_helper_neon_cls_s16(tcg_res, tcg_op); + } + } + break; default: g_assert_not_reached(); } @@ -8421,6 +9679,14 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) if (!is_q) { clear_vec_high(s, rd); } + + if (need_rmode) { + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + } + if (need_fpstatus) { + tcg_temp_free_ptr(tcg_fpstatus); + } } /* C3.6.13 AdvSIMD scalar x indexed element @@ -9045,6 +10311,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, dc->vec_stride = 0; dc->cp_regs = cpu->cp_regs; dc->current_pl = arm_current_pl(env); + dc->features = env->features; init_tmp_a64_array(dc); @@ -9061,8 +10328,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_clear_temp_count(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will diff --git a/target-arm/translate.c b/target-arm/translate.c index 253d2a1..56e3b4b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3939,6 +3939,9 @@ static void gen_nop_hint(DisasContext *s, int val) s->is_jmp = DISAS_WFI; break; case 2: /* wfe */ + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_WFE; + break; case 4: /* sev */ case 5: /* sevl */ /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */ @@ -6679,17 +6682,33 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins break; } case NEON_2RM_VRECPE: - gen_helper_recpe_u32(tmp, tmp, cpu_env); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_recpe_u32(tmp, tmp, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } case NEON_2RM_VRSQRTE: - gen_helper_rsqrte_u32(tmp, tmp, cpu_env); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_rsqrte_u32(tmp, tmp, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } case NEON_2RM_VRECPE_F: - gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_recpe_f32(cpu_F0s, cpu_F0s, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } case NEON_2RM_VRSQRTE_F: - gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */ gen_vfp_sito(0, 1); break; @@ -10651,6 +10670,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); dc->cp_regs = cpu->cp_regs; dc->current_pl = arm_current_pl(env); + dc->features = env->features; cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); @@ -10730,8 +10750,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, } #endif - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will @@ -10800,7 +10820,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(env, "IO on conditional branch instruction"); + cpu_abort(cs, "IO on conditional branch instruction"); } gen_io_end(); } @@ -10857,6 +10877,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, case DISAS_WFI: gen_helper_wfi(cpu_env); break; + case DISAS_WFE: + gen_helper_wfe(cpu_env); + break; case DISAS_SWI: gen_exception(EXCP_SWI); break; diff --git a/target-arm/translate.h b/target-arm/translate.h index 67da699..3525ffc 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -26,6 +26,7 @@ typedef struct DisasContext { int aarch64; int current_pl; GHashTable *cp_regs; + uint64_t features; /* CPU features bits */ #define TMP_A64_MAX 16 int tmp_a64_count; TCGv_i64 tmp_a64[TMP_A64_MAX]; @@ -33,6 +34,11 @@ typedef struct DisasContext { extern TCGv_ptr cpu_env; +static inline int arm_dc_feature(DisasContext *dc, int feature) +{ + return (dc->features & (1ULL << feature)) != 0; +} + /* target-specific extra values for is_jmp */ /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. @@ -44,6 +50,8 @@ extern TCGv_ptr cpu_env; * emitting unreachable code at the end of the TB in the A64 decoder */ #define DISAS_EXC 6 +/* WFE */ +#define DISAS_WFE 7 #ifdef TARGET_AARCH64 void a64_translate_init(void); diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 1ac8124..20d8809 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -33,6 +33,11 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +static bool cris_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); +} + /* CPUClass::reset() */ static void cris_cpu_reset(CPUState *s) { @@ -44,9 +49,9 @@ static void cris_cpu_reset(CPUState *s) ccc->parent_reset(s); vr = env->pregs[PR_VR]; - memset(env, 0, offsetof(CPUCRISState, breakpoints)); + memset(env, 0, offsetof(CPUCRISState, load_info)); env->pregs[PR_VR] = vr; - tlb_flush(env, 1); + tlb_flush(s, 1); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ @@ -84,18 +89,7 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) CRISCPU *cpu_cris_init(const char *cpu_model) { - CRISCPU *cpu; - ObjectClass *oc; - - oc = cris_cpu_class_by_name(cpu_model); - if (oc == NULL) { - return NULL; - } - cpu = CRIS_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model)); } /* Sort alphabetically by VR. */ @@ -283,12 +277,15 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->reset = cris_cpu_reset; cc->class_by_name = cris_cpu_class_by_name; + cc->has_work = cris_cpu_has_work; cc->do_interrupt = cris_cpu_do_interrupt; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; cc->gdb_write_register = cris_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = cris_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; #endif diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 1d7d80d..b88c147 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -171,8 +171,8 @@ typedef struct CPUCRISState { CPU_COMMON - /* Members after CPU_COMMON are preserved across resets. */ - void *load_info; + /* Members from load_info on are preserved across resets. */ + void *load_info; } CPUCRISState; #include "cpu-qom.h" @@ -247,9 +247,8 @@ static inline int cpu_mmu_index (CPUCRISState *env) return !!(env->pregs[PR_CCS] & U_FLAG); } -int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw, +int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 @@ -276,11 +275,6 @@ static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc, #define cpu_list cris_cpu_list void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf); -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); -} - #include "exec/exec-all.h" #endif diff --git a/target-cris/helper.c b/target-cris/helper.c index c940582..4092d27 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -41,7 +41,7 @@ void cris_cpu_do_interrupt(CPUState *cs) CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; - env->exception_index = -1; + cs->exception_index = -1; env->pregs[PR_ERP] = env->pc; } @@ -50,14 +50,14 @@ void crisv10_cpu_do_interrupt(CPUState *cs) cris_cpu_do_interrupt(cs); } -int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw, +int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - CRISCPU *cpu = cris_env_get_cpu(env); + CRISCPU *cpu = CRIS_CPU(cs); - env->exception_index = 0xaa; - env->pregs[PR_EDA] = address; - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); + cs->exception_index = 0xaa; + cpu->env.pregs[PR_EDA] = address; + cpu_dump_state(cs, stderr, fprintf, 0); return 1; } @@ -73,28 +73,30 @@ static void cris_shift_ccs(CPUCRISState *env) env->pregs[PR_CCS] = ccs; } -int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw, +int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - D(CPUState *cpu = CPU(cris_env_get_cpu(env))); + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; struct cris_mmu_result res; int prot, miss; int r = -1; target_ulong phy; - D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw)); + D(printf("%s addr=%" VADDR_PRIx " pc=%x rw=%x\n", + __func__, address, env->pc, rw)); miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, rw, mmu_idx, 0); if (miss) { - if (env->exception_index == EXCP_BUSFAULT) { - cpu_abort(env, + if (cs->exception_index == EXCP_BUSFAULT) { + cpu_abort(cs, "CRIS: Illegal recursive bus fault." - "addr=%x rw=%d\n", + "addr=%" VADDR_PRIx " rw=%d\n", address, rw); } env->pregs[PR_EDA] = address; - env->exception_index = EXCP_BUSFAULT; + cs->exception_index = EXCP_BUSFAULT; env->fault_vector = res.bf_vec; r = 1; } else { @@ -104,13 +106,13 @@ int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw, */ phy = res.phy & ~0x80000000; prot = res.prot; - tlb_set_page(env, address & TARGET_PAGE_MASK, phy, + tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } if (r > 0) { - D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n", - __func__, r, cpu->interrupt_request, address, res.phy, + D_LOG("%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" + " pc=%x\n", __func__, r, cs->interrupt_request, address, res.phy, res.bf_vec, env->pc); } return r; @@ -123,16 +125,16 @@ void crisv10_cpu_do_interrupt(CPUState *cs) int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", - env->exception_index, + cs->exception_index, cs->interrupt_request); if (env->dslot) { /* CRISv10 never takes interrupts while in a delay-slot. */ - cpu_abort(env, "CRIS: Interrupt on delay-slot\n"); + cpu_abort(cs, "CRIS: Interrupt on delay-slot\n"); } assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_BREAK: /* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */ @@ -148,7 +150,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) break; case EXCP_BUSFAULT: - cpu_abort(env, "Unhandled busfault"); + cpu_abort(cs, "Unhandled busfault"); break; default: @@ -185,10 +187,10 @@ void cris_cpu_do_interrupt(CPUState *cs) int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", - env->exception_index, + cs->exception_index, cs->interrupt_request); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_BREAK: /* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */ @@ -251,7 +253,7 @@ void cris_cpu_do_interrupt(CPUState *cs) /* Clear the excption_index to avoid spurios hw_aborts for recursive bus faults. */ - env->exception_index = -1; + cs->exception_index = -1; D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", __func__, env->pc, ex_vec, diff --git a/target-cris/mmu.c b/target-cris/mmu.c index 512e28b..1c95a41 100644 --- a/target-cris/mmu.c +++ b/target-cris/mmu.c @@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { + CRISCPU *cpu = cris_env_get_cpu(env); target_ulong vaddr; unsigned int idx; uint32_t lo, hi; @@ -315,7 +316,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) vaddr = tlb_vpn << TARGET_PAGE_BITS; D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr); - tlb_flush_page(env, vaddr); + tlb_flush_page(CPU(cpu), vaddr); } } } diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index b580513..bd9a583 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -54,23 +54,25 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; int ret; D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__, env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = cris_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - if (cpu_restore_state(env, retaddr)) { + if (cpu_restore_state(cs, retaddr)) { /* Evaluate flags after retranslation. */ helper_top_evaluate_flags(env); } } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -78,8 +80,10 @@ void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx, void helper_raise_exception(CPUCRISState *env, uint32_t index) { - env->exception_index = index; - cpu_loop_exit(env); + CPUState *cs = CPU(cris_env_get_cpu(env)); + + cs->exception_index = index; + cpu_loop_exit(cs); } void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) @@ -94,8 +98,11 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) void helper_spc_write(CPUCRISState *env, uint32_t new_spc) { #if !defined(CONFIG_USER_ONLY) - tlb_flush_page(env, env->pregs[PR_SPC]); - tlb_flush_page(env, new_spc); + CRISCPU *cpu = cris_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + tlb_flush_page(cs, env->pregs[PR_SPC]); + tlb_flush_page(cs, new_spc); #endif } @@ -110,6 +117,9 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2) void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) { +#if !defined(CONFIG_USER_ONLY) + CRISCPU *cpu = cris_env_get_cpu(env); +#endif uint32_t srs; srs = env->pregs[PR_SRS]; srs &= 3; @@ -151,7 +161,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", vaddr, tlb_v, env->pc); if (tlb_v) { - tlb_flush_page(env, vaddr); + tlb_flush_page(CPU(cpu), vaddr); } } } diff --git a/target-cris/translate.c b/target-cris/translate.c index f990d59..724f920 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -74,7 +74,7 @@ static TCGv env_pc; /* This is the state at translation time. */ typedef struct DisasContext { - CPUCRISState *env; + CRISCPU *cpu; target_ulong pc, ppc; /* Decoder. */ @@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int line) { printf("BUG: pc=%x %s %d\n", dc->pc, file, line); qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line); - cpu_abort(dc->env, "%s:%d\n", file, line); + cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line); } static const char *regnames[] = @@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, break; } default: - cpu_abort(dc->env, "Invalid fetch size %d\n", size); + cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size); break; } return r; @@ -1125,7 +1125,7 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) { - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ @@ -1139,7 +1139,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, unsigned int size, int sign) { - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ @@ -1154,7 +1154,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, static void gen_store (DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ @@ -3089,10 +3089,11 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) static void check_breakpoint(CPUCRISState *env, DisasContext *dc) { + CPUState *cs = CPU(cris_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc); @@ -3169,7 +3170,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, * delayslot, like in real hw. */ pc_start = tb->pc & ~1; - dc->env = env; + dc->cpu = cpu; dc->tb = tb; gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; @@ -3390,7 +3391,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, #if !DISAS_CRIS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { log_target_disas(env, pc_start, dc->pc - pc_start, - dc->env->pregs[PR_VR]); + env->pregs[PR_VR]); qemu_log("\nisize=%d osize=%td\n", dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf); } diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index d6ef084..2ad2b14 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -96,7 +96,7 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val, static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ @@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) default: LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled quickimm\n"); + cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n"); break; } return 2; @@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc) case 2: tmp = 1; break; case 1: tmp = 0; break; default: - cpu_abort(dc->env, "Unhandled BIAP"); + cpu_abort(CPU(dc->cpu), "Unhandled BIAP"); break; } @@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc) default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); break; } } else { @@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc) default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); break; } } @@ -1006,7 +1006,7 @@ static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size) if (!dc->postinc && (dc->ir & (1 << 11))) { int simm = dc->ir & 0xff; - /* cpu_abort(dc->env, "Unhandled opcode"); */ + /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */ /* sign extended. */ simm = (int8_t)simm; @@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) default: LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", dc->pc, size, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); break; } return insn_len; @@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) break; default: LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); break; } diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 722f11a..e9b3d57 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -38,7 +38,17 @@ OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU) /** + * X86CPUDefinition: + * + * CPU model definition data that was not converted to QOM per-subclass + * property defaults yet. + */ +typedef struct X86CPUDefinition X86CPUDefinition; + +/** * X86CPUClass: + * @cpu_def: CPU model definition + * @kvm_required: Whether CPU model requires KVM to be enabled. * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * @@ -49,6 +59,11 @@ typedef struct X86CPUClass { CPUClass parent_class; /*< public >*/ + /* Should be eventually replaced by subclass-specific property defaults. */ + X86CPUDefinition *cpu_def; + + bool kvm_required; + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } X86CPUClass; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 0e8812a..e7e62c5 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -315,7 +315,7 @@ typedef struct X86RegisterInfo32 { } X86RegisterInfo32; #define REGISTER(reg) \ - [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg } + [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { REGISTER(EAX), REGISTER(ECX), @@ -339,7 +339,7 @@ static const ExtSaveArea ext_save_areas[] = { [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, .offset = 0x3c0, .size = 0x40 }, [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, - .offset = 0x400, .size = 0x10 }, + .offset = 0x400, .size = 0x40 }, }; const char *get_register_name_32(unsigned int reg) @@ -358,17 +358,23 @@ typedef struct model_features_t { FeatureWord feat_word; } model_features_t; -static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) | +/* KVM-specific features that are automatically added to all CPU models + * when KVM is enabled. + */ +static uint32_t kvm_default_features[FEATURE_WORDS] = { + [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) | (1 << KVM_FEATURE_NOP_IO_DELAY) | (1 << KVM_FEATURE_CLOCKSOURCE2) | (1 << KVM_FEATURE_ASYNC_PF) | (1 << KVM_FEATURE_STEAL_TIME) | (1 << KVM_FEATURE_PV_EOI) | - (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); + (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT), + [FEAT_1_ECX] = CPUID_EXT_X2APIC, +}; -void disable_kvm_pv_eoi(void) +void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features) { - kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI); + kvm_default_features[w] &= ~features; } void host_cpuid(uint32_t function, uint32_t count, @@ -484,7 +490,35 @@ static void add_flagname_to_bitmaps(const char *flagname, } } -typedef struct x86_def_t { +/* CPU class name definitions: */ + +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) + +/* Return type name for a given CPU model name + * Caller is responsible for freeing the returned string. + */ +static char *x86_cpu_type_name(const char *model_name) +{ + return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); +} + +static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + + if (cpu_model == NULL) { + return NULL; + } + + typename = x86_cpu_type_name(cpu_model); + oc = object_class_by_name(typename); + g_free(typename); + return oc; +} + +struct X86CPUDefinition { const char *name; uint32_t level; uint32_t xlevel; @@ -497,7 +531,7 @@ typedef struct x86_def_t { FeatureWordArray features; char model_id[48]; bool cache_info_passthrough; -} x86_def_t; +}; #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ @@ -547,9 +581,7 @@ typedef struct x86_def_t { CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ -/* built-in CPU model definitions - */ -static x86_def_t builtin_x86_defs[] = { +static X86CPUDefinition builtin_x86_defs[] = { { .name = "qemu64", .level = 4, @@ -1108,7 +1140,7 @@ static x86_def_t builtin_x86_defs[] = { void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w, uint32_t feat_add, uint32_t feat_remove) { - x86_def_t *def; + X86CPUDefinition *def; int i; for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { def = &builtin_x86_defs[i]; @@ -1119,6 +1151,8 @@ void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w, } } +#ifdef CONFIG_KVM + static int cpu_x86_fill_model_id(char *str) { uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; @@ -1134,44 +1168,68 @@ static int cpu_x86_fill_model_id(char *str) return 0; } -/* Fill a x86_def_t struct with information about the host CPU, and - * the CPU features supported by the host hardware + host kernel +static X86CPUDefinition host_cpudef; + +/* class_init for the "host" CPU model * - * This function may be called only if KVM is enabled. + * This function may be called before KVM is initialized. */ -static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) +static void host_x86_cpu_class_init(ObjectClass *oc, void *data) { - KVMState *s = kvm_state; + X86CPUClass *xcc = X86_CPU_CLASS(oc); uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; - assert(kvm_enabled()); + xcc->kvm_required = true; - x86_cpu_def->name = "host"; - x86_cpu_def->cache_info_passthrough = true; host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx); + x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx); host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); - x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); - x86_cpu_def->stepping = eax & 0x0F; + host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); + host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); + host_cpudef.stepping = eax & 0x0F; - x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); - x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); - x86_cpu_def->xlevel2 = - kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); + cpu_x86_fill_model_id(host_cpudef.model_id); - cpu_x86_fill_model_id(x86_cpu_def->model_id); + xcc->cpu_def = &host_cpudef; + host_cpudef.cache_info_passthrough = true; + /* level, xlevel, xlevel2, and the feature words are initialized on + * instance_init, because they require KVM to be initialized. + */ +} + +static void host_x86_cpu_initfn(Object *obj) +{ + X86CPU *cpu = X86_CPU(obj); + CPUX86State *env = &cpu->env; + KVMState *s = kvm_state; FeatureWord w; + + assert(kvm_enabled()); + + env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); + env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); + env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); + for (w = 0; w < FEATURE_WORDS; w++) { FeatureWordInfo *wi = &feature_word_info[w]; - x86_cpu_def->features[w] = + env->features[w] = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx, wi->cpuid_reg); } + object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); } +static const TypeInfo host_x86_cpu_type_info = { + .name = X86_CPU_TYPE_NAME("host"), + .parent = TYPE_X86_CPU, + .instance_init = host_x86_cpu_initfn, + .class_init = host_x86_cpu_class_init, +}; + +#endif + static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask) { int i; @@ -1582,32 +1640,6 @@ static PropertyInfo qdev_prop_spinlocks = { .set = x86_set_hv_spinlocks, }; -static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def, - const char *name) -{ - x86_def_t *def; - int i; - - if (name == NULL) { - return -1; - } - if (kvm_enabled() && strcmp(name, "host") == 0) { - kvm_cpu_fill_host(x86_cpu_def); - object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); - return 0; - } - - for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { - def = &builtin_x86_defs[i]; - if (strcmp(name, def->name) == 0) { - memcpy(x86_cpu_def, def, sizeof(*def)); - return 0; - } - } - - return -1; -} - /* Convert all '_' in a feature string option name to '-', to make feature * name conform to QOM property naming rule, which uses '-' instead of '_'. */ @@ -1620,8 +1652,10 @@ static inline void feat2prop(char *s) /* Parse "+feature,-feature,feature=foo" CPU feature string */ -static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp) +static void x86_cpu_parse_featurestr(CPUState *cs, char *features, + Error **errp) { + X86CPU *cpu = X86_CPU(cs); char *featurestr; /* Single 'key=value" string being parsed */ /* Features to be added */ FeatureWordArray plus_features = { 0 }; @@ -1629,6 +1663,7 @@ static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp) FeatureWordArray minus_features = { 0 }; uint32_t numvalue; CPUX86State *env = &cpu->env; + Error *local_err = NULL; featurestr = features ? strtok(features, ",") : NULL; @@ -1647,16 +1682,16 @@ static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp) numvalue = strtoul(val, &err, 0); if (!*val || *err) { - error_setg(errp, "bad numerical value %s", val); + error_setg(&local_err, "bad numerical value %s", val); goto out; } if (numvalue < 0x80000000) { - fprintf(stderr, "xlevel value shall always be >= 0x80000000" - ", fixup will be removed in future versions\n"); + error_report("xlevel value shall always be >= 0x80000000" + ", fixup will be removed in future versions"); numvalue += 0x80000000; } snprintf(num, sizeof(num), "%" PRIu32, numvalue); - object_property_parse(OBJECT(cpu), num, featurestr, errp); + object_property_parse(OBJECT(cpu), num, featurestr, &local_err); } else if (!strcmp(featurestr, "tsc-freq")) { int64_t tsc_freq; char *err; @@ -1665,36 +1700,38 @@ static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp) tsc_freq = strtosz_suffix_unit(val, &err, STRTOSZ_DEFSUFFIX_B, 1000); if (tsc_freq < 0 || *err) { - error_setg(errp, "bad numerical value %s", val); + error_setg(&local_err, "bad numerical value %s", val); goto out; } snprintf(num, sizeof(num), "%" PRId64, tsc_freq); - object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp); + object_property_parse(OBJECT(cpu), num, "tsc-frequency", + &local_err); } else if (!strcmp(featurestr, "hv-spinlocks")) { char *err; const int min = 0xFFF; char num[32]; numvalue = strtoul(val, &err, 0); if (!*val || *err) { - error_setg(errp, "bad numerical value %s", val); + error_setg(&local_err, "bad numerical value %s", val); goto out; } if (numvalue < min) { - fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x" - ", fixup will be removed in future versions\n", + error_report("hv-spinlocks value shall always be >= 0x%x" + ", fixup will be removed in future versions", min); numvalue = min; } snprintf(num, sizeof(num), "%" PRId32, numvalue); - object_property_parse(OBJECT(cpu), num, featurestr, errp); + object_property_parse(OBJECT(cpu), num, featurestr, &local_err); } else { - object_property_parse(OBJECT(cpu), val, featurestr, errp); + object_property_parse(OBJECT(cpu), val, featurestr, &local_err); } } else { feat2prop(featurestr); - object_property_parse(OBJECT(cpu), "on", featurestr, errp); + object_property_parse(OBJECT(cpu), "on", featurestr, &local_err); } - if (error_is_set(errp)) { + if (local_err) { + error_propagate(errp, local_err); goto out; } featurestr = strtok(NULL, ","); @@ -1753,7 +1790,7 @@ static void listflags(char *buf, int bufsize, uint32_t fbits, /* generate CPU information. */ void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf) { - x86_def_t *def; + X86CPUDefinition *def; char buf[256]; int i; @@ -1780,7 +1817,7 @@ void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf) CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list = NULL; - x86_def_t *def; + X86CPUDefinition *def; int i; for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { @@ -1817,17 +1854,13 @@ static void filter_features_for_kvm(X86CPU *cpu) } } -static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp) +/* Load data from X86CPUDefinition + */ +static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp) { CPUX86State *env = &cpu->env; - x86_def_t def1, *def = &def1; - - memset(def, 0, sizeof(*def)); - - if (cpu_x86_find_by_name(cpu, def, name) < 0) { - error_setg(errp, "Unable to find CPU definition: %s", name); - return; - } + const char *vendor; + char host_vendor[CPUID_VENDOR_SZ + 1]; object_property_set_int(OBJECT(cpu), def->level, "level", errp); object_property_set_int(OBJECT(cpu), def->family, "family", errp); @@ -1847,10 +1880,14 @@ static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp) object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp); - /* Special cases not set in the x86_def_t structs: */ + /* Special cases not set in the X86CPUDefinition structs: */ if (kvm_enabled()) { - env->features[FEAT_KVM] |= kvm_default_features; + FeatureWord w; + for (w = 0; w < FEATURE_WORDS; w++) { + env->features[w] |= kvm_default_features[w]; + } } + env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; /* sysenter isn't supported in compatibility mode on AMD, @@ -1860,8 +1897,7 @@ static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp) * KVM's sysenter/syscall emulation in compatibility mode and * when doing cross vendor migration */ - const char *vendor = def->vendor; - char host_vendor[CPUID_VENDOR_SZ + 1]; + vendor = def->vendor; if (kvm_enabled()) { uint32_t ebx = 0, ecx = 0, edx = 0; host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); @@ -1877,9 +1913,10 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge, Error **errp) { X86CPU *cpu = NULL; + X86CPUClass *xcc; + ObjectClass *oc; gchar **model_pieces; char *name, *features; - char *typename; Error *error = NULL; model_pieces = g_strsplit(cpu_model, ",", 2); @@ -1890,30 +1927,30 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge, name = model_pieces[0]; features = model_pieces[1]; - cpu = X86_CPU(object_new(TYPE_X86_CPU)); -#ifndef CONFIG_USER_ONLY - if (icc_bridge == NULL) { - error_setg(&error, "Invalid icc-bridge value"); + oc = x86_cpu_class_by_name(name); + if (oc == NULL) { + error_setg(&error, "Unable to find CPU definition: %s", name); goto out; } - qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); - object_unref(OBJECT(cpu)); -#endif + xcc = X86_CPU_CLASS(oc); - cpu_x86_register(cpu, name, &error); - if (error) { + if (xcc->kvm_required && !kvm_enabled()) { + error_setg(&error, "CPU model '%s' requires KVM", name); goto out; } - /* Emulate per-model subclasses for global properties */ - typename = g_strdup_printf("%s-" TYPE_X86_CPU, name); - qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error); - g_free(typename); - if (error) { + cpu = X86_CPU(object_new(object_class_get_name(oc))); + +#ifndef CONFIG_USER_ONLY + if (icc_bridge == NULL) { + error_setg(&error, "Invalid icc-bridge value"); goto out; } + qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); + object_unref(OBJECT(cpu)); +#endif - cpu_x86_parse_featurestr(cpu, features, &error); + x86_cpu_parse_featurestr(CPU(cpu), features, &error); if (error) { goto out; } @@ -1921,8 +1958,10 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge, out: if (error != NULL) { error_propagate(errp, error); - object_unref(OBJECT(cpu)); - cpu = NULL; + if (cpu) { + object_unref(OBJECT(cpu)); + cpu = NULL; + } } g_strfreev(model_pieces); return cpu; @@ -1952,6 +1991,28 @@ out: return cpu; } +static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) +{ + X86CPUDefinition *cpudef = data; + X86CPUClass *xcc = X86_CPU_CLASS(oc); + + xcc->cpu_def = cpudef; +} + +static void x86_register_cpudef_type(X86CPUDefinition *def) +{ + char *typename = x86_cpu_type_name(def->name); + TypeInfo ti = { + .name = typename, + .parent = TYPE_X86_CPU, + .class_init = x86_cpu_cpudef_class_init, + .class_data = def, + }; + + type_register(&ti); + g_free(typename); +} + #if !defined(CONFIG_USER_ONLY) void cpu_clear_apic_feature(CPUX86State *env) @@ -1969,7 +2030,7 @@ void x86_cpudef_setup(void) static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" }; for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { - x86_def_t *def = &builtin_x86_defs[i]; + X86CPUDefinition *def = &builtin_x86_defs[i]; /* Look for specific "cpudef" models that */ /* have the QEMU version in .model_id */ @@ -2349,9 +2410,9 @@ static void x86_cpu_reset(CPUState *s) xcc->parent_reset(s); - memset(env, 0, offsetof(CPUX86State, breakpoints)); + memset(env, 0, offsetof(CPUX86State, pat)); - tlb_flush(env, 1); + tlb_flush(s, 1); env->old_exception = -1; @@ -2412,8 +2473,8 @@ static void x86_cpu_reset(CPUState *s) memset(env->dr, 0, sizeof(env->dr)); env->dr[6] = DR6_FIXED_1; env->dr[7] = DR7_FIXED_1; - cpu_breakpoint_remove_all(env, BP_CPU); - cpu_watchpoint_remove_all(env, BP_CPU); + cpu_breakpoint_remove_all(s, BP_CPU); + cpu_watchpoint_remove_all(s, BP_CPU); env->tsc_adjust = 0; env->tsc = 0; @@ -2613,6 +2674,7 @@ static void x86_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); X86CPU *cpu = X86_CPU(obj); + X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); CPUX86State *env = &cpu->env; static int inited; @@ -2656,6 +2718,8 @@ static void x86_cpu_initfn(Object *obj) cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY; env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index); + x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort); + /* init various static tables used in TCG mode */ if (tcg_enabled() && !inited) { inited = 1; @@ -2695,6 +2759,20 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.eip = tb->pc - tb->cs_base; } +static bool x86_cpu_has_work(CPUState *cs) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + return ((cs->interrupt_request & (CPU_INTERRUPT_HARD | + CPU_INTERRUPT_POLL)) && + (env->eflags & IF_MASK)) || + (cs->interrupt_request & (CPU_INTERRUPT_NMI | + CPU_INTERRUPT_INIT | + CPU_INTERRUPT_SIPI | + CPU_INTERRUPT_MCE)); +} + static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks }, @@ -2721,6 +2799,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->reset = x86_cpu_reset; cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; + cc->class_by_name = x86_cpu_class_by_name; + cc->parse_features = x86_cpu_parse_featurestr; + cc->has_work = x86_cpu_has_work; cc->do_interrupt = x86_cpu_do_interrupt; cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; @@ -2729,7 +2810,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = x86_cpu_gdb_write_register; cc->get_arch_id = x86_cpu_get_arch_id; cc->get_paging_enabled = x86_cpu_get_paging_enabled; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = x86_cpu_handle_mmu_fault; +#else cc->get_memory_mapping = x86_cpu_get_memory_mapping; cc->get_phys_page_debug = x86_cpu_get_phys_page_debug; cc->write_elf64_note = x86_cpu_write_elf64_note; @@ -2746,14 +2829,22 @@ static const TypeInfo x86_cpu_type_info = { .parent = TYPE_CPU, .instance_size = sizeof(X86CPU), .instance_init = x86_cpu_initfn, - .abstract = false, + .abstract = true, .class_size = sizeof(X86CPUClass), .class_init = x86_cpu_common_class_init, }; static void x86_cpu_register_types(void) { + int i; + type_register_static(&x86_cpu_type_info); + for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { + x86_register_cpudef_type(&builtin_x86_defs[i]); + } +#ifdef CONFIG_KVM + type_register_static(&host_x86_cpu_type_info); +#endif } type_init(x86_cpu_register_types) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 0014acc..4d1374c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -875,8 +875,8 @@ typedef struct CPUX86State { target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers */ union { - CPUBreakpoint *cpu_breakpoint[4]; - CPUWatchpoint *cpu_watchpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ uint32_t smbase; int old_exception; /* exception in flight */ @@ -887,6 +887,7 @@ typedef struct CPUX86State { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint64_t pat; /* processor features (e.g. for CPUID insn) */ @@ -1067,9 +1068,8 @@ void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); /* helper.c */ -int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, +int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int is_write, int mmu_idx); -#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault void x86_cpu_set_a20(X86CPU *cpu, int a20_state); static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index) @@ -1186,20 +1186,6 @@ void optimize_flags_init(void); #include "hw/i386/apic.h" #endif -static inline bool cpu_has_work(CPUState *cs) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - - return ((cs->interrupt_request & (CPU_INTERRUPT_HARD | - CPU_INTERRUPT_POLL)) && - (env->eflags & IF_MASK)) || - (cs->interrupt_request & (CPU_INTERRUPT_NMI | - CPU_INTERRUPT_INIT | - CPU_INTERRUPT_SIPI | - CPU_INTERRUPT_MCE)); -} - #include "exec/exec-all.h" static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, @@ -1276,11 +1262,11 @@ void do_smm_enter(X86CPU *cpu); void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); -void disable_kvm_pv_eoi(void); - void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w, uint32_t feat_add, uint32_t feat_remove); +void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features); + /* Return name of 32-bit register, from a R_* constant */ const char *get_register_name_32(unsigned int reg); diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c index 5319aef..f337fd2 100644 --- a/target-i386/excp_helper.c +++ b/target-i386/excp_helper.c @@ -94,6 +94,8 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, int is_int, int error_code, int next_eip_addend) { + CPUState *cs = CPU(x86_env_get_cpu(env)); + if (!is_int) { cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno, error_code); @@ -102,11 +104,11 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0); } - env->exception_index = intno; + cs->exception_index = intno; env->error_code = error_code; env->exception_is_int = is_int; env->exception_next_eip = env->eip + next_eip_addend; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* shortcuts to generate exceptions */ diff --git a/target-i386/helper.c b/target-i386/helper.c index 55c0457..4f447b8 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) a20_state = (a20_state != 0); if (a20_state != ((env->a20_mask >> 20) & 1)) { + CPUState *cs = CPU(cpu); + #if defined(DEBUG_MMU) printf("A20 update: a20=%d\n", a20_state); #endif /* if the cpu is currently executing code, we must unlink it and all the potentially executing TB */ - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); /* when a20 is changed, all the MMU mappings are invalid, so we must flush everything */ - tlb_flush(env, 1); + tlb_flush(cs, 1); env->a20_mask = ~(1 << 20) | (a20_state << 20); } } void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) { + X86CPU *cpu = x86_env_get_cpu(env); int pe_state; #if defined(DEBUG_MMU) @@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) #endif if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) != (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } #ifdef TARGET_X86_64 @@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) the PDPT */ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) { + X86CPU *cpu = x86_env_get_cpu(env); + env->cr[3] = new_cr3; if (env->cr[0] & CR0_PG_MASK) { #if defined(DEBUG_MMU) printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); #endif - tlb_flush(env, 0); + tlb_flush(CPU(cpu), 0); } } void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) { + X86CPU *cpu = x86_env_get_cpu(env); + #if defined(DEBUG_MMU) printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]); #endif if ((new_cr4 ^ env->cr[4]) & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK | CR4_SMEP_MASK | CR4_SMAP_MASK)) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } /* SSE handling */ if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) { @@ -485,15 +492,18 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) #if defined(CONFIG_USER_ONLY) -int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, +int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int is_write, int mmu_idx) { + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + /* user mode only emulation */ is_write &= 1; env->cr[2] = addr; env->error_code = (is_write << PG_ERROR_W_BIT); env->error_code |= PG_ERROR_U_MASK; - env->exception_index = EXCP0E_PAGE; + cs->exception_index = EXCP0E_PAGE; return 1; } @@ -508,14 +518,15 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, # endif /* return value: - -1 = cannot handle fault - 0 = nothing more to do - 1 = generate PF fault -*/ -int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, + * -1 = cannot handle fault + * 0 = nothing more to do + * 1 = generate PF fault + */ +int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int is_write1, int mmu_idx) { - CPUState *cs = ENV_GET_CPU(env); + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; uint64_t ptep, pte; target_ulong pde_addr, pte_addr; int error_code, is_dirty, prot, page_size, is_write, is_user; @@ -525,7 +536,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, is_user = mmu_idx == MMU_USER_IDX; #if defined(DEBUG_MMU) - printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n", + printf("MMU fault: addr=%" VADDR_PRIx " w=%d u=%d eip=" TARGET_FMT_lx "\n", addr, is_write1, is_user, env->eip); #endif is_write = is_write1 & 1; @@ -557,7 +568,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, sext = (int64_t)addr >> 47; if (sext != 0 && sext != -1) { env->error_code = 0; - env->exception_index = EXCP0D_GPF; + cs->exception_index = EXCP0D_GPF; return 1; } @@ -866,7 +877,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, paddr = (pte & TARGET_PAGE_MASK) + page_offset; vaddr = virt_addr + page_offset; - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; do_fault_protect: error_code = PG_ERROR_P_MASK; @@ -888,7 +899,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, env->cr[2] = addr; } env->error_code = error_code; - env->exception_index = EXCP0E_PAGE; + cs->exception_index = EXCP0E_PAGE; return 1; } @@ -989,12 +1000,13 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void hw_breakpoint_insert(CPUX86State *env, int index) { + CPUState *cs = CPU(x86_env_get_cpu(env)); int type = 0, err = 0; switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { - err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU, + err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU, &env->cpu_breakpoint[index]); } break; @@ -1010,7 +1022,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index) } if (type != 0) { - err = cpu_watchpoint_insert(env, env->dr[index], + err = cpu_watchpoint_insert(cs, env->dr[index], hw_breakpoint_len(env->dr[7], index), type, &env->cpu_watchpoint[index]); } @@ -1022,17 +1034,21 @@ void hw_breakpoint_insert(CPUX86State *env, int index) void hw_breakpoint_remove(CPUX86State *env, int index) { - if (!env->cpu_breakpoint[index]) + CPUState *cs; + + if (!env->cpu_breakpoint[index]) { return; + } + cs = CPU(x86_env_get_cpu(env)); switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { - cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]); + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]); } break; case DR7_TYPE_DATA_WR: case DR7_TYPE_DATA_RW: - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]); + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); break; case DR7_TYPE_IO_RW: /* No support for I/O watchpoints yet */ @@ -1084,19 +1100,20 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update) void breakpoint_handler(CPUX86State *env) { + CPUState *cs = CPU(x86_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_hw_breakpoints(env, false)) { raise_exception(env, EXCP01_DB); } else { - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->eip) { if (bp->flags & BP_CPU) { check_hw_breakpoints(env, true); @@ -1104,6 +1121,7 @@ void breakpoint_handler(CPUX86State *env) } break; } + } } } @@ -1250,13 +1268,14 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) { X86CPU *cpu = x86_env_get_cpu(env); + CPUState *cs = CPU(cpu); if (kvm_enabled()) { env->tpr_access_type = access; - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TPR); + cpu_interrupt(cs, CPU_INTERRUPT_TPR); } else { - cpu_restore_state(env, env->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); apic_handle_tpr_access_report(cpu->apic_state, env->eip, access); } diff --git a/target-i386/kvm.c b/target-i386/kvm.c index e555040..7a295f6 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -2277,13 +2277,13 @@ static int kvm_handle_debug(X86CPU *cpu, break; case 0x1: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_WRITE; break; case 0x3: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_ACCESS; break; @@ -2291,11 +2291,11 @@ static int kvm_handle_debug(X86CPU *cpu, } } } - } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) { + } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { ret = EXCP_DEBUG; } if (ret == 0) { - cpu_synchronize_state(CPU(cpu)); + cpu_synchronize_state(cs); assert(env->exception_injected == -1); /* pass to guest */ diff --git a/target-i386/machine.c b/target-i386/machine.c index d548c05..24bc373 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -290,6 +290,7 @@ static void cpu_pre_save(void *opaque) static int cpu_post_load(void *opaque, int version_id) { X86CPU *cpu = opaque; + CPUState *cs = CPU(cpu); CPUX86State *env = &cpu->env; int i; @@ -319,12 +320,12 @@ static int cpu_post_load(void *opaque, int version_id) env->fptags[i] = (env->fptag_vmstate >> i) & 1; } - cpu_breakpoint_remove_all(env, BP_CPU); - cpu_watchpoint_remove_all(env, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); for (i = 0; i < DR7_MAX_BP; i++) { hw_breakpoint_insert(env, i); } - tlb_flush(env, 1); + tlb_flush(cs, 1); return 0; } diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index 319a219..b3b811b 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -129,21 +129,25 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v) #if !defined(CONFIG_USER_ONLY) /* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - raise_exception_err(env, env->exception_index, env->error_code); + raise_exception_err(env, cs->exception_index, env->error_code); } } #endif diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 47f6a2f..1e2da1e 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -221,8 +221,10 @@ void helper_lmsw(CPUX86State *env, target_ulong t0) void helper_invlpg(CPUX86State *env, target_ulong addr) { + X86CPU *cpu = x86_env_get_cpu(env); + cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0); - tlb_flush_page(env, addr); + tlb_flush_page(CPU(cpu), addr); } void helper_rdtsc(CPUX86State *env) @@ -568,11 +570,11 @@ void helper_rdmsr(CPUX86State *env) static void do_pause(X86CPU *cpu) { - CPUX86State *env = &cpu->env; + CPUState *cs = CPU(cpu); /* Just let another CPU run. */ - env->exception_index = EXCP_INTERRUPT; - cpu_loop_exit(env); + cs->exception_index = EXCP_INTERRUPT; + cpu_loop_exit(cs); } static void do_hlt(X86CPU *cpu) @@ -582,8 +584,8 @@ static void do_hlt(X86CPU *cpu) env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ cs->halted = 1; - env->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); } void helper_hlt(CPUX86State *env, int next_eip_addend) @@ -638,6 +640,8 @@ void helper_pause(CPUX86State *env, int next_eip_addend) void helper_debug(CPUX86State *env) { - env->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); } diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 959212b..8c3f92c 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -95,6 +95,7 @@ static inline void load_seg_vm(CPUX86State *env, int seg, int selector) static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl) { + X86CPU *cpu = x86_env_get_cpu(env); int type, index, shift; #if 0 @@ -112,11 +113,11 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, #endif if (!(env->tr.flags & DESC_P_MASK)) { - cpu_abort(env, "invalid tss"); + cpu_abort(CPU(cpu), "invalid tss"); } type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; if ((type & 7) != 1) { - cpu_abort(env, "invalid tss type"); + cpu_abort(CPU(cpu), "invalid tss type"); } shift = type >> 3; index = (dpl * 4 + 2) << shift; @@ -782,6 +783,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) { + X86CPU *cpu = x86_env_get_cpu(env); int index; #if 0 @@ -790,7 +792,7 @@ static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) #endif if (!(env->tr.flags & DESC_P_MASK)) { - cpu_abort(env, "invalid tss"); + cpu_abort(CPU(cpu), "invalid tss"); } index = 8 * level + 4; if ((index + 7) > env->tr.limit) { @@ -935,9 +937,11 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int, #if defined(CONFIG_USER_ONLY) void helper_syscall(CPUX86State *env, int next_eip_addend) { - env->exception_index = EXCP_SYSCALL; + CPUState *cs = CPU(x86_env_get_cpu(env)); + + cs->exception_index = EXCP_SYSCALL; env->exception_next_eip = env->eip + next_eip_addend; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #else void helper_syscall(CPUX86State *env, int next_eip_addend) @@ -1131,7 +1135,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int, static void handle_even_inj(CPUX86State *env, int intno, int is_int, int error_code, int is_hw, int rm) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); @@ -1248,7 +1252,7 @@ void x86_cpu_do_interrupt(CPUState *cs) /* if user mode only, we simulate a fake exception which will be handled outside the cpu execution loop */ - do_interrupt_user(env, env->exception_index, + do_interrupt_user(env, cs->exception_index, env->exception_is_int, env->error_code, env->exception_next_eip); @@ -1258,7 +1262,7 @@ void x86_cpu_do_interrupt(CPUState *cs) /* simulate a real cpu exception. On i386, it can trigger new exceptions, but we do not handle double or triple faults yet. */ - do_interrupt_all(cpu, env->exception_index, + do_interrupt_all(cpu, cs->exception_index, env->exception_is_int, env->error_code, env->exception_next_eip, 0); diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 71c64b2..35901c9 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -181,8 +181,8 @@ void do_smm_enter(X86CPU *cpu) void helper_rsm(CPUX86State *env) { - CPUState *cs = ENV_GET_CPU(env); X86CPU *cpu = x86_env_get_cpu(env); + CPUState *cs = CPU(cpu); target_ulong sm_state; int i, offset; uint32_t val; diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index b38d450..aa17ecd 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -88,7 +88,8 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, static inline void svm_save_seg(CPUX86State *env, hwaddr addr, const SegmentCache *sc) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); + stw_phys(cs->as, addr + offsetof(struct vmcb_seg, selector), sc->selector); stq_phys(cs->as, addr + offsetof(struct vmcb_seg, base), @@ -102,7 +103,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr, static inline void svm_load_seg(CPUX86State *env, hwaddr addr, SegmentCache *sc) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); unsigned int flags; sc->selector = lduw_phys(cs->as, @@ -125,7 +126,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr, void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); target_ulong addr; uint32_t event_inj; uint32_t int_ctl; @@ -293,7 +294,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) break; case TLB_CONTROL_FLUSH_ALL_ASID: /* FIXME: this is not 100% correct but should work for now */ - tlb_flush(env, 1); + tlb_flush(cs, 1); break; } @@ -319,7 +320,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) /* FIXME: need to implement valid_err */ switch (event_inj & SVM_EVTINJ_TYPE_MASK) { case SVM_EVTINJ_TYPE_INTR: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; @@ -328,31 +329,31 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) do_interrupt_x86_hardirq(env, vector, 1); break; case SVM_EVTINJ_TYPE_NMI: - env->exception_index = EXCP02_NMI; + cs->exception_index = EXCP02_NMI; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_EXEPT: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_SOFT: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 1; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; } - qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index, + qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index, env->error_code); } } @@ -365,7 +366,7 @@ void helper_vmmcall(CPUX86State *env) void helper_vmload(CPUX86State *env, int aflag) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0); @@ -405,7 +406,7 @@ void helper_vmload(CPUX86State *env, int aflag) void helper_vmsave(CPUX86State *env, int aflag) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0); @@ -468,6 +469,7 @@ void helper_skinit(CPUX86State *env) void helper_invlpga(CPUX86State *env, int aflag) { + X86CPU *cpu = x86_env_get_cpu(env); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0); @@ -480,13 +482,13 @@ void helper_invlpga(CPUX86State *env, int aflag) /* XXX: could use the ASID to see if it is needed to do the flush */ - tlb_flush_page(env, addr); + tlb_flush_page(CPU(cpu), addr); } void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); if (likely(!(env->hflags & HF_SVMI_MASK))) { return; @@ -568,7 +570,8 @@ void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, uint32_t next_eip_addend) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(x86_env_get_cpu(env)); + if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) { /* FIXME: this should be read in at vmrun (faster this way?) */ uint64_t addr = ldq_phys(cs->as, env->vm_vmcb + @@ -766,11 +769,11 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) #GP fault is delivered inside the host. */ /* remove any pending exception */ - env->exception_index = -1; + cs->exception_index = -1; env->error_code = 0; env->old_exception = -1; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) diff --git a/target-i386/translate.c b/target-i386/translate.c index 707ebd5..02625e3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7965,8 +7965,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, gen_tb_start(); for(;;) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == pc_ptr && !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { gen_debug(dc, pc_ptr - dc->cs_base); diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 7e716fb..c5c20d7 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -110,6 +110,11 @@ static void lm32_cpu_init_cfg_reg(LM32CPU *cpu) env->cfg = cfg; } +static bool lm32_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + /* CPUClass::reset() */ static void lm32_cpu_reset(CPUState *s) { @@ -120,10 +125,10 @@ static void lm32_cpu_reset(CPUState *s) lcc->parent_reset(s); /* reset cpu state */ - memset(env, 0, offsetof(CPULM32State, breakpoints)); + memset(env, 0, offsetof(CPULM32State, eba)); lm32_cpu_init_cfg_reg(cpu); - tlb_flush(env, 1); + tlb_flush(s, 1); } static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) @@ -255,12 +260,15 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->reset = lm32_cpu_reset; cc->class_by_name = lm32_cpu_class_by_name; + cc->has_work = lm32_cpu_has_work; cc->do_interrupt = lm32_cpu_do_interrupt; cc->dump_state = lm32_cpu_dump_state; cc->set_pc = lm32_cpu_set_pc; cc->gdb_read_register = lm32_cpu_gdb_read_register; cc->gdb_write_register = lm32_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_lm32_cpu; #endif diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 18cf348..24bde78 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -166,11 +166,12 @@ struct CPULM32State { uint32_t bp[4]; /* breakpoints */ uint32_t wp[4]; /* watchpoints */ - CPUBreakpoint * cpu_breakpoint[4]; - CPUWatchpoint * cpu_watchpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ @@ -231,9 +232,8 @@ static inline CPULM32State *cpu_init(const char *cpu_model) #define cpu_gen_code cpu_lm32_gen_code #define cpu_signal_handler cpu_lm32_signal_handler -int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw, +int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault #include "exec/cpu-all.h" @@ -245,11 +245,6 @@ static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc, *flags = 0; } -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - #include "exec/exec-all.h" #endif diff --git a/target-lm32/helper.c b/target-lm32/helper.c index eecb9f6..783aa16 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -20,18 +20,20 @@ #include "cpu.h" #include "qemu/host-utils.h" -int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw, +int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; int prot; address &= TARGET_PAGE_MASK; prot = PAGE_BITS; if (env->flags & LM32_FLAG_IGNORE_MSB) { - tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx, + TARGET_PAGE_SIZE); } else { - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); } return 0; @@ -51,22 +53,28 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address) { - cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]); + LM32CPU *cpu = lm32_env_get_cpu(env); + + cpu_breakpoint_insert(CPU(cpu), address, BP_CPU, + &env->cpu_breakpoint[idx]); } void lm32_breakpoint_remove(CPULM32State *env, int idx) { + LM32CPU *cpu = lm32_env_get_cpu(env); + if (!env->cpu_breakpoint[idx]) { return; } - cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]); + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]); env->cpu_breakpoint[idx] = NULL; } void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, lm32_wp_t wp_type) { + LM32CPU *cpu = lm32_env_get_cpu(env); int flags = 0; switch (wp_type) { @@ -85,18 +93,20 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, } if (flags != 0) { - cpu_watchpoint_insert(env, address, 1, flags, + cpu_watchpoint_insert(CPU(cpu), address, 1, flags, &env->cpu_watchpoint[idx]); } } void lm32_watchpoint_remove(CPULM32State *env, int idx) { + LM32CPU *cpu = lm32_env_get_cpu(env); + if (!env->cpu_watchpoint[idx]) { return; } - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]); + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]); env->cpu_watchpoint[idx] = NULL; } @@ -116,19 +126,20 @@ static bool check_watchpoints(CPULM32State *env) void lm32_debug_excp_handler(CPULM32State *env) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_watchpoints(env)) { raise_exception(env, EXCP_WATCHPOINT); } else { - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->pc) { if (bp->flags & BP_CPU) { raise_exception(env, EXCP_BREAKPOINT); @@ -145,9 +156,9 @@ void lm32_cpu_do_interrupt(CPUState *cs) CPULM32State *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, - "exception at pc=%x type=%x\n", env->pc, env->exception_index); + "exception at pc=%x type=%x\n", env->pc, cs->exception_index); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_INSN_BUS_ERROR: case EXCP_DATA_BUS_ERROR: case EXCP_DIVIDE_BY_ZERO: @@ -158,9 +169,9 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->ie |= (env->ie & IE_IE) ? IE_EIE : 0; env->ie &= ~IE_IE; if (env->dc & DC_RE) { - env->pc = env->deba + (env->exception_index * 32); + env->pc = env->deba + (cs->exception_index * 32); } else { - env->pc = env->eba + (env->exception_index * 32); + env->pc = env->eba + (cs->exception_index * 32); } log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -170,30 +181,19 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->regs[R_BA] = env->pc; env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; env->ie &= ~IE_IE; - env->pc = env->deba + (env->exception_index * 32); + env->pc = env->deba + (cs->exception_index * 32); log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; default: - cpu_abort(env, "unhandled exception type=%d\n", - env->exception_index); + cpu_abort(cs, "unhandled exception type=%d\n", + cs->exception_index); break; } } LM32CPU *cpu_lm32_init(const char *cpu_model) { - LM32CPU *cpu; - ObjectClass *oc; - - oc = cpu_class_by_name(TYPE_LM32_CPU, cpu_model); - if (oc == NULL) { - return NULL; - } - cpu = LM32_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); } /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 7189cb5..2f36b7b 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -25,8 +25,10 @@ void raise_exception(CPULM32State *env, int index) { - env->exception_index = index; - cpu_loop_exit(env); + CPUState *cs = CPU(lm32_env_get_cpu(env)); + + cs->exception_index = index; + cpu_loop_exit(cs); } void HELPER(raise_exception)(CPULM32State *env, uint32_t index) @@ -39,8 +41,8 @@ void HELPER(hlt)(CPULM32State *env) CPUState *cs = CPU(lm32_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); } void HELPER(ill)(CPULM32State *env) @@ -148,20 +150,21 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) } /* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 80bffc7..c8abd1f 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1037,10 +1037,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPULM32State *env, DisasContext *dc) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); t_gen_raise_exception(dc, EXCP_DEBUG); diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 008d8db..c9cff19 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -30,6 +30,11 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +static bool m68k_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void m68k_set_feature(CPUM68KState *env, int feature) { env->features |= (1u << feature); @@ -44,7 +49,7 @@ static void m68k_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUM68KState, breakpoints)); + memset(env, 0, offsetof(CPUM68KState, features)); #if !defined(CONFIG_USER_ONLY) env->sr = 0x2700; #endif @@ -53,7 +58,7 @@ static void m68k_cpu_reset(CPUState *s) env->cc_op = CC_OP_FLAGS; /* TODO: We should set PC from the interrupt vector. */ env->pc = 0; - tlb_flush(env, 1); + tlb_flush(s, 1); } /* CPU models */ @@ -189,12 +194,15 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->reset = m68k_cpu_reset; cc->class_by_name = m68k_cpu_class_by_name; + cc->has_work = m68k_cpu_has_work; cc->do_interrupt = m68k_cpu_do_interrupt; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; cc->gdb_write_register = m68k_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_m68k_cpu; diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index cfd6846..6e4001d 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -110,6 +110,7 @@ typedef struct CPUM68KState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; @@ -237,9 +238,8 @@ static inline int cpu_mmu_index (CPUM68KState *env) return (env->sr & SR_S) == 0 ? 1 : 0; } -int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw, +int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault #include "exec/cpu-all.h" @@ -253,11 +253,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ } -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - #include "exec/exec-all.h" #endif diff --git a/target-m68k/helper.c b/target-m68k/helper.c index a364eb1..077b653 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -132,6 +132,7 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) { + M68kCPU *cpu = m68k_env_get_cpu(env); int flags; uint32_t src; uint32_t dest; @@ -204,7 +205,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) flags |= CCF_C; break; default: - cpu_abort(env, "Bad CC_OP %d", cc_op); + cpu_abort(CPU(cpu), "Bad CC_OP %d", cc_op); } env->cc_op = CC_OP_FLAGS; env->cc_dest = flags; @@ -212,6 +213,8 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val) { + M68kCPU *cpu = m68k_env_get_cpu(env); + switch (reg) { case 0x02: /* CACR */ env->cacr = val; @@ -225,7 +228,7 @@ void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val) break; /* TODO: Implement control registers. */ default: - cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n", + cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n", reg, val); } } @@ -277,11 +280,13 @@ void m68k_switch_sp(CPUM68KState *env) #if defined(CONFIG_USER_ONLY) -int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw, - int mmu_idx) +int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { - env->exception_index = EXCP_ACCESS; - env->mmu.ar = address; + M68kCPU *cpu = M68K_CPU(cs); + + cs->exception_index = EXCP_ACCESS; + cpu->env.mmu.ar = address; return 1; } @@ -295,14 +300,14 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return addr; } -int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw, - int mmu_idx) +int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { int prot; address &= TARGET_PAGE_MASK; prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 94c4983..9dffe8d 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -428,7 +428,8 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; /* Allocate the heap using sbrk. */ if (!ts->heap_limit) { abi_ulong ret; @@ -460,7 +461,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) #endif return; default: - cpu_abort(env, "Unsupported semihosting syscall %d\n", nr); + cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr); result = 0; } failed: diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index bbbfd7f..06302b1 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -23,10 +23,7 @@ void m68k_cpu_do_interrupt(CPUState *cs) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } void do_interrupt_m68k_hardirq(CPUM68KState *env) @@ -56,18 +53,18 @@ extern int semihosting_enabled; /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -87,7 +84,7 @@ static void do_rte(CPUM68KState *env) static void do_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs; + CPUState *cs = CPU(m68k_env_get_cpu(env)); uint32_t sp; uint32_t fmt; uint32_t retaddr; @@ -97,7 +94,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) retaddr = env->pc; if (!is_hw) { - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_RTE: /* Return from an exception. */ do_rte(env); @@ -112,20 +109,19 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) do_m68k_semihosting(env, env->dregs[0]); return; } - cs = CPU(m68k_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); return; } - if (env->exception_index >= EXCP_TRAP0 - && env->exception_index <= EXCP_TRAP15) { + if (cs->exception_index >= EXCP_TRAP0 + && cs->exception_index <= EXCP_TRAP15) { /* Move the PC after the trap instruction. */ retaddr += 2; } } - vector = env->exception_index << 2; + vector = cs->exception_index << 2; sp = env->aregs[7]; @@ -168,8 +164,10 @@ void do_interrupt_m68k_hardirq(CPUM68KState *env) static void raise_exception(CPUM68KState *env, int tt) { - env->exception_index = tt; - cpu_loop_exit(env); + CPUState *cs = CPU(m68k_env_get_cpu(env)); + + cs->exception_index = tt; + cpu_loop_exit(cs); } void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def index 4235b02..204663e 100644 --- a/target-m68k/qregs.def +++ b/target-m68k/qregs.def @@ -7,6 +7,5 @@ DEFO32(CC_SRC, cc_src) DEFO32(CC_X, cc_x) DEFO32(DIV1, div1) DEFO32(DIV2, div2) -DEFO32(EXCEPTION, exception_index) DEFO32(MACSR, macsr) DEFO32(MAC_MASK, mac_mask) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f54b94a..cd66289 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -43,6 +43,7 @@ #undef DEFF64 static TCGv_i32 cpu_halted; +static TCGv_i32 cpu_exception_index; static TCGv_ptr cpu_env; @@ -81,6 +82,10 @@ void m68k_tcg_init(void) cpu_halted = tcg_global_mem_new_i32(TCG_AREG0, -offsetof(M68kCPU, env) + offsetof(CPUState, halted), "HALTED"); + cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0, + -offsetof(M68kCPU, env) + + offsetof(CPUState, exception_index), + "EXCEPTION"); cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); @@ -110,14 +115,6 @@ void m68k_tcg_init(void) store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL"); } -static inline void qemu_assert(int cond, const char *msg) -{ - if (!cond) { - fprintf (stderr, "badness: %s\n", msg); - abort(); - } -} - /* internal defines */ typedef struct DisasContext { CPUM68KState *env; @@ -199,7 +196,7 @@ static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) tcg_gen_qemu_ld32u(tmp, addr, index); break; default: - qemu_assert(0, "bad load size"); + g_assert_not_reached(); } gen_throws_exception = gen_last_qop; return tmp; @@ -233,7 +230,7 @@ static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) tcg_gen_qemu_st32(val, addr, index); break; default: - qemu_assert(0, "bad store size"); + g_assert_not_reached(); } gen_throws_exception = gen_last_qop; } @@ -437,8 +434,7 @@ static inline int opsize_bytes(int opsize) case OS_SINGLE: return 4; case OS_DOUBLE: return 8; default: - qemu_assert(0, "bad operand size"); - return 0; + g_assert_not_reached(); } } @@ -465,8 +461,7 @@ static void gen_partset_reg(int opsize, TCGv reg, TCGv val) tcg_gen_mov_i32(reg, val); break; default: - qemu_assert(0, "Bad operand size"); - break; + g_assert_not_reached(); } } @@ -495,7 +490,7 @@ static inline TCGv gen_extend(TCGv val, int opsize, int sign) tmp = val; break; default: - qemu_assert(0, "Bad operand size"); + g_assert_not_reached(); } return tmp; } @@ -669,7 +664,7 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, offset = read_im32(env, s); break; default: - qemu_assert(0, "Bad immediate operand"); + g_assert_not_reached(); } return tcg_const_i32(offset); default: @@ -886,8 +881,10 @@ DISAS_INSN(undef_fpu) DISAS_INSN(undef) { + M68kCPU *cpu = m68k_env_get_cpu(env); + gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); - cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2); + cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); } DISAS_INSN(mulw) @@ -2087,12 +2084,14 @@ DISAS_INSN(wddata) DISAS_INSN(wdebug) { + M68kCPU *cpu = m68k_env_get_cpu(env); + if (IS_USER(s)) { gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); return; } /* TODO: Implement wdebug. */ - qemu_assert(0, "WDEBUG not implemented"); + cpu_abort(CPU(cpu), "WDEBUG not implemented"); } DISAS_INSN(trap) @@ -2466,14 +2465,18 @@ DISAS_INSN(fbcc) DISAS_INSN(frestore) { + M68kCPU *cpu = m68k_env_get_cpu(env); + /* TODO: Implement frestore. */ - qemu_assert(0, "FRESTORE not implemented"); + cpu_abort(CPU(cpu), "FRESTORE not implemented"); } DISAS_INSN(fsave) { + M68kCPU *cpu = m68k_env_get_cpu(env); + /* TODO: Implement fsave. */ - qemu_assert(0, "FSAVE not implemented"); + cpu_abort(CPU(cpu), "FSAVE not implemented"); } static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) @@ -3008,8 +3011,8 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, do { pc_offset = dc->pc - pc_start; gen_throws_exception = NULL; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception(dc, dc->pc, EXCP_DEBUG); dc->is_jmp = DISAS_JUMP; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index f108c0b..8e04811 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -34,6 +34,11 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.sregs[SR_PC] = value; } +static bool mb_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); +} + #ifndef CONFIG_USER_ONLY static void microblaze_cpu_set_irq(void *opaque, int irq, int level) { @@ -58,9 +63,9 @@ static void mb_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMBState, breakpoints)); + memset(env, 0, sizeof(CPUMBState)); env->res_addr = RES_ADDR_NONE; - tlb_flush(env, 1); + tlb_flush(s, 1); /* Disable stack protector. */ env->shr = ~0; @@ -160,12 +165,15 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) mcc->parent_reset = cc->reset; cc->reset = mb_cpu_reset; + cc->has_work = mb_cpu_has_work; cc->do_interrupt = mb_cpu_do_interrupt; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->gdb_read_register = mb_cpu_gdb_read_register; cc->gdb_write_register = mb_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; +#else cc->do_unassigned_access = mb_cpu_unassigned_access; cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; #endif diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 1df014e..6ccd060 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -332,9 +332,8 @@ static inline int cpu_mmu_index (CPUMBState *env) return MMU_KERNEL_IDX; } -int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw, +int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault static inline int cpu_interrupts_enabled(CPUMBState *env) { @@ -363,11 +362,6 @@ void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr, unsigned size); #endif -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); -} - #include "exec/exec-all.h" #endif diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 4fa9ce9..59c9ad5 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -31,26 +31,26 @@ void mb_cpu_do_interrupt(CPUState *cs) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; - env->exception_index = -1; + cs->exception_index = -1; env->res_addr = RES_ADDR_NONE; env->regs[14] = env->sregs[SR_PC]; } -int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw, +int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - MicroBlazeCPU *cpu = mb_env_get_cpu(env); - - env->exception_index = 0xaa; - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); + cs->exception_index = 0xaa; + cpu_dump_state(cs, stderr, fprintf, 0); return 1; } #else /* !CONFIG_USER_ONLY */ -int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw, - int mmu_idx) +int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; unsigned int hit; unsigned int mmu_available; int r = 1; @@ -77,7 +77,7 @@ int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw, DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n", mmu_idx, vaddr, paddr, lu.prot)); - tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } else { env->sregs[SR_EAR] = address; @@ -97,18 +97,18 @@ int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw, break; } - if (env->exception_index == EXCP_MMU) { - cpu_abort(env, "recursive faults\n"); + if (cs->exception_index == EXCP_MMU) { + cpu_abort(cs, "recursive faults\n"); } /* TLB miss. */ - env->exception_index = EXCP_MMU; + cs->exception_index = EXCP_MMU; } } else { /* MMU disabled or not available. */ address &= TARGET_PAGE_MASK; prot = PAGE_BITS; - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } return r; @@ -125,7 +125,7 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_HW_EXCP: if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { qemu_log("Exception raised on system without exceptions!\n"); @@ -251,7 +251,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; - if (env->exception_index == EXCP_HW_BREAK) { + if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; env->sregs[SR_PC] = cpu->base_vectors + 0x18; @@ -259,8 +259,8 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC] = env->btarget; break; default: - cpu_abort(env, "unhandled exception type=%d\n", - env->exception_index); + cpu_abort(cs, "unhandled exception type=%d\n", + cs->exception_index); break; } } diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c index 73bf805..728da13 100644 --- a/target-microblaze/mmu.c +++ b/target-microblaze/mmu.c @@ -34,6 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f) static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { + CPUState *cs = CPU(mb_env_get_cpu(env)); struct microblaze_mmu *mmu = &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; @@ -47,7 +48,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx) end = tlb_tag + tlb_size; while (tlb_tag < end) { - tlb_flush_page(env, tlb_tag); + tlb_flush_page(cs, tlb_tag); tlb_tag += TARGET_PAGE_SIZE; } } @@ -218,6 +219,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) { + MicroBlazeCPU *cpu = mb_env_get_cpu(env); unsigned int i; D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn])); @@ -251,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) /* Changes to the zone protection reg flush the QEMU TLB. Fortunately, these are very uncommon. */ if (v != env->mmu.regs[rn]) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } env->mmu.regs[rn] = v; break; diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index 14baa84..f8fb7f9 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -39,20 +39,21 @@ #include "exec/softmmu_template.h" /* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif @@ -94,8 +95,10 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl) void helper_raise_exception(CPUMBState *env, uint32_t index) { - env->exception_index = index; - cpu_loop_exit(env); + CPUState *cs = CPU(mb_env_get_cpu(env)); + + cs->exception_index = index; + cpu_loop_exit(cs); } void helper_debug(CPUMBState *env) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 270138c..782a489 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -56,7 +56,7 @@ static TCGv env_res_val; /* This is the state at translation time. */ typedef struct DisasContext { - CPUMBState *env; + MicroBlazeCPU *cpu; target_ulong pc; /* Decoder. */ @@ -327,8 +327,8 @@ static void dec_pattern(DisasContext *dc) int l1; if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) + && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } @@ -370,7 +370,7 @@ static void dec_pattern(DisasContext *dc) } break; default: - cpu_abort(dc->env, + cpu_abort(CPU(dc->cpu), "unsupported pattern insn opcode=%x\n", dc->opcode); break; } @@ -441,9 +441,10 @@ static inline void msr_write(DisasContext *dc, TCGv v) static void dec_msr(DisasContext *dc) { + CPUState *cs = CPU(dc->cpu); TCGv t0, t1; unsigned int sr, to, rn; - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); sr = dc->imm & ((1 << 14) - 1); to = dc->imm & (1 << 14); @@ -458,7 +459,7 @@ static void dec_msr(DisasContext *dc) LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", dc->rd, dc->imm); - if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) { + if (!(dc->cpu->env.pvr.regs[2] & PVR2_USE_MSR_INSTR)) { /* nop??? */ return; } @@ -537,7 +538,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr)); break; default: - cpu_abort(dc->env, "unknown mts reg %x\n", sr); + cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); break; } } else { @@ -586,7 +587,7 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, pvr.regs[rn])); break; default: - cpu_abort(dc->env, "unknown mfs reg %x\n", sr); + cpu_abort(cs, "unknown mfs reg %x\n", sr); break; } } @@ -643,8 +644,8 @@ static void dec_mul(DisasContext *dc) unsigned int subcode; if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) + && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -662,7 +663,7 @@ static void dec_mul(DisasContext *dc) /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ if (subcode >= 1 && subcode <= 3 - && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) { + && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_MUL64_MASK))) { /* nop??? */ } @@ -684,7 +685,7 @@ static void dec_mul(DisasContext *dc) t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: - cpu_abort(dc->env, "unknown MUL insn %x\n", subcode); + cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); break; } done: @@ -700,8 +701,8 @@ static void dec_div(DisasContext *dc) u = dc->imm & 2; LOG_DIS("div\n"); - if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) { + if ((dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) + && !((dc->cpu->env.pvr.regs[0] & PVR0_USE_DIV_MASK))) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } @@ -722,8 +723,8 @@ static void dec_barrel(DisasContext *dc) unsigned int s, t; if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) + && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_BARREL_MASK)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -752,9 +753,10 @@ static void dec_barrel(DisasContext *dc) static void dec_bit(DisasContext *dc) { + CPUState *cs = CPU(dc->cpu); TCGv t0; unsigned int op; - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); op = dc->ir & ((1 << 9) - 1); switch (op) { @@ -819,12 +821,12 @@ static void dec_bit(DisasContext *dc) break; case 0xe0: if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) + && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } - if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) { + if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) { gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]); } break; @@ -839,8 +841,8 @@ static void dec_bit(DisasContext *dc) tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); break; default: - cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - dc->pc, op, dc->rd, dc->ra, dc->rb); + cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", + dc->pc, op, dc->rd, dc->ra, dc->rb); break; } } @@ -933,7 +935,7 @@ static void dec_load(DisasContext *dc) } if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -991,7 +993,7 @@ static void dec_load(DisasContext *dc) } break; default: - cpu_abort(dc->env, "Invalid reverse size\n"); + cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); break; } } @@ -1018,9 +1020,9 @@ static void dec_load(DisasContext *dc) * address and if that succeeds we write into the destination reg. */ v = tcg_temp_new(); - tcg_gen_qemu_ld_tl(v, *addr, cpu_mmu_index(dc->env), mop); + tcg_gen_qemu_ld_tl(v, *addr, cpu_mmu_index(&dc->cpu->env), mop); - if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd), tcg_const_tl(0), tcg_const_tl(size - 1)); @@ -1063,7 +1065,7 @@ static void dec_store(DisasContext *dc) } if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -1096,7 +1098,8 @@ static void dec_store(DisasContext *dc) this compare and the following write to be atomic. For user emulation we need to add atomicity between threads. */ tval = tcg_temp_new(); - tcg_gen_qemu_ld_tl(tval, swx_addr, cpu_mmu_index(dc->env), MO_TEUL); + tcg_gen_qemu_ld_tl(tval, swx_addr, cpu_mmu_index(&dc->cpu->env), + MO_TEUL); tcg_gen_brcond_tl(TCG_COND_NE, env_res_val, tval, swx_skip); write_carryi(dc, 0); tcg_temp_free(tval); @@ -1142,14 +1145,14 @@ static void dec_store(DisasContext *dc) } break; default: - cpu_abort(dc->env, "Invalid reverse size\n"); + cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); break; } } - tcg_gen_qemu_st_tl(cpu_R[dc->rd], *addr, cpu_mmu_index(dc->env), mop); + tcg_gen_qemu_st_tl(cpu_R[dc->rd], *addr, cpu_mmu_index(&dc->cpu->env), mop); /* Verify alignment if needed. */ - if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe @@ -1193,7 +1196,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, tcg_gen_setcond_tl(TCG_COND_GT, d, a, b); break; default: - cpu_abort(dc->env, "Unknown condition code %x.\n", cc); + cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); break; } } @@ -1244,7 +1247,7 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); @@ -1376,7 +1379,7 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); i_bit = dc->ir & (1 << 21); b_bit = dc->ir & (1 << 22); @@ -1423,7 +1426,7 @@ static int dec_check_fpuv2(DisasContext *dc) { int r; - r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK; + r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; if (!r && (dc->tb_flags & MSR_EE_FLAG)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); @@ -1437,8 +1440,8 @@ static void dec_fpu(DisasContext *dc) unsigned int fpu_insn; if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) + && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -1540,7 +1543,7 @@ static void dec_fpu(DisasContext *dc) static void dec_null(DisasContext *dc) { if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -1552,7 +1555,7 @@ static void dec_null(DisasContext *dc) /* Insns connected to FSL or AXI stream attached devices. */ static void dec_stream(DisasContext *dc) { - int mem_index = cpu_mmu_index(dc->env); + int mem_index = cpu_mmu_index(&dc->cpu->env); TCGv_i32 t_id, t_ctrl; int ctrl; @@ -1628,8 +1631,8 @@ static inline void decode(DisasContext *dc, uint32_t ir) dc->nr_nops = 0; else { if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) { + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) + && (dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -1637,8 +1640,9 @@ static inline void decode(DisasContext *dc, uint32_t ir) LOG_DIS("nr_nops=%d\t", dc->nr_nops); dc->nr_nops++; - if (dc->nr_nops > 4) - cpu_abort(dc->env, "fetching nop sequence\n"); + if (dc->nr_nops > 4) { + cpu_abort(CPU(dc->cpu), "fetching nop sequence\n"); + } } /* bit 2 seems to indicate insn type. */ dc->type_b = ir & (1 << 29); @@ -1660,10 +1664,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPUMBState *env, DisasContext *dc) { + CPUState *cs = CPU(mb_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp = DISAS_UPDATE; @@ -1690,7 +1695,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, int max_insns; pc_start = tb->pc; - dc->env = env; + dc->cpu = cpu; dc->tb = tb; org_flags = dc->synced_flags = dc->tb_flags = tb->flags; @@ -1708,8 +1713,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, dc->abort_at_next_insn = 0; dc->nr_nops = 0; - if (pc_start & 3) - cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start); + if (pc_start & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); + } if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { #if !SIM_COMPAT diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 9dd47e8..ae37ae2 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -45,6 +45,35 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } +static bool mips_cpu_has_work(CPUState *cs) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + bool has_work = false; + + /* It is implementation dependent if non-enabled interrupts + wake-up the CPU, however most of the implementations only + check for interrupts that can be taken. */ + if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_mips_hw_interrupts_pending(env)) { + has_work = true; + } + + /* MIPS-MT has the ability to halt the CPU. */ + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + /* The QEMU model will issue an _WAKE request whenever the CPUs + should be woken up. */ + if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + has_work = true; + } + + if (!mips_vpe_active(env)) { + has_work = false; + } + } + return has_work; +} + /* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { @@ -54,8 +83,8 @@ static void mips_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMIPSState, breakpoints)); - tlb_flush(env, 1); + memset(env, 0, offsetof(CPUMIPSState, mvp)); + tlb_flush(s, 1); cpu_state_reset(env); } @@ -97,13 +126,16 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) mcc->parent_reset = cc->reset; cc->reset = mips_cpu_reset; + cc->has_work = mips_cpu_has_work; cc->do_interrupt = mips_cpu_do_interrupt; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; cc->gdb_read_register = mips_cpu_gdb_read_register; cc->gdb_write_register = mips_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = mips_cpu_handle_mmu_fault; +#else cc->do_unassigned_access = mips_cpu_unassigned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; #endif diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 60c8061..3ba3229 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -482,6 +482,7 @@ struct CPUMIPSState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; @@ -666,9 +667,8 @@ void cpu_mips_stop_count(CPUMIPSState *env); void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); /* helper.c */ -int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, - int mmu_idx); -#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault +int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, @@ -715,34 +715,6 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } -static inline bool cpu_has_work(CPUState *cpu) -{ - CPUMIPSState *env = &MIPS_CPU(cpu)->env; - bool has_work = false; - - /* It is implementation dependent if non-enabled interrupts - wake-up the CPU, however most of the implementations only - check for interrupts that can be taken. */ - if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_mips_hw_interrupts_pending(env)) { - has_work = true; - } - - /* MIPS-MT has the ability to halt the CPU. */ - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - /* The QEMU model will issue an _WAKE request whenever the CPUs - should be woken up. */ - if (cpu->interrupt_request & CPU_INTERRUPT_WAKE) { - has_work = true; - } - - if (!mips_vpe_active(env)) { - has_work = false; - } - } - return has_work; -} - #include "exec/exec-all.h" static inline void compute_hflags(CPUMIPSState *env) diff --git a/target-mips/helper.c b/target-mips/helper.c index 33e0e88..b28ae9b 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -204,6 +204,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) { + CPUState *cs = CPU(mips_env_get_cpu(env)); int exception = 0, error_code = 0; switch (tlb_error) { @@ -249,7 +250,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); #endif - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; } @@ -268,9 +269,11 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } #endif -int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, - int mmu_idx) +int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; #if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; @@ -279,9 +282,9 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, int ret = 0; #if 0 - log_cpu_state(CPU(mips_env_get_cpu(env)), 0); + log_cpu_state(cs, 0); #endif - qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n", + qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, env->active_tc.PC, address, rw, mmu_idx); rw &= 1; @@ -293,10 +296,11 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, address, rw, access_type); - qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", - __func__, address, ret, physical, prot); + qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx + " prot %d\n", + __func__, address, ret, physical, prot); if (ret == TLBRET_MATCH) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); ret = 0; @@ -401,27 +405,29 @@ static void set_hflags_for_handler (CPUMIPSState *env) void mips_cpu_do_interrupt(CPUState *cs) { +#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) target_ulong offset; int cause = -1; const char *name; - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { - if (env->exception_index < 0 || env->exception_index > EXCP_LAST) + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { + if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { name = "unknown"; - else - name = excp_names[env->exception_index]; + } else { + name = excp_names[cs->exception_index]; + } qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", __func__, env->active_tc.PC, env->CP0_EPC, name); } - if (env->exception_index == EXCP_EXT_INTERRUPT && - (env->hflags & MIPS_HFLAG_DM)) - env->exception_index = EXCP_DINT; + if (cs->exception_index == EXCP_EXT_INTERRUPT && + (env->hflags & MIPS_HFLAG_DM)) { + cs->exception_index = EXCP_DINT; + } offset = 0x180; - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_DSS: env->CP0_Debug |= 1 << CP0DB_DSS; /* Debug single step cannot be raised inside a delay slot and @@ -629,11 +635,11 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); break; default: - qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); - printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); + qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index); + printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index); exit(1); } - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", __func__, env->active_tc.PC, env->CP0_EPC, cause, @@ -641,12 +647,14 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_DEPC); } #endif - env->exception_index = EXCP_NONE; + cs->exception_index = EXCP_NONE; } #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { + MIPSCPU *cpu = mips_env_get_cpu(env); + CPUState *cs; r4k_tlb_t *tlb; target_ulong addr; target_ulong end; @@ -672,6 +680,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) /* 1k pages are not supported. */ mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); if (tlb->V0) { + cs = CPU(cpu); addr = tlb->VPN & ~mask; #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -680,11 +689,12 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) #endif end = addr | (mask >> 1); while (addr < end) { - tlb_flush_page (env, addr); + tlb_flush_page(cs, addr); addr += TARGET_PAGE_SIZE; } } if (tlb->V1) { + cs = CPU(cpu); addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -693,7 +703,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) #endif end = addr | mask; while (addr - 1 < end) { - tlb_flush_page (env, addr); + tlb_flush_page(cs, addr); addr += TARGET_PAGE_SIZE; } } diff --git a/target-mips/machine.c b/target-mips/machine.c index 23504ba..0a07db8 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUMIPSState *env = opaque; + MIPSCPU *cpu = mips_env_get_cpu(env); int i; if (version_id != 3) @@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) load_fpu(f, &env->fpus[i]); /* XXX: ensure compatibility for halted bit ? */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return 0; } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 2ef6633..e56f038 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -38,18 +38,20 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, int error_code, uintptr_t pc) { + CPUState *cs = CPU(mips_env_get_cpu(env)); + if (exception < EXCP_SC) { qemu_log("%s: %d %d\n", __func__, exception, error_code); } - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; if (pc) { /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cs, pc); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, @@ -278,7 +280,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env, lladdr = cpu_mips_translate_address(env, address, rw); if (lladdr == -1LL) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(mips_env_get_cpu(env))); } else { return lladdr; } @@ -1342,6 +1344,7 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { + MIPSCPU *cpu = mips_env_get_cpu(env); uint32_t val, old; uint32_t mask = env->CP0_Status_rw_bitmask; @@ -1363,7 +1366,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } @@ -1782,8 +1787,10 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) /* TLB management */ static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) { + MIPSCPU *cpu = mips_env_get_cpu(env); + /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush (env, flush_global); + tlb_flush(CPU(cpu), flush_global); env->tlb->tlb_in_use = env->tlb->nb_tlb; } @@ -1983,6 +1990,8 @@ static void debug_pre_eret(CPUMIPSState *env) static void debug_post_eret(CPUMIPSState *env) { + MIPSCPU *cpu = mips_env_get_cpu(env); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -1994,7 +2003,9 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } @@ -2143,14 +2154,17 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr); } -void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - do_raise_exception_err(env, env->exception_index, + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); } } diff --git a/target-mips/translate.c b/target-mips/translate.c index 083f6ab..71dccae 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15613,8 +15613,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); gen_tb_start(); while (ctx.bstate == BS_NONE) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; @@ -15929,10 +15929,8 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) void cpu_state_reset(CPUMIPSState *env) { -#ifndef CONFIG_USER_ONLY MIPSCPU *cpu = mips_env_get_cpu(env); CPUState *cs = CPU(cpu); -#endif /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; @@ -16063,7 +16061,7 @@ void cpu_state_reset(CPUMIPSState *env) } #endif compute_hflags(env); - env->exception_index = EXCP_NONE; + cs->exception_index = EXCP_NONE; } void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 29d39e2..a64fd2b 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -629,6 +629,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { + MIPSCPU *cpu = mips_env_get_cpu(env); + env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); switch (def->mmu_type) { @@ -645,7 +647,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(env, "MMU type not supported\n"); + cpu_abort(CPU(cpu), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 484ecc2..47b617f 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -29,6 +29,11 @@ static void moxie_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +static bool moxie_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void moxie_cpu_reset(CPUState *s) { MoxieCPU *cpu = MOXIE_CPU(s); @@ -37,10 +42,10 @@ static void moxie_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMoxieState, breakpoints)); + memset(env, 0, sizeof(CPUMoxieState)); env->pc = 0x1000; - tlb_flush(env, 1); + tlb_flush(s, 1); } static void moxie_cpu_realizefn(DeviceState *dev, Error **errp) @@ -99,10 +104,13 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = moxie_cpu_class_by_name; + cc->has_work = moxie_cpu_has_work; cc->do_interrupt = moxie_cpu_do_interrupt; cc->dump_state = moxie_cpu_dump_state; cc->set_pc = moxie_cpu_set_pc; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = moxie_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug; cc->vmsd = &vmstate_moxie_cpu; #endif @@ -130,18 +138,7 @@ static const MoxieCPUInfo moxie_cpus[] = { MoxieCPU *cpu_moxie_init(const char *cpu_model) { - MoxieCPU *cpu; - ObjectClass *oc; - - oc = moxie_cpu_class_by_name(cpu_model); - if (oc == NULL) { - return NULL; - } - cpu = MOXIE_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model)); } static void cpu_register(const MoxieCPUInfo *info) diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h index 5ce14b5..c5b12a5 100644 --- a/target-moxie/cpu.h +++ b/target-moxie/cpu.h @@ -152,12 +152,7 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc, *flags = 0; } -static inline int cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - -int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, +int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); #endif /* _CPU_MOXIE_H */ diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 7859102..3d0c34d 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -46,31 +46,33 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_moxie_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_exception(CPUMoxieState *env, int ex) { - env->exception_index = ex; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = ex; /* Stash the exception type. */ env->sregs[2] = ex; /* Stash the address where the exception occurred. */ - cpu_restore_state(env, GETPC()); + cpu_restore_state(cs, GETPC()); env->sregs[5] = env->pc; /* Jump the the exception handline routine. */ env->pc = env->sregs[1]; - cpu_loop_exit(env); + cpu_loop_exit(cs); } uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b) @@ -97,33 +99,39 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b) void helper_debug(CPUMoxieState *env) { - env->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); } #if defined(CONFIG_USER_ONLY) -void moxie_cpu_do_interrupt(CPUState *env) +void moxie_cpu_do_interrupt(CPUState *cs) { - env->exception_index = -1; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = -1; } -int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, +int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - MoxieCPU *cpu = moxie_env_get_cpu(env); + MoxieCPU *cpu = MOXIE_CPU(cs); - env->exception_index = 0xaa; - env->debug1 = address; - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); + cs->exception_index = 0xaa; + cpu->env.debug1 = address; + cpu_dump_state(cs, stderr, fprintf, 0); return 1; } #else /* !CONFIG_USER_ONLY */ -int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, +int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { + MoxieCPU *cpu = MOXIE_CPU(cs); + CPUMoxieState *env = &cpu->env; MoxieMMUResult res; int prot, miss; target_ulong phy; @@ -135,22 +143,19 @@ int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, if (miss) { /* handle the miss. */ phy = 0; - env->exception_index = MOXIE_EX_MMU_MISS; + cs->exception_index = MOXIE_EX_MMU_MISS; } else { phy = res.phy; r = 0; } - tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); return r; } void moxie_cpu_do_interrupt(CPUState *cs) { - MoxieCPU *cpu = MOXIE_CPU(cs); - CPUMoxieState *env = &cpu->env; - - switch (env->exception_index) { + switch (cs->exception_index) { case MOXIE_EX_BREAK: break; default: diff --git a/target-moxie/translate.c b/target-moxie/translate.c index a93196f..63f889f 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -845,8 +845,8 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 8137943..08e724c 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -27,6 +27,12 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +static bool openrisc_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & (CPU_INTERRUPT_HARD | + CPU_INTERRUPT_TIMER); +} + /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) { @@ -35,14 +41,18 @@ static void openrisc_cpu_reset(CPUState *s) occ->parent_reset(s); - memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); +#ifndef CONFIG_USER_ONLY + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb)); +#else + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq)); +#endif - tlb_flush(&cpu->env, 1); + tlb_flush(s, 1); /*tb_flush(&cpu->env); FIXME: Do we need it? */ cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; - cpu->env.exception_index = -1; + s->exception_index = -1; cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; @@ -153,12 +163,15 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->reset = openrisc_cpu_reset; cc->class_by_name = openrisc_cpu_class_by_name; + cc->has_work = openrisc_cpu_has_work; cc->do_interrupt = openrisc_cpu_do_interrupt; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; cc->gdb_write_register = openrisc_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; #endif @@ -201,18 +214,7 @@ static void openrisc_cpu_register_types(void) OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) { - OpenRISCCPU *cpu; - ObjectClass *oc; - - oc = openrisc_cpu_class_by_name(cpu_model); - if (oc == NULL) { - return NULL; - } - cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); } /* Sort alphabetically by type name, except for "any". */ diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 51d6afd..4512f45 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -304,6 +304,7 @@ typedef struct CPUOpenRISCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; @@ -353,15 +354,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, - target_ulong address, +int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_list cpu_openrisc_list #define cpu_exec cpu_openrisc_exec #define cpu_gen_code cpu_openrisc_gen_code -#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault #define cpu_signal_handler cpu_openrisc_signal_handler #ifndef CONFIG_USER_ONLY @@ -419,11 +418,6 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env) } #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | - CPU_INTERRUPT_TIMER); -} #include "exec/exec-all.h" diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c index 58e53c6..74652a5 100644 --- a/target-openrisc/exception.c +++ b/target-openrisc/exception.c @@ -22,6 +22,8 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) { - cpu->env.exception_index = excp; - cpu_loop_exit(&cpu->env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; + cpu_loop_exit(cs); } diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 2153e7e..3de567e 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -27,9 +27,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) { +#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY env->epcr = env->pc; if (env->flags & D_FLAG) { @@ -37,13 +37,13 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |= SR_DSX; env->epcr -= 4; } - if (env->exception_index == EXCP_SYSCALL) { + if (cs->exception_index == EXCP_SYSCALL) { env->epcr += 4; } /* For machine-state changed between user-mode and supervisor mode, we need flush TLB when we enter&exit EXCP. */ - tlb_flush(env, 1); + tlb_flush(cs, 1); env->esr = env->sr; env->sr &= ~SR_DME; @@ -54,12 +54,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - if (env->exception_index > 0 && env->exception_index < EXCP_NR) { - env->pc = (env->exception_index << 8); + if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { + env->pc = (cs->exception_index << 8); } else { - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } #endif - env->exception_index = -1; + cs->exception_index = -1; } diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c index 844648f..8194057 100644 --- a/target-openrisc/interrupt_helper.c +++ b/target-openrisc/interrupt_helper.c @@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) } if (need_flush_tlb) { - tlb_flush(&cpu->env, 1); + tlb_flush(cs, 1); } #endif cs->interrupt_request |= CPU_INTERRUPT_EXITTB; diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index dd487bd..750a936 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -139,6 +139,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int rw, int tlb_error) { + CPUState *cs = CPU(cpu); int exception = 0; switch (tlb_error) { @@ -169,24 +170,24 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, #endif } - cpu->env.exception_index = exception; + cs->exception_index = exception; cpu->env.eear = address; } #ifndef CONFIG_USER_ONLY -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, - target_ulong address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, + vaddr address, int rw, int mmu_idx) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); int ret = 0; hwaddr physical = 0; int prot = 0; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot, address, rw); if (ret == TLBRET_MATCH) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); ret = 0; @@ -198,11 +199,11 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, return ret; } #else -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, - target_ulong address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, + vaddr address, int rw, int mmu_idx) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); int ret = 0; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); ret = 1; diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index e46b092..fb457c7 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -36,20 +36,20 @@ #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_openrisc_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { if (retaddr) { /* now we have a real cpu fault. */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Raise Exception. */ - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c index be06c45..fedcbed 100644 --- a/target-openrisc/sys_helper.c +++ b/target-openrisc/sys_helper.c @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 17): /* SR */ if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ (rb & (SR_IME | SR_DME | SR_SM))) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } env->sr = rb; env->sr |= SR_FO; /* FO is const equal to 1 */ @@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); } env->tlb->dtlb[0][idx].mr = rb; break; @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); } env->tlb->itlb[0][idx].mr = rb; break; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 776cb6e..852b5e6 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1619,10 +1619,11 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc) { + CPUState *cs = CPU(cpu); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) { - QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); diff --git a/target-ppc/arch_dump.c b/target-ppc/arch_dump.c index 17fd4c6..9dccf1a 100644 --- a/target-ppc/arch_dump.c +++ b/target-ppc/arch_dump.c @@ -164,7 +164,7 @@ static void ppc64_write_elf64_speregset(Note *note, PowerPCCPU *cpu) speregset->spe_fscr = cpu_to_be32(cpu->env.spe_fscr); } -struct NoteFuncDescStruct { +static const struct NoteFuncDescStruct { int contents_size; void (*note_contents_func)(Note *note, PowerPCCPU *cpu); } note_func[] = { @@ -196,7 +196,7 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) int name_size = 8; /* "CORE" or "QEMU" rounded */ size_t elf_note_size = 0; int note_head_size; - NoteFuncDesc *nf; + const NoteFuncDesc *nf; if (class != ELFCLASS64) { return -1; @@ -221,7 +221,7 @@ static int ppc64_write_all_elf64_notes(const char *note_name, Note note; int ret = -1; int note_size; - NoteFuncDesc *nf; + const NoteFuncDesc *nf; for (nf = note_func; nf->note_contents_func; nf++) { note.hdr.n_namesz = cpu_to_be32(sizeof(note.name)); diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index b17c024..47dc8e6 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -38,6 +38,8 @@ #define POWERPC_CPU_GET_CLASS(obj) \ OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) +typedef struct PowerPCCPU PowerPCCPU; + /** * PowerPCCPUClass: * @parent_realize: The parent class' realize handler. @@ -71,7 +73,7 @@ typedef struct PowerPCCPUClass { void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); #if defined(CONFIG_SOFTMMU) - int (*handle_mmu_fault)(CPUPPCState *env, target_ulong eaddr, int rwx, + int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int mmu_idx); #endif } PowerPCCPUClass; @@ -83,14 +85,14 @@ typedef struct PowerPCCPUClass { * * A PowerPC CPU. */ -typedef struct PowerPCCPU { +struct PowerPCCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ CPUPPCState env; int cpu_dt_id; -} PowerPCCPU; +}; static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) { diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index afab267..2719c08 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -334,6 +334,7 @@ struct ppc_spr_t { void (*hea_write)(void *opaque, int spr_num, int gpr_num); #endif const char *name; + target_ulong default_value; #ifdef CONFIG_KVM /* We (ab)use the fact that all the SPRs will have ids for the * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning, @@ -1111,8 +1112,8 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo, void *puc); void ppc_hw_interrupt (CPUPPCState *env); #if defined(CONFIG_USER_ONLY) -int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, - int mmu_idx); +int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); #endif #if !defined(CONFIG_USER_ONLY) @@ -1900,6 +1901,8 @@ enum { PPC2_LSQ_ISA207 = 0x0000000000002000ULL, /* ISA 2.07 Altivec */ PPC2_ALTIVEC_207 = 0x0000000000004000ULL, + /* PowerISA 2.07 Book3s specification */ + PPC2_ISA207S = 0x0000000000008000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2100,7 +2103,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) } } - cpu_abort(env, "Unknown TLBe: %d\n", id); + cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); return 0; } @@ -2171,14 +2174,6 @@ static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) extern void (*cpu_ppc_hypercall)(PowerPCCPU *); -static inline bool cpu_has_work(CPUState *cpu) -{ - PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu); - CPUPPCState *env = &ppc_cpu->env; - - return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD); -} - #include "exec/exec-all.h" void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index d541929..19bc6b6 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -43,13 +43,15 @@ void ppc_cpu_do_interrupt(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; } void ppc_hw_interrupt(CPUPPCState *env) { - env->exception_index = POWERPC_EXCP_NONE; + CPUState *cs = CPU(ppc_env_get_cpu(env)); + + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; } #else /* defined(CONFIG_USER_ONLY) */ @@ -68,8 +70,8 @@ static inline void dump_syscall(CPUPPCState *env) */ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) { + CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - CPUState *cs; target_ulong msr, new_msr, vector; int srr0, srr1, asrr0, asrr1; int lpes0, lpes1, lev; @@ -135,7 +137,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) fprintf(stderr, "Machine check while not allowed. " "Entering checkstop state\n"); } - cs = CPU(cpu); cs->halted = 1; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } @@ -204,7 +205,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { LOG_EXCP("Ignore floating point exception\n"); - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; return; } @@ -241,7 +242,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; default: /* Should never occur */ - cpu_abort(env, "Invalid program exception %d. Aborting\n", + cpu_abort(cs, "Invalid program exception %d. Aborting\n", env->error_code); break; } @@ -301,26 +302,26 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } /* XXX: TODO */ - cpu_abort(env, "Debug exception is not implemented yet !\n"); + cpu_abort(cs, "Debug exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_current; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ /* XXX: TODO */ - cpu_abort(env, "Embedded floating point data exception " + cpu_abort(cs, "Embedded floating point data exception " "is not implemented yet !\n"); env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_next; case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ /* XXX: TODO */ - cpu_abort(env, "Embedded floating point round exception " + cpu_abort(cs, "Embedded floating point round exception " "is not implemented yet !\n"); env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_next; case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "Performance counter exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ @@ -402,15 +403,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) goto store_next; case POWERPC_EXCP_IO: /* IO error exception */ /* XXX: TODO */ - cpu_abort(env, "601 IO error exception is not implemented yet !\n"); + cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_RUNM: /* Run mode exception */ /* XXX: TODO */ - cpu_abort(env, "601 run mode exception is not implemented yet !\n"); + cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_EMUL: /* Emulation trap exception */ /* XXX: TODO */ - cpu_abort(env, "602 emulation trap exception " + cpu_abort(cs, "602 emulation trap exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ @@ -428,7 +429,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_74xx: goto tlb_miss_74xx; default: - cpu_abort(env, "Invalid instruction TLB miss exception\n"); + cpu_abort(cs, "Invalid instruction TLB miss exception\n"); break; } break; @@ -447,7 +448,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_74xx: goto tlb_miss_74xx; default: - cpu_abort(env, "Invalid data load TLB miss exception\n"); + cpu_abort(cs, "Invalid data load TLB miss exception\n"); break; } break; @@ -533,30 +534,30 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) msr |= env->error_code; /* key bit */ break; default: - cpu_abort(env, "Invalid data store TLB miss exception\n"); + cpu_abort(cs, "Invalid data store TLB miss exception\n"); break; } goto store_next; case POWERPC_EXCP_FPA: /* Floating-point assist exception */ /* XXX: TODO */ - cpu_abort(env, "Floating point assist exception " + cpu_abort(cs, "Floating point assist exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_DABR: /* Data address breakpoint */ /* XXX: TODO */ - cpu_abort(env, "DABR exception is not implemented yet !\n"); + cpu_abort(cs, "DABR exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ /* XXX: TODO */ - cpu_abort(env, "IABR exception is not implemented yet !\n"); + cpu_abort(cs, "IABR exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SMI: /* System management interrupt */ /* XXX: TODO */ - cpu_abort(env, "SMI exception is not implemented yet !\n"); + cpu_abort(cs, "SMI exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_THERM: /* Thermal interrupt */ /* XXX: TODO */ - cpu_abort(env, "Thermal management exception " + cpu_abort(cs, "Thermal management exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ @@ -564,36 +565,36 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) new_msr |= (target_ulong)MSR_HVB; } /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "Performance counter exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_VPUA: /* Vector assist exception */ /* XXX: TODO */ - cpu_abort(env, "VPU assist exception is not implemented yet !\n"); + cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SOFTP: /* Soft patch exception */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "970 soft-patch exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_MAINT: /* Maintenance exception */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "970 maintenance exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ /* XXX: TODO */ - cpu_abort(env, "Maskable external exception " + cpu_abort(cs, "Maskable external exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ /* XXX: TODO */ - cpu_abort(env, "Non maskable external exception " + cpu_abort(cs, "Non maskable external exception " "is not implemented yet !\n"); goto store_next; default: excp_invalid: - cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; store_current: /* save current instruction location */ @@ -615,7 +616,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } /* If we disactivated any translation, flush TLBs */ if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } #ifdef TARGET_PPC64 @@ -635,7 +636,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Jump to handler */ vector = env->excp_vectors[excp]; if (vector == (target_ulong)-1ULL) { - cpu_abort(env, "Raised an exception without defined vector %d\n", + cpu_abort(cs, "Raised an exception without defined vector %d\n", excp); } vector |= env->excp_prefix; @@ -662,7 +663,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) hreg_compute_hflags(env); env->nip = vector; /* Reset exception state */ - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; if ((env->mmu_model == POWERPC_MMU_BOOKE) || @@ -670,7 +671,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* XXX: The BookE changes address space when switching modes, we should probably implement that as different MMU indexes, but for the moment we do it the slow way and flush all. */ - tlb_flush(env, 1); + tlb_flush(cs, 1); } } @@ -679,7 +680,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - powerpc_excp(cpu, env->excp_model, env->exception_index); + powerpc_excp(cpu, env->excp_model, cs->exception_index); } void ppc_hw_interrupt(CPUPPCState *env) @@ -815,12 +816,14 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr) void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, uint32_t error_code) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + #if 0 printf("Raise exception %3x code : %d\n", exception, error_code); #endif - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_exception(CPUPPCState *env, uint32_t exception) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index e7f3295..fd91239 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -119,6 +119,7 @@ uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf) static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint64_t ret = 0; int ve; @@ -155,7 +156,7 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op, } /* We must update the target FPR before raising the exception */ if (ve != 0) { - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; @@ -224,6 +225,8 @@ static inline void float_zero_divide_excp(CPUPPCState *env) static inline void float_overflow_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_OX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -232,7 +235,7 @@ static inline void float_overflow_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; } else { env->fpscr |= 1 << FPSCR_XX; @@ -242,6 +245,8 @@ static inline void float_overflow_excp(CPUPPCState *env) static inline void float_underflow_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_UX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -250,13 +255,15 @@ static inline void float_underflow_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; } } static inline void float_inexact_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_XX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -264,7 +271,7 @@ static inline void float_inexact_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; } } @@ -316,6 +323,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int prev; prev = (env->fpscr >> bit) & 1; @@ -439,7 +447,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We have to update Rc1 before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; break; } } @@ -447,6 +455,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong prev, new; int i; @@ -468,7 +477,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) } if ((fpscr_ex & fpscr_eex) != 0) { env->fpscr |= 1 << FPSCR_FEX; - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; /* XXX: we should compute it properly */ env->error_code = POWERPC_EXCP_FP; } else { @@ -484,6 +493,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) void helper_float_check_status(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int status = get_float_exception_flags(&env->fp_status); if (status & float_flag_divbyzero) { @@ -496,11 +506,11 @@ void helper_float_check_status(CPUPPCState *env) float_inexact_excp(env); } - if (env->exception_index == POWERPC_EXCP_PROGRAM && + if (cs->exception_index == POWERPC_EXCP_PROGRAM && (env->error_code & POWERPC_EXCP_FP)) { /* Differred floating-point exception after target FPR update */ if (msr_fe0 != 0 || msr_fe1 != 0) { - helper_raise_exception_err(env, env->exception_index, + helper_raise_exception_err(env, cs->exception_index, env->error_code); } } diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index c02e8da..f7ec9c2 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, if (((value >> MSR_IR) & 1) != msr_ir || ((value >> MSR_DR) & 1) != msr_dr) { /* Flush all tlb when changing translation mode */ - tlb_flush(env, 1); + tlb_flush(cs, 1); excp = POWERPC_EXCP_NONE; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 63dde94..18b54f0 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1075,7 +1075,7 @@ void helper_vbpermq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) #undef VBPERMQ_INDEX #undef VBPERMQ_DW -uint64_t VGBBD_MASKS[256] = { +static const uint64_t VGBBD_MASKS[256] = { 0x0000000000000000ull, /* 00 */ 0x0000000000000080ull, /* 01 */ 0x0000000000008000ull, /* 02 */ @@ -2216,7 +2216,7 @@ static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b) uint8_t dig_a = bcd_get_digit(a, i, &invalid); uint8_t dig_b = bcd_get_digit(b, i, &invalid); if (unlikely(invalid)) { - return 0; /* doesnt matter */ + return 0; /* doesn't matter */ } else if (dig_a > dig_b) { return 1; } else if (dig_a < dig_b) { diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 32e7a8c..9974b10 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -1178,7 +1178,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu) if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } return 0; @@ -1504,7 +1504,6 @@ int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) void kvmppc_set_papr(PowerPCCPU *cpu) { - CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); struct kvm_enable_cap cap = {}; int ret; @@ -1513,7 +1512,7 @@ void kvmppc_set_papr(PowerPCCPU *cpu) ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); if (ret) { - cpu_abort(env, "This KVM version does not support PAPR\n"); + cpu_abort(cs, "This KVM version does not support PAPR\n"); } /* Update the capability flag so we sync the right information @@ -1523,7 +1522,6 @@ void kvmppc_set_papr(PowerPCCPU *cpu) void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) { - CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); struct kvm_enable_cap cap = {}; int ret; @@ -1533,7 +1531,7 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); if (ret && mpic_proxy) { - cpu_abort(env, "This KVM version does not support EPR\n"); + cpu_abort(cs, "This KVM version does not support EPR\n"); } } diff --git a/target-ppc/machine.c b/target-ppc/machine.c index 2d46cec..063b379 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -114,7 +114,7 @@ static void put_avr(QEMUFile *f, void *pv, size_t size) qemu_put_be64(f, v->u64[1]); } -const VMStateInfo vmstate_info_avr = { +static const VMStateInfo vmstate_info_avr = { .name = "avr", .get = get_avr, .put = put_avr, @@ -288,7 +288,7 @@ static void put_slbe(QEMUFile *f, void *pv, size_t size) qemu_put_be64(f, v->vsid); } -const VMStateInfo vmstate_info_slbe = { +static const VMStateInfo vmstate_info_slbe = { .name = "slbe", .get = get_slbe, .put = put_slbe, diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c index dc2ebfc..2eb2fa6 100644 --- a/target-ppc/misc_helper.c +++ b/target-ppc/misc_helper.c @@ -62,10 +62,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + if (likely(env->pb[num] != value)) { env->pb[num] = value; /* Should be optimized */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 6a77dc4..1cc1916 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -222,6 +222,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, target_ulong eaddr, int rwx, hwaddr *raddr, int *prot) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); LOG_MMU("direct store...\n"); @@ -238,7 +239,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, if (rwx == 2) { /* No code fetch is allowed in direct-store areas */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -249,7 +250,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, break; case ACCESS_FLOAT: /* Floating point load/store */ - env->exception_index = POWERPC_EXCP_ALIGN; + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = eaddr; return 1; @@ -272,7 +273,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, return 0; case ACCESS_EXT: /* eciwx or ecowx */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -290,7 +291,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, *raddr = eaddr; return 0; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -380,9 +381,11 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int mmu_idx) { + CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; target_ulong sr; hwaddr pte_offset; ppc_hash_pte32_t pte; @@ -397,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { /* Translation is off */ raddr = eaddr; - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -409,10 +412,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, if (raddr != -1) { if (need_prot[rwx] & ~prot) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -424,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, return 1; } - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -438,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, if (sr & SR32_T) { if (ppc_hash32_direct_store(env, sr, eaddr, rwx, &raddr, &prot) == 0) { - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -449,7 +452,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, /* 5. Check for segment level no-execute violation */ if ((rwx == 2) && (sr & SR32_NX)) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -458,10 +461,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte); if (pte_offset == -1) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -483,10 +486,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, /* Access right violation */ LOG_MMU("PTE access rejected\n"); if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -519,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, raddr = ppc_hash32_pte_raddr(sr, pte, eaddr); - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h index 4671141..d515d4f 100644 --- a/target-ppc/mmu-hash32.h +++ b/target-ppc/mmu-hash32.h @@ -5,7 +5,7 @@ hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash); hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr); -int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw, int mmu_idx); /* @@ -68,7 +68,8 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env, hwaddr pte_offset) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); + assert(!env->external_htab); /* Not supported on 32-bit for now */ return ldl_phys(cs->as, env->htab_base + pte_offset); } @@ -76,7 +77,8 @@ static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env, static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env, hwaddr pte_offset) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); + assert(!env->external_htab); /* Not supported on 32-bit for now */ return ldl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2); } @@ -84,7 +86,8 @@ static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env, static inline void ppc_hash32_store_hpte0(CPUPPCState *env, hwaddr pte_offset, target_ulong pte0) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); + assert(!env->external_htab); /* Not supported on 32-bit for now */ stl_phys(cs->as, env->htab_base + pte_offset, pte0); } @@ -92,7 +95,8 @@ static inline void ppc_hash32_store_hpte0(CPUPPCState *env, static inline void ppc_hash32_store_hpte1(CPUPPCState *env, hwaddr pte_offset, target_ulong pte1) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); + assert(!env->external_htab); /* Not supported on 32-bit for now */ stl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1); } diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index f2af4fb..1fefe58 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -99,6 +99,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) void helper_slbia(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int n, do_invalidate; do_invalidate = 0; @@ -116,12 +117,13 @@ void helper_slbia(CPUPPCState *env) } } if (do_invalidate) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } void helper_slbie(CPUPPCState *env, target_ulong addr) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppc_slb_t *slb; slb = slb_lookup(env, addr); @@ -136,7 +138,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) * in QEMU, we just invalidate all TLBs */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -454,9 +456,11 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte, return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int mmu_idx) { + CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; ppc_slb_t *slb; hwaddr pte_offset; ppc_hash_pte64_t pte; @@ -472,7 +476,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, /* Translation is off */ /* In real mode the top 4 effective address bits are ignored */ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -483,10 +487,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, if (!slb) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISEG; + cs->exception_index = POWERPC_EXCP_ISEG; env->error_code = 0; } else { - env->exception_index = POWERPC_EXCP_DSEG; + cs->exception_index = POWERPC_EXCP_DSEG; env->error_code = 0; env->spr[SPR_DAR] = eaddr; } @@ -495,7 +499,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, /* 3. Check for segment level no-execute violation */ if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -504,10 +508,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte); if (pte_offset == -1) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -530,12 +534,12 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, /* Access right violation */ LOG_MMU("PTE access rejected\n"); if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { target_ulong dsisr = 0; - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (need_prot[rwx] & ~pp_prot) { @@ -574,7 +578,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, raddr = ppc_hash64_pte_raddr(slb, pte, eaddr); - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -608,7 +612,7 @@ void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong pte_index, target_ulong pte0, target_ulong pte1) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); if (kvmppc_kern_htab) { return kvmppc_hash64_write_pte(env, pte_index, pte0, pte1); diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 1746b3e..49e385d 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -7,7 +7,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs); hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr); -int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw, int mmu_idx); void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong index, target_ulong pte0, target_ulong pte1); @@ -85,8 +85,9 @@ void ppc_hash64_stop_access(uint64_t token); static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env, uint64_t token, int index) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint64_t addr; + addr = token + (index * HASH_PTE_SIZE_64); if (env->external_htab) { return ldq_p((const void *)(uintptr_t)addr); @@ -98,8 +99,9 @@ static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env, static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env, uint64_t token, int index) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint64_t addr; + addr = token + (index * HASH_PTE_SIZE_64) + HASH_PTE_SIZE_64/2; if (env->external_htab) { return ldq_p((const void *)(uintptr_t)addr); diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 8e2f8e7..1771863 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -231,6 +231,7 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppc6xx_tlb_t *tlb; int nr, max; @@ -244,7 +245,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlb6[nr]; pte_invalidate(&tlb->pte0); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, @@ -252,6 +253,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppc6xx_tlb_t *tlb; int way, nr; @@ -263,7 +265,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr, env->nb_tlb, eaddr); pte_invalidate(&tlb->pte0); - tlb_flush_page(env, tlb->EPN); + tlb_flush_page(cs, tlb->EPN); } } #else @@ -643,6 +645,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, /* Helpers specific to PowerPC 40x implementations */ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; int i; @@ -650,13 +653,14 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlbe[i]; tlb->prot &= ~PAGE_VALID; } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, target_ulong eaddr, uint32_t pid) { #if !defined(FLUSH_ALL_TLBS) + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppcemb_tlb_t *tlb; hwaddr raddr; target_ulong page, end; @@ -667,7 +671,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { end = tlb->EPN + tlb->size; for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } tlb->prot &= ~PAGE_VALID; break; @@ -746,9 +750,11 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, void store_40x_sler(CPUPPCState *env, uint32_t val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + /* XXX: TO BE FIXED */ if (val != 0x00000000) { - cpu_abort(env, "Little-endian regions are not supported by now\n"); + cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n"); } env->spr[SPR_405_SLER] = val; } @@ -858,6 +864,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, static void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int tlb_size; int i, j; ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -874,7 +881,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags, tlb += booke206_tlb_size(env, i); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, @@ -1344,6 +1351,7 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int access_type) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int ret = -1; bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) || (access_type != ACCESS_CODE && msr_dr == 0); @@ -1388,17 +1396,17 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: if (real_mode) { ret = check_physical(env, ctx, eaddr, rw); } else { - cpu_abort(env, "PowerPC in real mode do not do any translation\n"); + cpu_abort(CPU(cpu), "PowerPC in real mode do not do any translation\n"); } return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n"); return -1; } #if 0 @@ -1491,6 +1499,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); mmu_ctx_t ctx; int access_type; int ret = 0; @@ -1505,29 +1514,29 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, } ret = get_physical_address(env, &ctx, address, rw, access_type); if (ret == 0) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, mmu_idx, TARGET_PAGE_SIZE); ret = 0; } else if (ret < 0) { - LOG_MMU_STATE(CPU(ppc_env_get_cpu(env))); + LOG_MMU_STATE(cs); if (access_type == ACCESS_CODE) { switch (ret) { case -1: /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - env->exception_index = POWERPC_EXCP_IFTLB; + cs->exception_index = POWERPC_EXCP_IFTLB; env->error_code = 1 << 18; env->spr[SPR_IMISS] = address; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; case POWERPC_MMU_SOFT_74xx: - env->exception_index = POWERPC_EXCP_IFTLB; + cs->exception_index = POWERPC_EXCP_IFTLB; goto tlb_miss_74xx; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: - env->exception_index = POWERPC_EXCP_ITLB; + cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; env->spr[SPR_40x_ESR] = 0x00000000; @@ -1536,26 +1545,26 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, booke206_update_mas_tlb_miss(env, address, rw); /* fall through */ case POWERPC_MMU_BOOKE: - env->exception_index = POWERPC_EXCP_ITLB; + cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; return -1; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: - cpu_abort(env, "PowerPC in real mode should never raise " + cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(cs, "Unknown or invalid MMU model\n"); return -1; } break; case -2: /* Access rights violation */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; break; case -3: @@ -1564,13 +1573,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, (env->mmu_model == POWERPC_MMU_BOOKE206)) { env->spr[SPR_BOOKE_ESR] = 0x00000000; } - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; case -4: /* Direct store exception */ /* No code fetch is allowed in direct-store areas */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; } @@ -1581,10 +1590,10 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: if (rw == 1) { - env->exception_index = POWERPC_EXCP_DSTLB; + cs->exception_index = POWERPC_EXCP_DSTLB; env->error_code = 1 << 16; } else { - env->exception_index = POWERPC_EXCP_DLTLB; + cs->exception_index = POWERPC_EXCP_DLTLB; env->error_code = 0; } env->spr[SPR_DMISS] = address; @@ -1598,9 +1607,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_SOFT_74xx: if (rw == 1) { - env->exception_index = POWERPC_EXCP_DSTLB; + cs->exception_index = POWERPC_EXCP_DSTLB; } else { - env->exception_index = POWERPC_EXCP_DLTLB; + cs->exception_index = POWERPC_EXCP_DLTLB; } tlb_miss_74xx: /* Implement LRU algorithm */ @@ -1611,7 +1620,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: - env->exception_index = POWERPC_EXCP_DTLB; + cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; if (rw) { @@ -1622,29 +1631,29 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE206: booke206_update_mas_tlb_miss(env, address, rw); /* fall through */ case POWERPC_MMU_BOOKE: - env->exception_index = POWERPC_EXCP_DTLB; + cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0; return -1; case POWERPC_MMU_REAL: - cpu_abort(env, "PowerPC in real mode should never raise " + cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(cs, "Unknown or invalid MMU model\n"); return -1; } break; case -2: /* Access rights violation */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; if (env->mmu_model == POWERPC_MMU_SOFT_4xx || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { @@ -1670,13 +1679,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, switch (access_type) { case ACCESS_FLOAT: /* Floating point load/store */ - env->exception_index = POWERPC_EXCP_ALIGN; + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = address; break; case ACCESS_RES: /* lwarx, ldarx or stwcx. */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) { @@ -1687,7 +1696,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case ACCESS_EXT: /* eciwx or ecowx */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) { @@ -1698,7 +1707,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; default: printf("DSI: invalid exception (%d)\n", ret); - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; env->spr[SPR_DAR] = address; @@ -1709,7 +1718,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, } #if 0 printf("%s: set exception to %d %02x\n", __func__, - env->exception, env->error_code); + cs->exception, env->error_code); #endif ret = 1; } @@ -1723,6 +1732,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, target_ulong mask) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong base, end, page; base = BATu & ~0x0001FFFF; @@ -1730,7 +1740,7 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", base, end, mask); for (page = base; page != end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } LOG_BATS("Flush done\n"); } @@ -1892,6 +1902,8 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) /* TLB management */ void ppc_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: @@ -1902,14 +1914,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case POWERPC_MMU_BOOKE206: booke206_flush_tlb(env, -1, 0); @@ -1922,11 +1934,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: #endif /* defined(TARGET_PPC64) */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; default: /* XXX: TODO */ - cpu_abort(env, "Unknown MMU model\n"); + cpu_abort(CPU(cpu), "Unknown MMU model\n"); break; } } @@ -1934,6 +1946,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) { #if !defined(FLUSH_ALL_TLBS) + PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs; + addr &= TARGET_PAGE_MASK; switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: @@ -1948,43 +1963,44 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); break; case POWERPC_MMU_REAL: - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: /* XXX: TODO */ - cpu_abort(env, "BookE MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE206: /* XXX: TODO */ - cpu_abort(env, "BookE 2.06 MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n"); break; case POWERPC_MMU_32B: case POWERPC_MMU_601: /* tlbie invalidate TLBs for all segments */ addr &= ~((target_ulong)-1ULL << 28); + cs = CPU(cpu); /* XXX: this case should be optimized, * giving a mask to tlb_flush_page */ - tlb_flush_page(env, addr | (0x0 << 28)); - tlb_flush_page(env, addr | (0x1 << 28)); - tlb_flush_page(env, addr | (0x2 << 28)); - tlb_flush_page(env, addr | (0x3 << 28)); - tlb_flush_page(env, addr | (0x4 << 28)); - tlb_flush_page(env, addr | (0x5 << 28)); - tlb_flush_page(env, addr | (0x6 << 28)); - tlb_flush_page(env, addr | (0x7 << 28)); - tlb_flush_page(env, addr | (0x8 << 28)); - tlb_flush_page(env, addr | (0x9 << 28)); - tlb_flush_page(env, addr | (0xA << 28)); - tlb_flush_page(env, addr | (0xB << 28)); - tlb_flush_page(env, addr | (0xC << 28)); - tlb_flush_page(env, addr | (0xD << 28)); - tlb_flush_page(env, addr | (0xE << 28)); - tlb_flush_page(env, addr | (0xF << 28)); + tlb_flush_page(cs, addr | (0x0 << 28)); + tlb_flush_page(cs, addr | (0x1 << 28)); + tlb_flush_page(cs, addr | (0x2 << 28)); + tlb_flush_page(cs, addr | (0x3 << 28)); + tlb_flush_page(cs, addr | (0x4 << 28)); + tlb_flush_page(cs, addr | (0x5 << 28)); + tlb_flush_page(cs, addr | (0x6 << 28)); + tlb_flush_page(cs, addr | (0x7 << 28)); + tlb_flush_page(cs, addr | (0x8 << 28)); + tlb_flush_page(cs, addr | (0x9 << 28)); + tlb_flush_page(cs, addr | (0xA << 28)); + tlb_flush_page(cs, addr | (0xB << 28)); + tlb_flush_page(cs, addr | (0xC << 28)); + tlb_flush_page(cs, addr | (0xD << 28)); + tlb_flush_page(cs, addr | (0xE << 28)); + tlb_flush_page(cs, addr | (0xF << 28)); break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: @@ -1996,12 +2012,12 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, * we just invalidate all TLBs */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; #endif /* defined(TARGET_PPC64) */ default: /* XXX: TODO */ - cpu_abort(env, "Unknown MMU model\n"); + cpu_abort(CPU(cpu), "Unknown MMU model\n"); break; } #else @@ -2013,6 +2029,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) /* Special registers manipulation */ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); assert(!env->external_htab); if (env->spr[SPR_SDR1] != value) { @@ -2035,7 +2053,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF; env->htab_base = value & SDR_32_HTABORG; } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -2053,6 +2071,8 @@ target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num) void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) @@ -2085,11 +2105,11 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) page = (16 << 20) * srnum; end = page + (16 << 20); for (; page != end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(CPU(cpu), page); } } #else - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); #endif } } @@ -2316,6 +2336,8 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry) void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs = CPU(cpu); ppcemb_tlb_t *tlb; target_ulong page, end; @@ -2329,7 +2351,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end); for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } } tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT) @@ -2339,7 +2361,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, * of the ppc or ppc64 one */ if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) { - cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u " + cpu_abort(cs, "TLB size " TARGET_FMT_lu " < %u " "are not supported (%d)\n", tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7)); } @@ -2348,7 +2370,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot |= PAGE_VALID; if (val & PPC4XX_TLBHI_E) { /* XXX: TO BE FIXED */ - cpu_abort(env, + cpu_abort(cs, "Little-endian TLB entries are not supported by now\n"); } } else { @@ -2368,7 +2390,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end); for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } } } @@ -2409,6 +2431,7 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address) void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong EPN, RPN, size; int do_flush_tlbs; @@ -2444,13 +2467,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, } tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF; if (do_flush_tlbs) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 1: RPN = value & 0xFFFFFC0F; if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } tlb->RPN = RPN; break; @@ -2544,6 +2567,7 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address) static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg = 0; int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT; int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK); @@ -2553,7 +2577,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb]; if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) { - cpu_abort(env, "we don't support HES yet\n"); + cpu_abort(CPU(cpu), "we don't support HES yet\n"); } return booke206_get_tlbm(env, tlb, ea, esel); @@ -2561,13 +2585,16 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + env->spr[pidn] = pid; /* changing PIDs mean we're in a different address space now */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbwe(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; @@ -2621,7 +2648,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } if (msr_gs) { - cpu_abort(env, "missing HV implementation\n"); + cpu_abort(CPU(cpu), "missing HV implementation\n"); } tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) | env->spr[SPR_BOOKE_MAS3]; @@ -2655,9 +2682,9 @@ void helper_booke206_tlbwe(CPUPPCState *env) } if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) { - tlb_flush_page(env, tlb->mas2 & MAS2_EPN_MASK); + tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); } else { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -2764,6 +2791,8 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn, void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + if (address & 0x4) { /* flush all entries */ if (address & 0x8) { @@ -2779,11 +2808,11 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) if (address & 0x8) { /* flush TLB1 entries */ booke206_invalidate_ea_tlb(env, 1, address); - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); - tlb_flush_page(env, address & MAS2_EPN_MASK); + tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK); } } @@ -2795,6 +2824,7 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address) void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -2811,11 +2841,12 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) } tlb += booke206_tlb_size(env, i); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; ppcmas_tlb_t *tlb; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); @@ -2851,7 +2882,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) tlb->mas1 &= ~MAS1_VALID; } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) @@ -2892,23 +2923,24 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - CPUState *cpu = CPU(ppc_env_get_cpu(env)); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); + CPUPPCState *env = &cpu->env; int ret; if (pcc->handle_mmu_fault) { - ret = pcc->handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = pcc->handle_mmu_fault(cpu, addr, is_write, mmu_idx); } else { ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx); } if (unlikely(ret != 0)) { if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - helper_raise_exception_err(env, env->exception_index, env->error_code); + helper_raise_exception_err(env, cs->exception_index, env->error_code); } } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 91c33dc..e3fcb03 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11377,8 +11377,8 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, /* Set env in case of segfault during code fetch */ while (ctx.exception == POWERPC_EXCP_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.nip) { gen_debug_exception(ctxp); break; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 3eafbb0..7f53c33 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -631,7 +631,7 @@ static inline void _spr_register(CPUPPCState *env, int num, #if defined(CONFIG_KVM) spr->one_reg_id = one_reg_id, #endif - env->spr[num] = initial_value; + env->spr[num] = spr->default_value = initial_value; } /* Generic PowerPC SPRs */ @@ -4432,6 +4432,7 @@ enum fsl_e500_version { static void init_proc_e500 (CPUPPCState *env, int version) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg[2]; uint64_t ivor_mask; uint64_t ivpr_mask = 0xFFFF0000ULL; @@ -4490,7 +4491,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); break; default: - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } #endif /* Cache sizes */ @@ -4507,7 +4508,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) l1cfg0 |= 0x1000000; /* 64 byte cache block size */ break; default: - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } gen_spr_BookE206(env, 0x000000DF, tlbncfg); /* XXX : not implemented */ @@ -7172,7 +7173,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207; + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7433,7 +7435,7 @@ static int create_new_table (opc_handler_t **table, unsigned char idx) { opc_handler_t **tmp; - tmp = g_malloc(0x20 * sizeof(opc_handler_t)); + tmp = g_new(opc_handler_t *, 0x20); fill_new_table(tmp, 0x20); table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); @@ -7847,6 +7849,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) max_smt, kvm_enabled() ? "KVM" : "TCG"); return; } + if (!is_power_of_2(smp_threads)) { + error_setg(errp, "Cannot support %d threads on PPC with %s, " + "threads count must be a power of 2.", + smp_threads, kvm_enabled() ? "KVM" : "TCG"); + return; + } cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt + (cs->cpu_index % smp_threads); @@ -8220,26 +8228,7 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name) PowerPCCPU *cpu_ppc_init(const char *cpu_model) { - PowerPCCPU *cpu; - ObjectClass *oc; - Error *err = NULL; - - oc = ppc_cpu_class_by_name(cpu_model); - if (oc == NULL) { - return NULL; - } - - cpu = POWERPC_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", &err); - if (err != NULL) { - error_report("%s", error_get_pretty(err)); - error_free(err); - object_unref(OBJECT(cpu)); - return NULL; - } - - return cpu; + return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); } /* Sort by PVR, ordering special case "host" last. */ @@ -8384,6 +8373,14 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.nip = value; } +static bool ppc_cpu_has_work(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); +} + /* CPUClass::reset() */ static void ppc_cpu_reset(CPUState *s) { @@ -8391,6 +8388,7 @@ static void ppc_cpu_reset(CPUState *s) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; target_ulong msr; + int i; pcc->parent_reset(s); @@ -8433,7 +8431,7 @@ static void ppc_cpu_reset(CPUState *s) env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ env->pending_interrupts = 0; - env->exception_index = POWERPC_EXCP_NONE; + s->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) @@ -8444,8 +8442,17 @@ static void ppc_cpu_reset(CPUState *s) env->dtl_size = 0; #endif /* TARGET_PPC64 */ + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { + ppc_spr_t *spr = &env->spr_cb[i]; + + if (!spr->name) { + continue; + } + env->spr[i] = spr->default_value; + } + /* Flush all TLBs */ - tlb_flush(env, 1); + tlb_flush(s, 1); } static void ppc_cpu_initfn(Object *obj) @@ -8511,13 +8518,16 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->reset = ppc_cpu_reset; cc->class_by_name = ppc_cpu_class_by_name; + cc->has_work = ppc_cpu_has_work; cc->do_interrupt = ppc_cpu_do_interrupt; cc->dump_state = ppc_cpu_dump_state; cc->dump_statistics = ppc_cpu_dump_statistics; cc->set_pc = ppc_cpu_set_pc; cc->gdb_read_register = ppc_cpu_gdb_read_register; cc->gdb_write_register = ppc_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_ppc_cpu; #if defined(TARGET_PPC64) diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c index 56e686e..829f66f 100644 --- a/target-ppc/user_only_helper.c +++ b/target-ppc/user_only_helper.c @@ -20,9 +20,11 @@ #include "cpu.h" -int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, - int mmu_idx) +int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; int exception, error_code; if (rw == 2) { @@ -37,7 +39,7 @@ int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, env->spr[SPR_DAR] = address; env->spr[SPR_DSISR] = error_code; } - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; return 1; diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index a6d60bf..9e676a5 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -407,6 +407,7 @@ static uint32_t cc_calc_flogr(uint64_t dst) static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr) { + S390CPU *cpu = s390_env_get_cpu(env); uint32_t r = 0; switch (cc_op) { @@ -524,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, break; default: - cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op)); + cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op)); } HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__, @@ -548,7 +549,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src, void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { load_psw(env, mask, addr); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } void HELPER(sacf)(CPUS390XState *env, uint64_t a1) diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 1a8c1cc..dfd83e8 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -65,6 +65,15 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr = value; } +static bool s390_cpu_has_work(CPUState *cs) +{ + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + + return (cs->interrupt_request & CPU_INTERRUPT_HARD) && + (env->psw.mask & PSW_MASK_EXT); +} + #if !defined(CONFIG_USER_ONLY) /* S390CPUClass::load_normal() */ static void s390_cpu_load_normal(CPUState *s) @@ -89,7 +98,7 @@ static void s390_cpu_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) s->halted = 1; #endif - tlb_flush(env, 1); + tlb_flush(s, 1); } /* S390CPUClass::initial_reset() */ @@ -100,7 +109,7 @@ static void s390_cpu_initial_reset(CPUState *s) s390_cpu_reset(s); /* initial reset does not touch regs,fregs and aregs */ - memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) - + memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) - offsetof(CPUS390XState, fpc)); /* architectured initial values for CR 0 and 14 */ @@ -130,7 +139,7 @@ static void s390_cpu_full_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUS390XState, breakpoints)); + memset(env, 0, offsetof(CPUS390XState, cpu_num)); /* architectured initial values for CR 0 and 14 */ env->cregs[0] = CR0_RESET; @@ -144,7 +153,7 @@ static void s390_cpu_full_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) s->halted = 1; #endif - tlb_flush(env, 1); + tlb_flush(s, 1); } #if !defined(CONFIG_USER_ONLY) @@ -232,12 +241,15 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) scc->cpu_reset = s390_cpu_reset; scc->initial_cpu_reset = s390_cpu_initial_reset; cc->reset = s390_cpu_full_reset; + cc->has_work = s390_cpu_has_work; cc->do_interrupt = s390_cpu_do_interrupt; cc->dump_state = s390_cpu_dump_state; cc->set_pc = s390_cpu_set_pc; cc->gdb_read_register = s390_cpu_gdb_read_register; cc->gdb_write_register = s390_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; cc->write_elf64_note = s390_cpu_write_elf64_note; cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote; diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index effe84b..f332d41 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -320,9 +320,8 @@ int cpu_s390x_exec(CPUS390XState *s); is returned if the signal was handled by the virtual CPU. */ int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); -int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw, - int mmu_idx); -#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault +int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); #include "ioinst.h" @@ -1041,15 +1040,6 @@ static inline void cpu_inject_crw_mchk(S390CPU *cpu) cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); } -static inline bool cpu_has_work(CPUState *cpu) -{ - S390CPU *s390_cpu = S390_CPU(cpu); - CPUS390XState *env = &s390_cpu->env; - - return (cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->psw.mask & PSW_MASK_EXT); -} - /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); uint32_t set_cc_nz_f64(float64 v); diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c index 94375b6..3e9c7b2 100644 --- a/target-s390x/fpu_helper.c +++ b/target-s390x/fpu_helper.c @@ -80,6 +80,8 @@ static void handle_exceptions(CPUS390XState *env, uintptr_t retaddr) static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) { + S390CPU *cpu = s390_env_get_cpu(env); + switch (float_compare) { case float_relation_equal: return 0; @@ -90,7 +92,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) case float_relation_unordered: return 3; default: - cpu_abort(env, "unknown return value for float compare\n"); + cpu_abort(CPU(cpu), "unknown return value for float compare\n"); } } diff --git a/target-s390x/helper.c b/target-s390x/helper.c index aa537e1..aa628b8 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -85,20 +85,19 @@ S390CPU *cpu_s390x_init(const char *cpu_model) void s390_cpu_do_interrupt(CPUState *cs) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } -int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address, - int rw, int mmu_idx) +int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, + int rw, int mmu_idx) { - env->exception_index = EXCP_PGM; - env->int_pgm_code = PGM_ADDRESSING; + S390CPU *cpu = S390_CPU(cs); + + cs->exception_index = EXCP_PGM; + cpu->env.int_pgm_code = PGM_ADDRESSING; /* On real machines this value is dropped into LowMem. Since this is userland, simply put this someplace that cpu_loop can find it. */ - env->__excp_addr = address; + cpu->env.__excp_addr = address; return 1; } @@ -108,13 +107,16 @@ int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address, static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen) { - env->exception_index = EXCP_PGM; + CPUState *cs = CPU(s390_env_get_cpu(env)); + + cs->exception_index = EXCP_PGM; env->int_pgm_code = code; env->int_pgm_ilen = ilen; } static int trans_bits(CPUS390XState *env, uint64_t mode) { + S390CPU *cpu = s390_env_get_cpu(env); int bits = 0; switch (mode) { @@ -128,7 +130,7 @@ static int trans_bits(CPUS390XState *env, uint64_t mode) bits = 3; break; default: - cpu_abort(env, "unknown asc mode\n"); + cpu_abort(CPU(cpu), "unknown asc mode\n"); break; } @@ -138,7 +140,7 @@ static int trans_bits(CPUS390XState *env, uint64_t mode) static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(s390_env_get_cpu(env)); int ilen = ILEN_LATER_INC; int bits = trans_bits(env, mode) | 4; @@ -152,7 +154,7 @@ static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type, uint64_t asc, int rw) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(s390_env_get_cpu(env)); int ilen = ILEN_LATER; int bits = trans_bits(env, asc); @@ -172,7 +174,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc, uint64_t asce, int level, target_ulong *raddr, int *flags, int rw) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(s390_env_get_cpu(env)); uint64_t offs = 0; uint64_t origin; uint64_t new_asce; @@ -379,14 +381,16 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, return r; } -int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr, - int rw, int mmu_idx) +int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, + int rw, int mmu_idx) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; uint64_t asc = env->psw.mask & PSW_MASK_ASC; target_ulong vaddr, raddr; int prot; - DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n", + DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, orig_vaddr, rw, mmu_idx); orig_vaddr &= TARGET_PAGE_MASK; @@ -413,7 +417,7 @@ int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr, DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); - tlb_set_page(env, orig_vaddr, raddr, prot, + tlb_set_page(cs, orig_vaddr, raddr, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -425,7 +429,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) CPUS390XState *env = &cpu->env; target_ulong raddr; int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - int old_exc = env->exception_index; + int old_exc = cs->exception_index; uint64_t asc = env->psw.mask & PSW_MASK_ASC; /* 31-Bit mode */ @@ -434,7 +438,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) } mmu_translate(env, vaddr, 2, asc, &raddr, &prot); - env->exception_index = old_exc; + cs->exception_index = old_exc; return raddr; } @@ -452,7 +456,7 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) } } cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } env->psw.addr = addr; @@ -476,13 +480,14 @@ static uint64_t get_psw_mask(CPUS390XState *env) static LowCore *cpu_map_lowcore(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); LowCore *lowcore; hwaddr len = sizeof(LowCore); lowcore = cpu_physical_memory_map(env->psa, &len, 1); if (len < sizeof(LowCore)) { - cpu_abort(env, "Could not map lowcore\n"); + cpu_abort(CPU(cpu), "Could not map lowcore\n"); } return lowcore; @@ -580,16 +585,17 @@ static void do_program_interrupt(CPUS390XState *env) static void do_ext_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); uint64_t mask, addr; LowCore *lowcore; ExtQueue *q; if (!(env->psw.mask & PSW_MASK_EXT)) { - cpu_abort(env, "Ext int w/o ext mask\n"); + cpu_abort(CPU(cpu), "Ext int w/o ext mask\n"); } if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) { - cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index); + cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index); } q = &env->ext_queue[env->ext_index]; @@ -619,6 +625,7 @@ static void do_ext_interrupt(CPUS390XState *env) static void do_io_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); LowCore *lowcore; IOIntQueue *q; uint8_t isc; @@ -626,7 +633,7 @@ static void do_io_interrupt(CPUS390XState *env) int found = 0; if (!(env->psw.mask & PSW_MASK_IO)) { - cpu_abort(env, "I/O int w/o I/O mask\n"); + cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n"); } for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) { @@ -636,7 +643,7 @@ static void do_io_interrupt(CPUS390XState *env) continue; } if (env->io_index[isc] > MAX_IO_QUEUE) { - cpu_abort(env, "I/O queue overrun for isc %d: %d\n", + cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n", isc, env->io_index[isc]); } @@ -683,24 +690,25 @@ static void do_io_interrupt(CPUS390XState *env) static void do_mchk_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); uint64_t mask, addr; LowCore *lowcore; MchkQueue *q; int i; if (!(env->psw.mask & PSW_MASK_MCHECK)) { - cpu_abort(env, "Machine check w/o mchk mask\n"); + cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n"); } if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) { - cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index); + cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index); } q = &env->mchk_queue[env->mchk_index]; if (q->type != 1) { /* Don't know how to handle this... */ - cpu_abort(env, "Unknown machine check type %d\n", q->type); + cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type); } if (!(env->cregs[14] & (1 << 28))) { /* CRW machine checks disabled */ @@ -749,43 +757,43 @@ void s390_cpu_do_interrupt(CPUState *cs) CPUS390XState *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n", - __func__, env->exception_index, env->psw.addr); + __func__, cs->exception_index, env->psw.addr); s390_add_running_cpu(cpu); /* handle machine checks */ if ((env->psw.mask & PSW_MASK_MCHECK) && - (env->exception_index == -1)) { + (cs->exception_index == -1)) { if (env->pending_int & INTERRUPT_MCHK) { - env->exception_index = EXCP_MCHK; + cs->exception_index = EXCP_MCHK; } } /* handle external interrupts */ if ((env->psw.mask & PSW_MASK_EXT) && - env->exception_index == -1) { + cs->exception_index == -1) { if (env->pending_int & INTERRUPT_EXT) { /* code is already in env */ - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; } else if (env->pending_int & INTERRUPT_TOD) { cpu_inject_ext(cpu, 0x1004, 0, 0); - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; env->pending_int &= ~INTERRUPT_EXT; env->pending_int &= ~INTERRUPT_TOD; } else if (env->pending_int & INTERRUPT_CPUTIMER) { cpu_inject_ext(cpu, 0x1005, 0, 0); - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; env->pending_int &= ~INTERRUPT_EXT; env->pending_int &= ~INTERRUPT_TOD; } } /* handle I/O interrupts */ if ((env->psw.mask & PSW_MASK_IO) && - (env->exception_index == -1)) { + (cs->exception_index == -1)) { if (env->pending_int & INTERRUPT_IO) { - env->exception_index = EXCP_IO; + cs->exception_index = EXCP_IO; } } - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_PGM: do_program_interrupt(env); break; @@ -802,7 +810,7 @@ void s390_cpu_do_interrupt(CPUState *cs) do_mchk_interrupt(env); break; } - env->exception_index = -1; + cs->exception_index = -1; if (!env->pending_int) { cs->interrupt_request &= ~CPU_INTERRUPT_HARD; diff --git a/target-s390x/int_helper.c b/target-s390x/int_helper.c index 85e49aa..6a929ca 100644 --- a/target-s390x/int_helper.c +++ b/target-s390x/int_helper.c @@ -106,9 +106,10 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, runtime_exception(env, PGM_FIXPT_DIVIDE, GETPC()); } #else + S390CPU *cpu = s390_env_get_cpu(env); /* 32-bit hosts would need special wrapper functionality - just abort if we encounter such a case; it's very unlikely anyways. */ - cpu_abort(env, "128 -> 64/64 division not implemented\n"); + cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n"); #endif } return ret; diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 875ea95..d8ca300 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -44,18 +44,18 @@ NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -72,6 +72,7 @@ void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx, static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, uint8_t byte) { + S390CPU *cpu = s390_env_get_cpu(env); hwaddr dest_phys; hwaddr len = l; void *dest_p; @@ -80,7 +81,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) { cpu_stb_data(env, dest, byte); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } dest_phys |= dest & ~TARGET_PAGE_MASK; @@ -94,6 +95,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) { + S390CPU *cpu = s390_env_get_cpu(env); hwaddr dest_phys; hwaddr src_phys; hwaddr len = l; @@ -104,13 +106,13 @@ static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest, if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) { cpu_stb_data(env, dest, 0); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } dest_phys |= dest & ~TARGET_PAGE_MASK; if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) { cpu_ldub_data(env, src); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } src_phys |= src & ~TARGET_PAGE_MASK; @@ -483,6 +485,7 @@ static uint32_t helper_icm(CPUS390XState *env, uint32_t r1, uint64_t address, uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret) { + S390CPU *cpu = s390_env_get_cpu(env); uint16_t insn = cpu_lduw_code(env, addr); HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr, @@ -534,7 +537,7 @@ uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, cc = helper_icm(env, r1, get_address(env, 0, b2, d2), r3); } else { abort: - cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n", + cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implemented\n", insn); } return cc; @@ -807,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array, #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { + S390CPU *cpu = s390_env_get_cpu(env); int i; uint64_t src = a2; @@ -821,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { + S390CPU *cpu = s390_env_get_cpu(env); int i; uint64_t src = a2; @@ -839,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) @@ -932,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) /* compare and swap and purge */ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2) { + S390CPU *cpu = s390_env_get_cpu(env); uint32_t cc; uint32_t o1 = env->regs[r1]; uint64_t a2 = r2 & ~3ULL; @@ -941,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2) cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]); if (r2 & 0x3) { /* flush TLB / ALB */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } cc = 0; } else { @@ -955,7 +961,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2) static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2, uint64_t mode2) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(s390_env_get_cpu(env)); target_ulong src, dest; int flags, cc = 0, i; @@ -968,12 +974,12 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1, } if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } dest |= a1 & ~TARGET_PAGE_MASK; if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } src |= a2 & ~TARGET_PAGE_MASK; @@ -1010,7 +1016,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2) /* invalidate pte */ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(s390_env_get_cpu(env)); uint64_t page = vaddr & TARGET_PAGE_MASK; uint64_t pte = 0; @@ -1024,34 +1030,38 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr) /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ - tlb_flush_page(env, page); + tlb_flush_page(cs, page); /* XXX 31-bit hack */ if (page & 0x80000000) { - tlb_flush_page(env, page & ~0x80000000); + tlb_flush_page(cs, page & ~0x80000000); } else { - tlb_flush_page(env, page | 0x80000000); + tlb_flush_page(cs, page | 0x80000000); } } /* flush local tlb */ void HELPER(ptlb)(CPUS390XState *env) { - tlb_flush(env, 1); + S390CPU *cpu = s390_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } /* store using real address */ void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(s390_env_get_cpu(env)); + stw_phys(cs->as, get_address(env, 0, 0, addr), (uint32_t)v1); } /* load real address */ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) { + CPUState *cs = CPU(s390_env_get_cpu(env)); uint32_t cc = 0; - int old_exc = env->exception_index; + int old_exc = cs->exception_index; uint64_t asc = env->psw.mask & PSW_MASK_ASC; uint64_t ret; int flags; @@ -1061,16 +1071,16 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) program_interrupt(env, PGM_SPECIAL_OP, 2); } - env->exception_index = old_exc; + cs->exception_index = old_exc; if (mmu_translate(env, addr, 0, asc, &ret, &flags)) { cc = 3; } - if (env->exception_index == EXCP_PGM) { + if (cs->exception_index == EXCP_PGM) { ret = env->int_pgm_code | 0x80000000; } else { ret |= addr & ~TARGET_PAGE_MASK; } - env->exception_index = old_exc; + cs->exception_index = old_exc; env->cc_op = cc; return ret; diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 728456f..294b3ed 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -47,46 +47,53 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, uintptr_t retaddr) { + CPUState *cs = CPU(s390_env_get_cpu(env)); int t; - env->exception_index = EXCP_PGM; + cs->exception_index = EXCP_PGM; env->int_pgm_code = excp; /* Use the (ultimate) callers address to find the insn that trapped. */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); /* Advance past the insn. */ t = cpu_ldub_code(env, env->psw.addr); env->int_pgm_ilen = t = get_ilen(t); env->psw.addr += 2 * t; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* Raise an exception statically from a TB. */ void HELPER(exception)(CPUS390XState *env, uint32_t excp) { + CPUState *cs = CPU(s390_env_get_cpu(env)); + HELPER_LOG("%s: exception %d\n", __func__, excp); - env->exception_index = excp; - cpu_loop_exit(env); + cs->exception_index = excp; + cpu_loop_exit(cs); } #ifndef CONFIG_USER_ONLY void program_interrupt(CPUS390XState *env, uint32_t code, int ilen) { + S390CPU *cpu = s390_env_get_cpu(env); + qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", env->psw.addr); if (kvm_enabled()) { #ifdef CONFIG_KVM - kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code); + kvm_s390_interrupt(cpu, KVM_S390_PROGRAM_INT, code); #endif } else { + CPUState *cs = CPU(cpu); + env->int_pgm_code = code; env->int_pgm_ilen = ilen; - env->exception_index = EXCP_PGM; - cpu_loop_exit(env); + cs->exception_index = EXCP_PGM; + cpu_loop_exit(cs); } } @@ -230,11 +237,13 @@ uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem, /* Set Prefix */ void HELPER(spx)(CPUS390XState *env, uint64_t a1) { + CPUState *cs = CPU(s390_env_get_cpu(env)); uint32_t prefix = a1 & 0x7fffe000; + env->psa = prefix; qemu_log("prefix: %#x\n", prefix); - tlb_flush_page(env, 0); - tlb_flush_page(env, TARGET_PAGE_SIZE); + tlb_flush_page(cs, 0); + tlb_flush_page(cs, TARGET_PAGE_SIZE); } static inline uint64_t clock_value(CPUS390XState *env) @@ -449,11 +458,11 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, #if !defined(CONFIG_USER_ONLY) case SIGP_RESTART: qemu_system_reset_request(); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); break; case SIGP_STOP: qemu_system_shutdown_request(); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); break; #endif default: diff --git a/target-s390x/translate.c b/target-s390x/translate.c index bc99a37..81b7e33 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -4795,8 +4795,8 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, } status = NO_EXIT; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc.pc) { status = EXIT_PC_STALE; do_debug = true; diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index c23294d..e7f0521 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -39,6 +39,11 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.flags = tb->flags; } +static bool superh_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + /* CPUClass::reset() */ static void superh_cpu_reset(CPUState *s) { @@ -48,8 +53,8 @@ static void superh_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSH4State, breakpoints)); - tlb_flush(env, 1); + memset(env, 0, offsetof(CPUSH4State, id)); + tlb_flush(s, 1); env->pc = 0xA0000000; #if defined(CONFIG_USER_ONLY) @@ -143,18 +148,7 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) SuperHCPU *cpu_sh4_init(const char *cpu_model) { - SuperHCPU *cpu; - ObjectClass *oc; - - oc = superh_cpu_class_by_name(cpu_model); - if (oc == NULL) { - return NULL; - } - cpu = SUPERH_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); } static void sh7750r_cpu_initfn(Object *obj) @@ -280,13 +274,16 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->reset = superh_cpu_reset; cc->class_by_name = superh_cpu_class_by_name; + cc->has_work = superh_cpu_has_work; cc->do_interrupt = superh_cpu_do_interrupt; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; cc->gdb_read_register = superh_cpu_gdb_read_register; cc->gdb_write_register = superh_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = superh_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_sh_cpu; diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index c181dda..a2e9e2c 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -175,6 +175,7 @@ typedef struct CPUSH4State { CPU_COMMON + /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ /* The features that we should emulate. See sh_features above. */ @@ -193,9 +194,8 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model); int cpu_sh4_exec(CPUSH4State * s); int cpu_sh4_signal_handler(int host_signum, void *pinfo, void *puc); -int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, - int mmu_idx); -#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault +int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); #if !defined(CONFIG_USER_ONLY) @@ -352,11 +352,6 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ } -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - #include "exec/exec-all.h" #endif /* _CPU_SH4_H */ diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 9ac2825..9ebdd5c 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -33,26 +33,26 @@ void superh_cpu_do_interrupt(CPUState *cs) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } -int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, - int mmu_idx) +int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + env->tea = address; - env->exception_index = -1; + cs->exception_index = -1; switch (rw) { case 0: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case 1: - env->exception_index = 0x0c0; + cs->exception_index = 0x0c0; break; case 2: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; } return 1; @@ -86,16 +86,16 @@ void superh_cpu_do_interrupt(CPUState *cs) SuperHCPU *cpu = SUPERH_CPU(cs); CPUSH4State *env = &cpu->env; int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; - int do_exp, irq_vector = env->exception_index; + int do_exp, irq_vector = cs->exception_index; /* prioritize exceptions over interrupts */ - do_exp = env->exception_index != -1; - do_irq = do_irq && (env->exception_index == -1); + do_exp = cs->exception_index != -1; + do_irq = do_irq && (cs->exception_index == -1); if (env->sr & SR_BL) { - if (do_exp && env->exception_index != 0x1e0) { - env->exception_index = 0x000; /* masked exception -> reset */ + if (do_exp && cs->exception_index != 0x1e0) { + cs->exception_index = 0x000; /* masked exception -> reset */ } if (do_irq && !env->in_sleep) { return; /* masked */ @@ -113,7 +113,7 @@ void superh_cpu_do_interrupt(CPUState *cs) if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *expname; - switch (env->exception_index) { + switch (cs->exception_index) { case 0x0e0: expname = "addr_error"; break; @@ -177,8 +177,8 @@ void superh_cpu_do_interrupt(CPUState *cs) env->flags = 0; if (do_exp) { - env->expevt = env->exception_index; - switch (env->exception_index) { + env->expevt = cs->exception_index; + switch (cs->exception_index) { case 0x000: case 0x020: case 0x140: @@ -234,15 +234,21 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb) static int itlb_replacement(CPUSH4State * env) { - if ((env->mmucr & 0xe0000000) == 0xe0000000) + SuperHCPU *cpu = sh_env_get_cpu(env); + + if ((env->mmucr & 0xe0000000) == 0xe0000000) { return 0; - if ((env->mmucr & 0x98000000) == 0x18000000) + } + if ((env->mmucr & 0x98000000) == 0x18000000) { return 1; - if ((env->mmucr & 0x54000000) == 0x04000000) + } + if ((env->mmucr & 0x54000000) == 0x04000000) { return 2; - if ((env->mmucr & 0x2c000000) == 0x00000000) + } + if ((env->mmucr & 0x2c000000) == 0x00000000) { return 3; - cpu_abort(env, "Unhandled itlb_replacement"); + } + cpu_abort(CPU(cpu), "Unhandled itlb_replacement"); } /* Find the corresponding entry in the right TLB @@ -298,7 +304,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) itlb = itlb_replacement(env); ientry = &env->itlb[itlb]; if (ientry->v) { - tlb_flush_page(env, ientry->vpn << 10); + tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10); } *ientry = env->utlb[utlb]; update_itlb_use(env, itlb); @@ -447,9 +453,11 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical, return get_mmu_address(env, physical, prot, address, rw, access_type); } -int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, - int mmu_idx) +int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) { + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; target_ulong physical; int prot, ret, access_type; @@ -467,36 +475,36 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, switch (ret) { case MMU_ITLB_MISS: case MMU_DTLB_MISS_READ: - env->exception_index = 0x040; + cs->exception_index = 0x040; break; case MMU_DTLB_MULTIPLE: case MMU_ITLB_MULTIPLE: - env->exception_index = 0x140; + cs->exception_index = 0x140; break; case MMU_ITLB_VIOLATION: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case MMU_DTLB_MISS_WRITE: - env->exception_index = 0x060; + cs->exception_index = 0x060; break; case MMU_DTLB_INITIAL_WRITE: - env->exception_index = 0x080; + cs->exception_index = 0x080; break; case MMU_DTLB_VIOLATION_READ: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case MMU_DTLB_VIOLATION_WRITE: - env->exception_index = 0x0c0; + cs->exception_index = 0x0c0; break; case MMU_IADDR_ERROR: case MMU_DADDR_ERROR_READ: - env->exception_index = 0x0e0; + cs->exception_index = 0x0e0; break; case MMU_DADDR_ERROR_WRITE: - env->exception_index = 0x100; + cs->exception_index = 0x100; break; default: - cpu_abort(env, "Unhandled MMU fault"); + cpu_abort(cs, "Unhandled MMU fault"); } return 1; } @@ -504,7 +512,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, address &= TARGET_PAGE_MASK; physical &= TARGET_PAGE_MASK; - tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } @@ -520,13 +528,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void cpu_load_tlb(CPUSH4State * env) { + SuperHCPU *cpu = sh_env_get_cpu(env); int n = cpu_mmucr_urc(env->mmucr); tlb_t * entry = &env->utlb[n]; if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(env, address); + tlb_flush_page(CPU(cpu), address); } /* Take values into cpu status from registers. */ @@ -549,7 +558,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->size = 1024 * 1024; /* 1M */ break; default: - cpu_abort(env, "Unhandled load_tlb"); + cpu_abort(CPU(cpu), "Unhandled load_tlb"); break; } entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); @@ -576,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->v = 0; } - tlb_flush(s, 1); + tlb_flush(CPU(sh_env_get_cpu(s)), 1); } uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, @@ -602,7 +611,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in itlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->asid = asid; entry->vpn = vpn; @@ -644,7 +653,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; @@ -697,8 +706,10 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, if (entry->vpn == vpn && (!use_asid || entry->asid == asid || entry->sh)) { if (utlb_match_entry) { + CPUState *cs = CPU(sh_env_get_cpu(s)); + /* Multiple TLB Exception */ - s->exception_index = 0x140; + cs->exception_index = 0x140; s->tea = addr; break; } @@ -726,16 +737,19 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, } } - if (needs_tlb_flush) - tlb_flush_page(s, vpn << 10); + if (needs_tlb_flush) { + tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); + } } else { int index = (addr & 0x00003f00) >> 8; tlb_t * entry = &s->utlb[index]; if (entry->v) { + CPUState *cs = CPU(sh_env_get_cpu(s)); + /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(cs, address); } entry->asid = asid; entry->vpn = vpn; @@ -786,7 +800,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index e955e81..720a97b 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -38,18 +38,18 @@ #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { /* now we have a real cpu fault */ if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -58,8 +58,10 @@ void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx, void helper_ldtlb(CPUSH4State *env) { #ifdef CONFIG_USER_ONLY + SuperHCPU *cpu = sh_env_get_cpu(env); + /* XXXXX */ - cpu_abort(env, "Unhandled ldtlb"); + cpu_abort(CPU(cpu), "Unhandled ldtlb"); #else cpu_load_tlb(env); #endif @@ -68,11 +70,13 @@ void helper_ldtlb(CPUSH4State *env) static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, uintptr_t retaddr) { - env->exception_index = index; + CPUState *cs = CPU(sh_env_get_cpu(env)); + + cs->exception_index = index; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_illegal_instruction(CPUSH4State *env) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 661fc6c..2360609 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1889,8 +1889,8 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, max_insns = CF_COUNT_MASK; gen_tb_start(); while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { /* We have hit a breakpoint - make sure PC is up-to-date */ tcg_gen_movi_i32(cpu_pc, ctx.pc); diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index e7f878e..d9f37e9 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -18,6 +18,7 @@ */ #include "cpu.h" +#include "qemu/error-report.h" //#define DEBUG_FEATURES @@ -32,8 +33,8 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSPARCState, breakpoints)); - tlb_flush(env, 1); + memset(env, 0, offsetof(CPUSPARCState, version)); + tlb_flush(s, 1); env->cwp = 0; #ifndef TARGET_SPARC64 env->wim = 1; @@ -69,21 +70,32 @@ static void sparc_cpu_reset(CPUState *s) env->cache_control = 0; } -static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) +static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model) { + CPUClass *cc = CPU_GET_CLASS(cpu); + CPUSPARCState *env = &cpu->env; + char *s = g_strdup(cpu_model); + char *featurestr, *name = strtok(s, ","); sparc_def_t def1, *def = &def1; + Error *err = NULL; - if (cpu_sparc_find_by_name(def, cpu_model) < 0) { + if (cpu_sparc_find_by_name(def, name) < 0) { + g_free(s); return -1; } env->def = g_new0(sparc_def_t, 1); memcpy(env->def, def, sizeof(*def)); -#if defined(CONFIG_USER_ONLY) - if ((env->def->features & CPU_FEATURE_FLOAT)) { - env->def->features |= CPU_FEATURE_FLOAT128; + + featurestr = strtok(NULL, ","); + cc->parse_features(CPU(cpu), featurestr, &err); + g_free(s); + if (err) { + error_report("%s", error_get_pretty(err)); + error_free(err); + return -1; } -#endif + env->version = def->iu_version; env->fsr = def->fpu_version; env->nwindows = def->nwindows; @@ -103,12 +115,10 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) SPARCCPU *cpu_sparc_init(const char *cpu_model) { SPARCCPU *cpu; - CPUSPARCState *env; cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU)); - env = &cpu->env; - if (cpu_sparc_register(env, cpu_model) < 0) { + if (cpu_sparc_register(cpu, cpu_model) < 0) { object_unref(OBJECT(cpu)); return NULL; } @@ -458,7 +468,8 @@ static const sparc_def_t sparc_defs[] = { .mmu_trcr_mask = 0xffffffff, .nwindows = 8, .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | - CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN, + CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | + CPU_FEATURE_CASA, }, #endif }; @@ -505,19 +516,13 @@ static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) return; } } - fprintf(stderr, "CPU feature %s not found\n", flagname); + error_report("CPU feature %s not found", flagname); } -static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) +static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *name) { unsigned int i; const sparc_def_t *def = NULL; - char *s = g_strdup(cpu_model); - char *featurestr, *name = strtok(s, ","); - uint32_t plus_features = 0; - uint32_t minus_features = 0; - uint64_t iu_version; - uint32_t fpu_version, mmu_version, nwindows; for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { if (strcasecmp(name, sparc_defs[i].name) == 0) { @@ -525,11 +530,24 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) } } if (!def) { - goto error; + return -1; } memcpy(cpu_def, def, sizeof(*def)); + return 0; +} - featurestr = strtok(NULL, ","); +static void sparc_cpu_parse_features(CPUState *cs, char *features, + Error **errp) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + sparc_def_t *cpu_def = cpu->env.def; + char *featurestr; + uint32_t plus_features = 0; + uint32_t minus_features = 0; + uint64_t iu_version; + uint32_t fpu_version, mmu_version, nwindows; + + featurestr = features ? strtok(features, ",") : NULL; while (featurestr) { char *val; @@ -544,8 +562,8 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) iu_version = strtoll(val, &err, 0); if (!*val || *err) { - fprintf(stderr, "bad numerical value %s\n", val); - goto error; + error_setg(errp, "bad numerical value %s", val); + return; } cpu_def->iu_version = iu_version; #ifdef DEBUG_FEATURES @@ -556,8 +574,8 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) fpu_version = strtol(val, &err, 0); if (!*val || *err) { - fprintf(stderr, "bad numerical value %s\n", val); - goto error; + error_setg(errp, "bad numerical value %s", val); + return; } cpu_def->fpu_version = fpu_version; #ifdef DEBUG_FEATURES @@ -568,8 +586,8 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) mmu_version = strtol(val, &err, 0); if (!*val || *err) { - fprintf(stderr, "bad numerical value %s\n", val); - goto error; + error_setg(errp, "bad numerical value %s", val); + return; } cpu_def->mmu_version = mmu_version; #ifdef DEBUG_FEATURES @@ -581,21 +599,21 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) nwindows = strtol(val, &err, 0); if (!*val || *err || nwindows > MAX_NWINDOWS || nwindows < MIN_NWINDOWS) { - fprintf(stderr, "bad numerical value %s\n", val); - goto error; + error_setg(errp, "bad numerical value %s", val); + return; } cpu_def->nwindows = nwindows; #ifdef DEBUG_FEATURES fprintf(stderr, "nwindows %d\n", nwindows); #endif } else { - fprintf(stderr, "unrecognized feature %s\n", featurestr); - goto error; + error_setg(errp, "unrecognized feature %s", featurestr); + return; } } else { - fprintf(stderr, "feature string `%s' not in format " - "(+feature|-feature|feature=xyz)\n", featurestr); - goto error; + error_setg(errp, "feature string `%s' not in format " + "(+feature|-feature|feature=xyz)", featurestr); + return; } featurestr = strtok(NULL, ","); } @@ -604,12 +622,6 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) #ifdef DEBUG_FEATURES print_features(stderr, fprintf, cpu_def->features, NULL); #endif - g_free(s); - return 0; - - error: - g_free(s); - return -1; } void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf) @@ -738,9 +750,26 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.npc = tb->cs_base; } +static bool sparc_cpu_has_work(CPUState *cs) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + + return (cs->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_interrupts_enabled(env); +} + static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) { SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); +#if defined(CONFIG_USER_ONLY) + SPARCCPU *cpu = SPARC_CPU(dev); + CPUSPARCState *env = &cpu->env; + + if ((env->def->features & CPU_FEATURE_FLOAT)) { + env->def->features |= CPU_FEATURE_FLOAT128; + } +#endif qemu_init_vcpu(CPU(dev)); @@ -781,6 +810,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) scc->parent_reset = cc->reset; cc->reset = sparc_cpu_reset; + cc->parse_features = sparc_cpu_parse_features; + cc->has_work = sparc_cpu_has_work; cc->do_interrupt = sparc_cpu_do_interrupt; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) @@ -790,7 +821,9 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; cc->gdb_read_register = sparc_cpu_gdb_read_register; cc->gdb_write_register = sparc_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault; +#else cc->do_unassigned_access = sparc_cpu_unassigned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; #endif diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index c519063..f72451d 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -271,6 +271,7 @@ typedef struct sparc_def_t { #define CPU_FEATURE_ASR17 (1 << 15) #define CPU_FEATURE_CACHE_CTRL (1 << 16) #define CPU_FEATURE_POWERDOWN (1 << 17) +#define CPU_FEATURE_CASA (1 << 18) #ifndef TARGET_SPARC64 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ @@ -282,7 +283,8 @@ typedef struct sparc_def_t { CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ - CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) + CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ + CPU_FEATURE_CASA) enum { mmu_us_12, // Ultrasparc < III (64 entry TLB) mmu_us_3, // Ultrasparc III (512 entry TLB) @@ -421,6 +423,7 @@ struct CPUSPARCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; @@ -519,9 +522,8 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model); void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); /* mmu_helper.c */ -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); @@ -747,15 +749,6 @@ static inline bool tb_am_enabled(int tb_flags) #endif } -static inline bool cpu_has_work(CPUState *cpu) -{ - SPARCCPU *sparc_cpu = SPARC_CPU(cpu); - CPUSPARCState *env1 = &sparc_cpu->env; - - return (cpu->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_interrupts_enabled(env1); -} - #include "exec/exec-all.h" #endif diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 57c20af..f3c7fbf 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -24,14 +24,18 @@ void helper_raise_exception(CPUSPARCState *env, int tt) { - env->exception_index = tt; - cpu_loop_exit(env); + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = tt; + cpu_loop_exit(cs); } void helper_debug(CPUSPARCState *env) { - env->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); } #ifdef TARGET_SPARC64 @@ -67,6 +71,7 @@ void helper_tick_set_limit(void *opaque, uint64_t limit) static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, target_ulong b, int cc) { + SPARCCPU *cpu = sparc_env_get_cpu(env); int overflow = 0; uint64_t x0; uint32_t x1; @@ -75,7 +80,7 @@ static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, x1 = (b & 0xffffffff); if (x1 == 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } @@ -106,6 +111,7 @@ target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b) static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, target_ulong b, int cc) { + SPARCCPU *cpu = sparc_env_get_cpu(env); int overflow = 0; int64_t x0; int32_t x1; @@ -114,7 +120,7 @@ static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, x1 = (b & 0xffffffff); if (x1 == 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } @@ -147,7 +153,9 @@ int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b) { if (b == 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu = sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } else if (b == -1) { /* Avoid overflow trap with i386 divide insn. */ @@ -161,7 +169,9 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) { if (b == 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu = sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } return a / b; @@ -171,6 +181,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu = sparc_env_get_cpu(env); target_ulong dst; /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -193,13 +204,14 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, return dst; tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu = sparc_env_get_cpu(env); target_ulong dst; /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -222,7 +234,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, return dst; tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } @@ -232,9 +244,9 @@ void helper_power_down(CPUSPARCState *env) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; env->pc = env->npc; env->npc = env->pc + 4; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #endif diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 2a771b2..cd8d3fa 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -22,7 +22,6 @@ DEF_HELPER_1(popc, tl, tl) DEF_HELPER_4(ldda_asi, void, env, tl, int, int) DEF_HELPER_5(ldf_asi, void, env, tl, int, int, int) DEF_HELPER_5(stf_asi, void, env, tl, int, int, int) -DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32) DEF_HELPER_5(casx_asi, tl, env, tl, tl, tl, i32) DEF_HELPER_2(set_softint, void, env, i64) DEF_HELPER_2(clear_softint, void, env, i64) @@ -31,6 +30,9 @@ DEF_HELPER_2(tick_set_count, void, ptr, i64) DEF_HELPER_1(tick_get_count, i64, ptr) DEF_HELPER_2(tick_set_limit, void, ptr, i64) #endif +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32) +#endif DEF_HELPER_3(check_align, void, env, tl, i32) DEF_HELPER_1(debug, void, env) DEF_HELPER_1(save, void, env) diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index d532238..7c380ba 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -62,7 +62,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int cwp, intno = env->exception_index; + int cwp, intno = cs->exception_index; /* Compute PSR before exposing state. */ if (env->cc_op != CC_OP_FLAGS) { @@ -105,12 +105,12 @@ void sparc_cpu_do_interrupt(CPUState *cs) #endif #if !defined(CONFIG_USER_ONLY) if (env->psret == 0) { - if (env->exception_index == 0x80 && + if (cs->exception_index == 0x80 && env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { - cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", - env->exception_index); + cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state", + cs->exception_index); } return; } @@ -125,7 +125,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) /* IRQ acknowledgment */ diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index bf7dd86..bf24232 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -63,7 +63,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int intno = env->exception_index; + int intno = cs->exception_index; trap_state *tsptr; /* Compute PSR before exposing state. */ @@ -111,8 +111,8 @@ void sparc_cpu_do_interrupt(CPUState *cs) #endif #if !defined(CONFIG_USER_ONLY) if (env->tl >= env->maxtl) { - cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," - " Error state", env->exception_index, env->tl, env->maxtl); + cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," + " Error state", cs->exception_index, env->tl, env->maxtl); return; } #endif @@ -160,7 +160,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; } trap_state *cpu_tsptr(CPUSPARCState* env) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 92761ad..ec14802 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -141,6 +141,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb, /* flush page range if translation is valid */ if (TTE_IS_VALID(tlb->tte)) { + CPUState *cs = CPU(sparc_env_get_cpu(env1)); mask = 0xffffffffffffe000ULL; mask <<= 3 * ((tlb->tte >> 61) & 3); @@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb, va = tlb->tag & mask; for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { - tlb_flush_page(env1, va + offset); + tlb_flush_page(cs, va + offset); } } @@ -447,7 +448,7 @@ static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, int sign) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(sparc_env_get_cpu(env)); uint64_t ret = 0; #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) uint32_t last_addr = addr; @@ -584,6 +585,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, } break; case 0xb: /* Supervisor data access */ + case 0x80: switch (size) { case 1: ret = cpu_ldub_kernel(env, addr); @@ -687,8 +689,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, break; case 8: /* User code access, XXX */ default: - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), - addr, false, false, asi, size); + cpu_unassigned_access(cs, addr, false, false, asi, size); ret = 0; break; } @@ -716,7 +717,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, int size) { - CPUState *cs = ENV_GET_CPU(env); + SPARCCPU *cpu = sparc_env_get_cpu(env); + CPUState *cs = CPU(cpu); + helper_check_align(env, addr, size - 1); switch (asi) { case 2: /* SuperSparc MXCC registers and Leon3 cache control */ @@ -862,13 +865,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, DPRINTF_MMU("mmu flush level %d\n", mmulev); switch (mmulev) { case 0: /* flush page */ - tlb_flush_page(env, addr & 0xfffff000); + tlb_flush_page(CPU(cpu), addr & 0xfffff000); break; case 1: /* flush segment (256k) */ case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; default: break; @@ -893,7 +896,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, disabled mode are invalid in normal mode */ if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) != (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 1: /* Context Table Pointer Register */ @@ -904,7 +907,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, if (oldreg != env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -955,6 +958,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, } break; case 0xb: /* Supervisor data access */ + case 0x80: switch (size) { case 1: cpu_stb_kernel(env, addr, val); @@ -1290,7 +1294,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, int sign) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(sparc_env_get_cpu(env)); uint64_t ret = 0; #if defined(DEBUG_ASI) target_ulong last_addr = addr; @@ -1324,7 +1328,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, dump_asi("read ", last_addr, asi, size, ret); #endif /* env->exception_index is set in get_physical_address_data(). */ - helper_raise_exception(env, env->exception_index); + helper_raise_exception(env, cs->exception_index); } /* convert nonfaulting load ASIs to normal load ASIs */ @@ -1603,8 +1607,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, case 0x5f: /* D-MMU demap, WO */ case 0x77: /* Interrupt vector, WO */ default: - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), - addr, false, false, 1, size); + cpu_unassigned_access(cs, addr, false, false, 1, size); ret = 0; break; } @@ -1660,7 +1663,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, int asi, int size) { - CPUState *cs = ENV_GET_CPU(env); + SPARCCPU *cpu = sparc_env_get_cpu(env); + CPUState *cs = CPU(cpu); + #ifdef DEBUG_ASI dump_asi("write", addr, asi, size, val); #endif @@ -1869,7 +1874,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, #ifdef DEBUG_MMU dump_mmu(stdout, fprintf, env); #endif - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } return; } @@ -1958,13 +1963,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.mmu_primary_context = val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context = val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -2038,8 +2043,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case 0x8a: /* Primary no-fault LE, RO */ case 0x8b: /* Secondary no-fault LE, RO */ default: - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), - addr, true, false, 1, size); + cpu_unassigned_access(cs, addr, true, false, 1, size); return; } } @@ -2232,33 +2236,35 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, } } -target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, - target_ulong val1, target_ulong val2, uint32_t asi) +target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, + target_ulong val1, target_ulong val2, + uint32_t asi) { target_ulong ret; - val2 &= 0xffffffffUL; - ret = helper_ld_asi(env, addr, asi, 4, 0); - ret &= 0xffffffffUL; + ret = helper_ld_asi(env, addr, asi, 8, 0); if (val2 == ret) { - helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); + helper_st_asi(env, addr, val1, asi, 8); } return ret; } +#endif /* TARGET_SPARC64 */ -target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, - target_ulong val1, target_ulong val2, - uint32_t asi) +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, + target_ulong val1, target_ulong val2, uint32_t asi) { target_ulong ret; - ret = helper_ld_asi(env, addr, asi, 8, 0); + val2 &= 0xffffffffUL; + ret = helper_ld_asi(env, addr, asi, 4, 0); + ret &= 0xffffffffUL; if (val2 == ret) { - helper_st_asi(env, addr, val1, asi, 8); + helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); } return ret; } -#endif /* TARGET_SPARC64 */ +#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */ void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx) { @@ -2393,7 +2399,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, /* flush neverland mappings created during no-fault mode, so the sequential MMU faults report proper fault types */ if (env->mmuregs[0] & MMU_NF) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } } #else @@ -2423,12 +2429,13 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + SPARCCPU *cpu = sparc_env_get_cpu(env); #ifdef DEBUG_UNALIGNED printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx "\n", addr, env->pc); #endif if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); } helper_raise_exception(env, TT_UNALIGNED); } @@ -2437,17 +2444,17 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-sparc/machine.c b/target-sparc/machine.c index a353dab..3f3de4c 100644 --- a/target-sparc/machine.c +++ b/target-sparc/machine.c @@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque) int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUSPARCState *env = opaque; + SPARCCPU *cpu = sparc_env_get_cpu(env); int i; uint32_t tmp; @@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be64s(f, &env->ssr); cpu_get_timer(f, env->hstick); #endif - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return 0; } diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 5fc2fd6..61afbcf 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -25,13 +25,13 @@ #if defined(CONFIG_USER_ONLY) -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { if (rw & 2) { - env1->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - env1->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -86,7 +86,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, uint32_t pde; int error_code = 0, is_dirty, is_user; unsigned long page_offset; - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(sparc_env_get_cpu(env)); is_user = mmu_idx == MMU_USER_IDX; @@ -198,9 +198,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, } /* Perform address translation */ -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; hwaddr paddr; target_ulong vaddr; target_ulong page_size; @@ -212,10 +214,10 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, vaddr = address; if (error_code == 0) { #ifdef DEBUG_MMU - printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " + printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", address, paddr, vaddr); #endif - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; } @@ -231,13 +233,13 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } else { if (rw & 2) { - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -245,7 +247,7 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(sparc_env_get_cpu(env)); hwaddr pde_ptr; uint32_t pde; @@ -487,6 +489,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; uint64_t sfsr = 0; @@ -551,10 +554,10 @@ static int get_physical_address_data(CPUSPARCState *env, if (do_fault) { /* faults above are reported with TT_DFAULT. */ - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { do_fault = 1; - env->exception_index = TT_DPROT; + cs->exception_index = TT_DPROT; trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); } @@ -598,7 +601,7 @@ static int get_physical_address_data(CPUSPARCState *env, * - JPS1: SFAR updated and some fields of SFSR updated */ env->dmmu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_DMISS; + cs->exception_index = TT_DMISS; return 1; } @@ -606,6 +609,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; @@ -649,7 +653,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* FIXME: ASI field in SFSR must be set */ env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; env->immu.tag_access = (address & ~0x1fffULL) | context; @@ -667,7 +671,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */ env->immu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_TMISS; + cs->exception_index = TT_TMISS; return 1; } @@ -705,9 +709,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, } /* Perform address translation */ -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; target_ulong vaddr; hwaddr paddr; target_ulong page_size; @@ -723,7 +729,7 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; } /* XXX */ diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6150b22..2de1c4a 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2107,18 +2107,6 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, tcg_temp_free_i64(t64); } -static inline void gen_cas_asi(DisasContext *dc, TCGv addr, - TCGv val2, int insn, int rd) -{ - TCGv val1 = gen_load_gpr(dc, rd); - TCGv dst = gen_dest_gpr(dc, rd); - TCGv_i32 r_asi = gen_get_asi(insn, addr); - - gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); - tcg_temp_free_i32(r_asi); - gen_store_gpr(dc, rd, dst); -} - static inline void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2, int insn, int rd) { @@ -2229,6 +2217,22 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, #endif #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +static inline void gen_cas_asi(DisasContext *dc, TCGv addr, + TCGv val2, int insn, int rd) +{ + TCGv val1 = gen_load_gpr(dc, rd); + TCGv dst = gen_dest_gpr(dc, rd); +#ifdef TARGET_SPARC64 + TCGv_i32 r_asi = gen_get_asi(insn, addr); +#else + TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); +#endif + + gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); + tcg_temp_free_i32(r_asi); + gen_store_gpr(dc, rd, dst); +} + static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) { TCGv_i64 r_val; @@ -5103,11 +5107,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) } gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); break; - case 0x3c: /* V9 casa */ - rs2 = GET_FIELD(insn, 27, 31); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); - break; case 0x3e: /* V9 casxa */ rs2 = GET_FIELD(insn, 27, 31); cpu_src2 = gen_load_gpr(dc, rs2); @@ -5120,6 +5119,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x37: /* stdc */ goto ncp_insn; #endif +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) + case 0x3c: /* V9 or LEON3 casa */ +#ifndef TARGET_SPARC64 + CHECK_IU_FEATURE(dc, CASA); + if (IS_IMM) { + goto illegal_insn; + } + if (!supervisor(dc)) { + goto priv_insn; + } +#endif + rs2 = GET_FIELD(insn, 27, 31); + cpu_src2 = gen_load_gpr(dc, rs2); + gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); + break; +#endif default: goto illegal_insn; } @@ -5255,8 +5270,8 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, max_insns = CF_COUNT_MASK; gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc); diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 3f78208..2d2c429 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -23,6 +23,12 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.regs[31] = value; } +static bool uc32_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); +} + static inline void set_feature(CPUUniCore32State *env, int feature) { env->features |= feature; @@ -115,7 +121,7 @@ static void uc32_cpu_initfn(Object *obj) env->regs[31] = 0x03000000; #endif - tlb_flush(env, 1); + tlb_flush(cs, 1); if (tcg_enabled() && !inited) { inited = true; @@ -138,10 +144,13 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) dc->realize = uc32_cpu_realizefn; cc->class_by_name = uc32_cpu_class_by_name; + cc->has_work = uc32_cpu_has_work; cc->do_interrupt = uc32_cpu_do_interrupt; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_uc32_cpu; diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 967511e..50972f9 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -125,13 +125,10 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask) #define cpu_init uc32_cpu_init #define cpu_exec uc32_cpu_exec #define cpu_signal_handler uc32_cpu_signal_handler -#define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault CPUUniCore32State *uc32_cpu_init(const char *cpu_model); int uc32_cpu_exec(CPUUniCore32State *s); int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc); -int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw, - int mmu_idx); /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel @@ -157,13 +154,9 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc } } +int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & - (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); -} - #endif /* QEMU_UNICORE32_CPU_H */ diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index 9bf4fea..169c85c 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -28,19 +28,12 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model) { UniCore32CPU *cpu; - CPUUniCore32State *env; - ObjectClass *oc; - oc = cpu_class_by_name(TYPE_UNICORE32_CPU, cpu_model); - if (oc == NULL) { + cpu = UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)); + if (cpu == NULL) { return NULL; } - cpu = UNICORE32_CPU(object_new(object_class_get_name(oc))); - env = &cpu->env; - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return env; + return &cpu->env; } uint32_t HELPER(clo)(uint32_t x) @@ -57,6 +50,8 @@ uint32_t HELPER(clz)(uint32_t x) void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + /* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D @@ -125,7 +120,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, case 6: if ((cop <= 6) && (cop >= 2)) { /* invalid all tlb */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return; } break; @@ -236,23 +231,22 @@ void helper_cp1_putc(target_ulong x) #ifdef CONFIG_USER_ONLY void switch_mode(CPUUniCore32State *env, int mode) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (mode != ASR_MODE_USER) { - cpu_abort(env, "Tried to switch out of user mode\n"); + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); } } void uc32_cpu_do_interrupt(CPUState *cs) { - UniCore32CPU *cpu = UNICORE32_CPU(cs); - CPUUniCore32State *env = &cpu->env; - - cpu_abort(env, "NO interrupt in user mode\n"); + cpu_abort(cs, "NO interrupt in user mode\n"); } -int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, +int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int access_type, int mmu_idx) { - cpu_abort(env, "NO mmu fault in user mode\n"); + cpu_abort(cs, "NO mmu fault in user mode\n"); return 1; } #endif diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index 4f9f41e..4c6950d 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -16,8 +16,10 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) { - env->exception_index = excp; - cpu_loop_exit(env); + CPUState *cs = CPU(uc32_env_get_cpu(env)); + + cs->exception_index = excp; + cpu_loop_exit(cs); } static target_ulong asr_read(CPUUniCore32State *env) @@ -255,18 +257,18 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i) #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { int ret; - ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index 22defc6..9a3786d 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -33,6 +33,8 @@ /* Map CPU modes onto saved register banks. */ static inline int bank_number(CPUUniCore32State *env, int mode) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + switch (mode) { case ASR_MODE_USER: case ASR_MODE_SUSR: @@ -46,7 +48,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode) case ASR_MODE_INTR: return 4; } - cpu_abort(env, "Bad mode %x\n", mode); + cpu_abort(CPU(cpu), "Bad mode %x\n", mode); return -1; } @@ -79,7 +81,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) uint32_t addr; int new_mode; - switch (env->exception_index) { + switch (cs->exception_index) { case UC32_EXCP_PRIV: new_mode = ASR_MODE_PRIV; addr = 0x08; @@ -99,7 +101,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) addr = 0x18; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; } /* High vectors. */ @@ -121,7 +123,8 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, int access_type, int is_user, uint32_t *phys_ptr, int *prot, target_ulong *page_size) { - CPUState *cs = ENV_GET_CPU(env); + UniCore32CPU *cpu = uc32_env_get_cpu(env); + CPUState *cs = CPU(cpu); int code; uint32_t table; uint32_t desc; @@ -168,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, *page_size = TARGET_PAGE_SIZE; break; default: - cpu_abort(env, "wrong page type!"); + cpu_abort(CPU(cpu), "wrong page type!"); } break; default: - cpu_abort(env, "wrong page type!"); + cpu_abort(CPU(cpu), "wrong page type!"); } *phys_ptr = phys_addr; @@ -209,9 +212,11 @@ do_fault: return code; } -int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, +int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int access_type, int mmu_idx) { + UniCore32CPU *cpu = UNICORE32_CPU(cs); + CPUUniCore32State *env = &cpu->env; uint32_t phys_addr; target_ulong page_size; int prot; @@ -231,7 +236,7 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, ret = get_phys_addr_ucv2(env, address, access_type, is_user, &phys_addr, &prot, &page_size); if (is_user) { - DPRINTF("user space access: ret %x, address %x, " + DPRINTF("user space access: ret %x, address %" VADDR_PRIx ", " "access_type %x, phys_addr %x, prot %x\n", ret, address, access_type, phys_addr, prot); } @@ -248,16 +253,16 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, /* Map a single page. */ phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; - tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); return 0; } env->cp0.c3_faultstatus = ret; env->cp0.c4_faultaddr = address; if (access_type == 2) { - env->exception_index = UC32_EXCP_ITRAP; + cs->exception_index = UC32_EXCP_ITRAP; } else { - env->exception_index = UC32_EXCP_DTRAP; + cs->exception_index = UC32_EXCP_DTRAP; } return ret; } @@ -266,6 +271,6 @@ hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { UniCore32CPU *cpu = UNICORE32_CPU(cs); - cpu_abort(&cpu->env, "%s not supported yet\n", __func__); + cpu_abort(CPU(cpu), "%s not supported yet\n", __func__); return addr; } diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 4572890..c2402cf 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -176,7 +176,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) #define UCOP_SET_L UCOP_SET(24) #define UCOP_SET_S UCOP_SET(24) -#define ILLEGAL cpu_abort(env, \ +#define ILLEGAL cpu_abort(CPU(cpu), \ "Illegal UniCore32 instruction %x at line %d!", \ insn, __LINE__) @@ -184,6 +184,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp, tmp2, tmp3; if ((insn & 0xfe000000) == 0xe0000000) { tmp2 = new_tmp(); @@ -209,6 +210,7 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xff003fff) == 0xe1000400) { @@ -689,6 +691,7 @@ static inline long ucf64_reg_offset(int reg) /* UniCore-F64 single load/store I_offset */ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); int offset; TCGv tmp; TCGv addr; @@ -735,6 +738,7 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 load/store multiple words */ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int i; int j, n, freg; TCGv tmp; @@ -820,6 +824,7 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 mrc/mcr */ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xfe0003ff) == 0xe2000000) { @@ -884,6 +889,8 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* UniCore-F64 convert instructions */ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -950,6 +957,8 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 compare instructions */ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_SET(25)) { ILLEGAL; } @@ -1028,6 +1037,8 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 data processing */ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -1061,6 +1072,8 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* Disassemble an F64 instruction */ static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (!UCOP_SET(29)) { if (UCOP_SET(26)) { do_ucf64_ldst_m(env, s, insn); @@ -1167,6 +1180,8 @@ static void gen_exception_return(DisasContext *s, TCGv pc) static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + switch (UCOP_CPNUM) { #ifndef CONFIG_USER_ONLY case 0: @@ -1181,13 +1196,14 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, break; default: /* Unknown coprocessor. */ - cpu_abort(env, "Unknown coprocessor!"); + cpu_abort(CPU(cpu), "Unknown coprocessor!"); } } /* data processing instructions */ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; TCGv tmp2; int logic_cc; @@ -1421,6 +1437,7 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* miscellaneous instructions */ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; TCGv tmp; @@ -1546,6 +1563,7 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* SWP instruction */ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; TCGv tmp2; @@ -1573,6 +1591,7 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store hw/sb */ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; @@ -1625,6 +1644,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store multiple words */ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val, i, mmu_idx; int j, n, reg, user, loaded_base; TCGv tmp; @@ -1766,6 +1786,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* branch (and link) */ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; int32_t offset; TCGv tmp; @@ -1795,6 +1816,7 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int insn; if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { @@ -1922,8 +1944,8 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_set_pc_im(dc->pc); gen_exception(EXCP_DEBUG); @@ -1978,7 +2000,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(env, "IO on conditional branch instruction"); + cpu_abort(cs, "IO on conditional branch instruction"); } gen_io_end(); } diff --git a/target-unicore32/ucf64_helper.c b/target-unicore32/ucf64_helper.c index a516edd..34fa2a5 100644 --- a/target-unicore32/ucf64_helper.c +++ b/target-unicore32/ucf64_helper.c @@ -76,6 +76,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits) void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); int i; uint32_t changed; @@ -99,7 +100,7 @@ void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) i = float_round_down; break; default: /* 100 and 101 not implement */ - cpu_abort(env, "Unsupported UniCore-F64 round mode"); + cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode"); } set_float_rounding_mode(i, &env->ucf64.fp_status); } diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 749e205..6251f1c 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +static bool xtensa_cpu_has_work(CPUState *cs) +{ + XtensaCPU *cpu = XTENSA_CPU(cs); + + return cpu->env.pending_irq_level; +} + /* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { @@ -134,6 +141,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->reset = xtensa_cpu_reset; cc->class_by_name = xtensa_cpu_class_by_name; + cc->has_work = xtensa_cpu_has_work; cc->do_interrupt = xtensa_cpu_do_interrupt; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 1cf5ea3..e210bac 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -359,7 +359,7 @@ typedef struct CPUXtensaState { int exception_taken; /* Watchpoints for DBREAK registers */ - CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; CPU_COMMON } CPUXtensaState; @@ -493,6 +493,8 @@ static inline int cpu_mmu_index(CPUXtensaState *env) static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + *pc = env->pc; *cs_base = 0; *flags = 0; @@ -515,7 +517,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; } - if (ENV_GET_CPU(env)->singlestep_enabled && env->exception_taken) { + if (cs->singlestep_enabled && env->exception_taken) { *flags |= XTENSA_TBFLAG_EXCEPTION; } } @@ -523,11 +525,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, #include "exec/cpu-all.h" #include "exec/exec-all.h" -static inline int cpu_has_work(CPUState *cpu) -{ - CPUXtensaState *env = &XTENSA_CPU(cpu)->env; - - return env->pending_irq_level; -} - #endif diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 60cb055..94dcd94 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -81,16 +81,18 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env) void xtensa_breakpoint_handler(CPUXtensaState *env) { - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { uint32_t cause; - env->watchpoint_hit = NULL; + cs->watchpoint_hit = NULL; cause = check_hw_breakpoints(env); if (cause) { debug_exception_env(env, cause); } - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } @@ -169,6 +171,8 @@ static void handle_interrupt(CPUXtensaState *env) (env->config->level_mask[level] & env->sregs[INTSET] & env->sregs[INTENABLE])) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + if (level > 1) { env->sregs[EPC1 + level - 1] = env->pc; env->sregs[EPS2 + level - 2] = env->sregs[PS]; @@ -185,10 +189,10 @@ static void handle_interrupt(CPUXtensaState *env) } else { env->sregs[EPC1] = env->pc; } - env->exception_index = EXC_DOUBLE; + cs->exception_index = EXC_DOUBLE; } else { env->sregs[EPC1] = env->pc; - env->exception_index = + cs->exception_index = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; } env->sregs[PS] |= PS_EXCM; @@ -202,7 +206,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; - if (env->exception_index == EXC_IRQ) { + if (cs->exception_index == EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, "%s(EXC_IRQ) level = %d, cintlevel = %d, " "pc = %08x, a0 = %08x, ps = %08x, " @@ -215,7 +219,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) handle_interrupt(env); } - switch (env->exception_index) { + switch (cs->exception_index) { case EXC_WINDOW_OVERFLOW4: case EXC_WINDOW_UNDERFLOW4: case EXC_WINDOW_OVERFLOW8: @@ -228,15 +232,15 @@ void xtensa_cpu_do_interrupt(CPUState *cs) case EXC_DEBUG: qemu_log_mask(CPU_LOG_INT, "%s(%d) " "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", - __func__, env->exception_index, + __func__, cs->exception_index, env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); - if (env->config->exception_vector[env->exception_index]) { + if (env->config->exception_vector[cs->exception_index]) { env->pc = relocated_vector(env, - env->config->exception_vector[env->exception_index]); + env->config->exception_vector[cs->exception_index]); env->exception_taken = 1; } else { qemu_log("%s(pc = %08x) bad exception_index: %d\n", - __func__, env->pc, env->exception_index); + __func__, env->pc, cs->exception_index); } break; @@ -245,7 +249,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) default: qemu_log("%s(pc = %08x) unknown exception_index: %d\n", - __func__, env->pc, env->exception_index); + __func__, env->pc, cs->exception_index); break; } check_interrupts(env); @@ -552,7 +556,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = CPU(xtensa_env_get_cpu(env)); uint32_t paddr; uint32_t page_size; unsigned access; diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 509ba49..b531019 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -52,17 +52,21 @@ static void do_unaligned_access(CPUXtensaState *env, static void do_unaligned_access(CPUXtensaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); HELPER(exception_cause_vaddr)(env, env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); } } -void tlb_fill(CPUXtensaState *env, - target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, + target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) { + XtensaCPU *cpu = XTENSA_CPU(cs); + CPUXtensaState *env = &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; @@ -73,12 +77,12 @@ void tlb_fill(CPUXtensaState *env, vaddr, is_write, mmu_idx, paddr, ret); if (ret == 0) { - tlb_set_page(env, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); + tlb_set_page(cs, + vaddr & TARGET_PAGE_MASK, + paddr & TARGET_PAGE_MASK, + access, mmu_idx, page_size); } else { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } } @@ -97,11 +101,13 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { - env->exception_index = excp; + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + cs->exception_index = excp; if (excp == EXCP_DEBUG) { env->exception_taken = 0; } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) @@ -387,7 +393,7 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) (intlevel << PS_INTLEVEL_SHIFT); check_interrupts(env); if (env->pending_irq_level) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); return; } @@ -481,10 +487,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + v = (v & 0xffffff00) | 0x1; if (v != env->sregs[RASID]) { env->sregs[RASID] = v; - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -681,7 +689,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) uint32_t wi; xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); if (entry->variable && entry->asid) { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); entry->asid = 0; } } @@ -726,21 +734,23 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + CPUState *cs = CPU(cpu); xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { if (entry->variable) { if (entry->asid) { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); } xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); } else { qemu_log("%s %d, %d, %d trying to set immutable entry\n", __func__, dtlb, wi, ei); } } else { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); if (xtensa_option_enabled(env->config, XTENSA_OPTION_REGION_TRANSLATION)) { entry->paddr = pte & REGION_PAGE_MASK; @@ -784,11 +794,12 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t mask = dbreakc | ~DBREAKC_MASK; if (env->cpu_watchpoint[i]) { - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); } if (dbreakc & DBREAKC_SB) { flags |= BP_MEM_WRITE; @@ -802,7 +813,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, /* cut mask after the first zero bit */ mask = 0xffffffff << (32 - clo32(mask)); } - if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1, + if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, flags, &env->cpu_watchpoint[i])) { env->cpu_watchpoint[i] = NULL; qemu_log("Failed to set data breakpoint at 0x%08x/%d\n", @@ -828,7 +839,9 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) set_dbreak(env, i, env->sregs[DBREAKA + i], v); } else { if (env->cpu_watchpoint[i]) { - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); env->cpu_watchpoint[i] = NULL; } } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 9f5895e..764cee9 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2948,10 +2948,11 @@ invalid_opcode: static void check_breakpoint(CPUXtensaState *env, DisasContext *dc) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_i32(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 04d7ae3..661a5af 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -13,6 +13,11 @@ #include "tcg-be-ldst.h" #include "qemu/bitops.h" +/* We're going to re-use TCGType in setting of the SF bit, which controls + the size of the operation performed. If we know the values match, it + makes things much cleaner. */ +QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1); + #ifndef NDEBUG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "%x0", "%x1", "%x2", "%x3", "%x4", "%x5", "%x6", "%x7", @@ -66,24 +71,22 @@ static const int tcg_target_call_oarg_regs[1] = { # endif #endif -static inline void reloc_pc26(void *code_ptr, tcg_target_long target) +static inline void reloc_pc26(void *code_ptr, intptr_t target) { - tcg_target_long offset; uint32_t insn; - offset = (target - (tcg_target_long)code_ptr) / 4; + intptr_t offset = (target - (intptr_t)code_ptr) / 4; /* read instruction, mask away previous PC_REL26 parameter contents, set the proper offset, then write back the instruction. */ - insn = *(uint32_t *)code_ptr; + uint32_t insn = *(uint32_t *)code_ptr; insn = deposit32(insn, 0, 26, offset); *(uint32_t *)code_ptr = insn; } -static inline void reloc_pc19(void *code_ptr, tcg_target_long target) +static inline void reloc_pc19(void *code_ptr, intptr_t target) { - tcg_target_long offset; uint32_t insn; - offset = (target - (tcg_target_long)code_ptr) / 4; + intptr_t offset = (target - (intptr_t)code_ptr) / 4; /* read instruction, mask away previous PC_REL19 parameter contents, set the proper offset, then write back the instruction. */ - insn = *(uint32_t *)code_ptr; + uint32_t insn = *(uint32_t *)code_ptr; insn = deposit32(insn, 5, 19, offset); *(uint32_t *)code_ptr = insn; } @@ -107,6 +110,12 @@ static inline void patch_reloc(uint8_t *code_ptr, int type, } } +#define TCG_CT_CONST_IS32 0x100 +#define TCG_CT_CONST_AIMM 0x200 +#define TCG_CT_CONST_LIMM 0x400 +#define TCG_CT_CONST_ZERO 0x800 +#define TCG_CT_CONST_MONE 0x1000 + /* parse target specific constraints */ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) @@ -130,6 +139,21 @@ static int target_parse_constraint(TCGArgConstraint *ct, tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); #endif break; + case 'w': /* The operand should be considered 32-bit. */ + ct->ct |= TCG_CT_CONST_IS32; + break; + case 'A': /* Valid for arithmetic immediate (positive or negative). */ + ct->ct |= TCG_CT_CONST_AIMM; + break; + case 'L': /* Valid for logical immediate. */ + ct->ct |= TCG_CT_CONST_LIMM; + break; + case 'M': /* minus one */ + ct->ct |= TCG_CT_CONST_MONE; + break; + case 'Z': /* zero */ + ct->ct |= TCG_CT_CONST_ZERO; + break; default: return -1; } @@ -139,14 +163,54 @@ static int target_parse_constraint(TCGArgConstraint *ct, return 0; } -static inline int tcg_target_const_match(tcg_target_long val, - const TCGArgConstraint *arg_ct) +static inline bool is_aimm(uint64_t val) +{ + return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0; +} + +static inline bool is_limm(uint64_t val) +{ + /* Taking a simplified view of the logical immediates for now, ignoring + the replication that can happen across the field. Match bit patterns + of the forms + 0....01....1 + 0..01..10..0 + and their inverses. */ + + /* Make things easier below, by testing the form with msb clear. */ + if ((int64_t)val < 0) { + val = ~val; + } + if (val == 0) { + return false; + } + val += val & -val; + return (val & (val - 1)) == 0; +} + +static int tcg_target_const_match(tcg_target_long val, + const TCGArgConstraint *arg_ct) { int ct = arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } + if (ct & TCG_CT_CONST_IS32) { + val = (int32_t)val; + } + if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) { + return 1; + } + if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) { + return 1; + } + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } + if ((ct & TCG_CT_CONST_MONE) && val == -1) { + return 1; + } return 0; } @@ -200,23 +264,76 @@ enum aarch64_ldst_op_type { /* type of operation */ LDST_LD_S_W = 0xc, /* load and sign-extend into Wt */ }; -enum aarch64_arith_opc { - ARITH_AND = 0x0a, - ARITH_ADD = 0x0b, - ARITH_OR = 0x2a, - ARITH_ADDS = 0x2b, - ARITH_XOR = 0x4a, - ARITH_SUB = 0x4b, - ARITH_ANDS = 0x6a, - ARITH_SUBS = 0x6b, -}; - -enum aarch64_srr_opc { - SRR_SHL = 0x0, - SRR_SHR = 0x4, - SRR_SAR = 0x8, - SRR_ROR = 0xc -}; +/* We encode the format of the insn into the beginning of the name, so that + we can have the preprocessor help "typecheck" the insn vs the output + function. Arm didn't provide us with nice names for the formats, so we + use the section number of the architecture reference manual in which the + instruction group is described. */ +typedef enum { + /* Add/subtract immediate instructions. */ + I3401_ADDI = 0x11000000, + I3401_ADDSI = 0x31000000, + I3401_SUBI = 0x51000000, + I3401_SUBSI = 0x71000000, + + /* Bitfield instructions. */ + I3402_BFM = 0x33000000, + I3402_SBFM = 0x13000000, + I3402_UBFM = 0x53000000, + + /* Extract instruction. */ + I3403_EXTR = 0x13800000, + + /* Logical immediate instructions. */ + I3404_ANDI = 0x12000000, + I3404_ORRI = 0x32000000, + I3404_EORI = 0x52000000, + + /* Move wide immediate instructions. */ + I3405_MOVN = 0x12800000, + I3405_MOVZ = 0x52800000, + I3405_MOVK = 0x72800000, + + /* Add/subtract shifted register instructions (without a shift). */ + I3502_ADD = 0x0b000000, + I3502_ADDS = 0x2b000000, + I3502_SUB = 0x4b000000, + I3502_SUBS = 0x6b000000, + + /* Add/subtract shifted register instructions (with a shift). */ + I3502S_ADD_LSL = I3502_ADD, + + /* Add/subtract with carry instructions. */ + I3503_ADC = 0x1a000000, + I3503_SBC = 0x5a000000, + + /* Conditional select instructions. */ + I3506_CSEL = 0x1a800000, + I3506_CSINC = 0x1a800400, + + /* Data-processing (2 source) instructions. */ + I3508_LSLV = 0x1ac02000, + I3508_LSRV = 0x1ac02400, + I3508_ASRV = 0x1ac02800, + I3508_RORV = 0x1ac02c00, + I3508_SMULH = 0x9b407c00, + I3508_UMULH = 0x9bc07c00, + I3508_UDIV = 0x1ac00800, + I3508_SDIV = 0x1ac00c00, + + /* Data-processing (3 source) instructions. */ + I3509_MADD = 0x1b000000, + I3509_MSUB = 0x1b008000, + + /* Logical shifted register instructions (without a shift). */ + I3510_AND = 0x0a000000, + I3510_BIC = 0x0a200000, + I3510_ORR = 0x2a000000, + I3510_ORN = 0x2a200000, + I3510_EOR = 0x4a000000, + I3510_EON = 0x4a200000, + I3510_ANDS = 0x6a000000, +} AArch64Insn; static inline enum aarch64_ldst_op_data aarch64_ldst_get_data(TCGOpcode tcg_op) @@ -296,24 +413,95 @@ static inline uint32_t tcg_in32(TCGContext *s) return v; } +/* Emit an opcode with "type-checking" of the format. */ +#define tcg_out_insn(S, FMT, OP, ...) \ + glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__) + +static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, uint64_t aimm) +{ + if (aimm > 0xfff) { + assert((aimm & 0xfff) == 0); + aimm >>= 12; + assert(aimm <= 0xfff); + aimm |= 1 << 12; /* apply LSL 12 */ + } + tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd); +} + +/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4 + (Logical immediate). Both insn groups have N, IMMR and IMMS fields + that feed the DecodeBitMasks pseudo function. */ +static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, int n, int immr, int imms) +{ + tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10 + | rn << 5 | rd); +} + +#define tcg_out_insn_3404 tcg_out_insn_3402 + +static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm, int imms) +{ + tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10 + | rn << 5 | rd); +} + +/* This function is used for the Move (wide immediate) instruction group. + Note that SHIFT is a full shift count, not the 2 bit HW field. */ +static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, uint16_t half, unsigned shift) +{ + assert((shift & ~0x30) == 0); + tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd); +} + +/* This function is for both 3.5.2 (Add/Subtract shifted register), for + the rare occasion when we actually want to supply a shift amount. */ +static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, + TCGType ext, TCGReg rd, TCGReg rn, + TCGReg rm, int imm6) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd); +} + +/* This function is for 3.5.2 (Add/subtract shifted register), + and 3.5.10 (Logical shifted register), for the vast majorty of cases + when we don't want to apply a shift. Thus it can also be used for + 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */ +static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd); +} + +#define tcg_out_insn_3503 tcg_out_insn_3502 +#define tcg_out_insn_3508 tcg_out_insn_3502 +#define tcg_out_insn_3510 tcg_out_insn_3502 + +static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd + | tcg_cond_to_aarch64[c] << 12); +} + +static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd); +} + + static inline void tcg_out_ldst_9(TCGContext *s, enum aarch64_ldst_op_data op_data, enum aarch64_ldst_op_type op_type, TCGReg rd, TCGReg rn, tcg_target_long offset) { /* use LDUR with BASE register with 9bit signed unscaled offset */ - unsigned int mod, off; - - if (offset < 0) { - off = (256 + offset); - mod = 0x1; - } else { - off = offset; - mod = 0x0; - } - - mod |= op_type; - tcg_out32(s, op_data << 24 | mod << 20 | off << 12 | rn << 5 | rd); + tcg_out32(s, op_data << 24 | op_type << 20 + | (offset & 0x1ff) << 12 | rn << 5 | rd); } /* tcg_out_ldst_12 expects a scaled unsigned immediate offset */ @@ -327,46 +515,42 @@ static inline void tcg_out_ldst_12(TCGContext *s, | op_type << 20 | scaled_uimm << 10 | rn << 5 | rd); } -static inline void tcg_out_movr(TCGContext *s, int ext, TCGReg rd, TCGReg src) +/* Register to register move using ORR (shifted register with no shift). */ +static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm) { - /* register to register move using MOV (shifted register with no shift) */ - /* using MOV 0x2a0003e0 | (shift).. */ - unsigned int base = ext ? 0xaa0003e0 : 0x2a0003e0; - tcg_out32(s, base | src << 16 | rd); + tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm); } -static inline void tcg_out_movi_aux(TCGContext *s, - TCGReg rd, uint64_t value) +/* Register to register move using ADDI (move to/from SP). */ +static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn) { - uint32_t half, base, shift, movk = 0; - /* construct halfwords of the immediate with MOVZ/MOVK with LSL */ - /* using MOVZ 0x52800000 | extended reg.. */ - base = (value > 0xffffffff) ? 0xd2800000 : 0x52800000; + tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0); +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, + tcg_target_long value) +{ + AArch64Insn insn; + + if (type == TCG_TYPE_I32) { + value = (uint32_t)value; + } + /* count trailing zeros in 16 bit steps, mapping 64 to 0. Emit the first MOVZ with the half-word immediate skipping the zeros, with a shift - (LSL) equal to this number. Then morph all next instructions into MOVKs. + (LSL) equal to this number. Then all next instructions use MOVKs. Zero the processed half-word in the value, continue until empty. We build the final result 16bits at a time with up to 4 instructions, but do not emit instructions for 16bit zero holes. */ + insn = I3405_MOVZ; do { - shift = ctz64(value) & (63 & -16); - half = (value >> shift) & 0xffff; - tcg_out32(s, base | movk | shift << 17 | half << 5 | rd); - movk = 0x20000000; /* morph next MOVZs into MOVKs */ + unsigned shift = ctz64(value) & (63 & -16); + tcg_out_insn_3405(s, insn, shift >= 32, rd, value >> shift, shift); value &= ~(0xffffUL << shift); + insn = I3405_MOVK; } while (value); } -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg rd, tcg_target_long value) -{ - if (type == TCG_TYPE_I64) { - tcg_out_movi_aux(s, rd, value); - } else { - tcg_out_movi_aux(s, rd, value & 0xffffffff); - } -} - static inline void tcg_out_ldst_r(TCGContext *s, enum aarch64_ldst_op_data op_data, enum aarch64_ldst_op_type op_type, @@ -407,14 +591,6 @@ static inline void tcg_out_ldst(TCGContext *s, enum aarch64_ldst_op_data data, tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP); } -/* mov alias implemented with add immediate, useful to move to/from SP */ -static inline void tcg_out_movr_sp(TCGContext *s, int ext, TCGReg rd, TCGReg rn) -{ - /* using ADD 0x11000000 | (ext) | rn << 5 | rd */ - unsigned int base = ext ? 0x91000000 : 0x11000000; - tcg_out32(s, base | rn << 5 | rd); -} - static inline void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { @@ -437,121 +613,95 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, arg, arg1, arg2); } -static inline void tcg_out_arith(TCGContext *s, enum aarch64_arith_opc opc, - int ext, TCGReg rd, TCGReg rn, TCGReg rm, - int shift_imm) +static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned int a, unsigned int b) { - /* Using shifted register arithmetic operations */ - /* if extended register operation (64bit) just OR with 0x80 << 24 */ - unsigned int shift, base = ext ? (0x80 | opc) << 24 : opc << 24; - if (shift_imm == 0) { - shift = 0; - } else if (shift_imm > 0) { - shift = shift_imm << 10 | 1 << 22; - } else /* (shift_imm < 0) */ { - shift = (-shift_imm) << 10; - } - tcg_out32(s, base | rm << 16 | shift | rn << 5 | rd); -} - -static inline void tcg_out_mul(TCGContext *s, int ext, - TCGReg rd, TCGReg rn, TCGReg rm) -{ - /* Using MADD 0x1b000000 with Ra = wzr alias MUL 0x1b007c00 */ - unsigned int base = ext ? 0x9b007c00 : 0x1b007c00; - tcg_out32(s, base | rm << 16 | rn << 5 | rd); -} - -static inline void tcg_out_shiftrot_reg(TCGContext *s, - enum aarch64_srr_opc opc, int ext, - TCGReg rd, TCGReg rn, TCGReg rm) -{ - /* using 2-source data processing instructions 0x1ac02000 */ - unsigned int base = ext ? 0x9ac02000 : 0x1ac02000; - tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd); + tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b); } -static inline void tcg_out_ubfm(TCGContext *s, int ext, TCGReg rd, TCGReg rn, - unsigned int a, unsigned int b) +static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned int a, unsigned int b) { - /* Using UBFM 0x53000000 Wd, Wn, a, b */ - unsigned int base = ext ? 0xd3400000 : 0x53000000; - tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd); + tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b); } -static inline void tcg_out_sbfm(TCGContext *s, int ext, TCGReg rd, TCGReg rn, - unsigned int a, unsigned int b) +static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned int a, unsigned int b) { - /* Using SBFM 0x13000000 Wd, Wn, a, b */ - unsigned int base = ext ? 0x93400000 : 0x13000000; - tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd); + tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b); } -static inline void tcg_out_extr(TCGContext *s, int ext, TCGReg rd, +static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn, TCGReg rm, unsigned int a) { - /* Using EXTR 0x13800000 Wd, Wn, Wm, a */ - unsigned int base = ext ? 0x93c00000 : 0x13800000; - tcg_out32(s, base | rm << 16 | a << 10 | rn << 5 | rd); + tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a); } -static inline void tcg_out_shl(TCGContext *s, int ext, +static inline void tcg_out_shl(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn, unsigned int m) { - int bits, max; - bits = ext ? 64 : 32; - max = bits - 1; + int bits = ext ? 64 : 32; + int max = bits - 1; tcg_out_ubfm(s, ext, rd, rn, bits - (m & max), max - (m & max)); } -static inline void tcg_out_shr(TCGContext *s, int ext, +static inline void tcg_out_shr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn, unsigned int m) { int max = ext ? 63 : 31; tcg_out_ubfm(s, ext, rd, rn, m & max, max); } -static inline void tcg_out_sar(TCGContext *s, int ext, +static inline void tcg_out_sar(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn, unsigned int m) { int max = ext ? 63 : 31; tcg_out_sbfm(s, ext, rd, rn, m & max, max); } -static inline void tcg_out_rotr(TCGContext *s, int ext, +static inline void tcg_out_rotr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn, unsigned int m) { int max = ext ? 63 : 31; tcg_out_extr(s, ext, rd, rn, rn, m & max); } -static inline void tcg_out_rotl(TCGContext *s, int ext, +static inline void tcg_out_rotl(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn, unsigned int m) { - int bits, max; - bits = ext ? 64 : 32; - max = bits - 1; + int bits = ext ? 64 : 32; + int max = bits - 1; tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max)); } -static inline void tcg_out_cmp(TCGContext *s, int ext, TCGReg rn, TCGReg rm, - int shift_imm) +static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned lsb, unsigned width) { - /* Using CMP alias SUBS wzr, Wn, Wm */ - tcg_out_arith(s, ARITH_SUBS, ext, TCG_REG_XZR, rn, rm, shift_imm); + unsigned size = ext ? 64 : 32; + unsigned a = (size - lsb) & (size - 1); + unsigned b = width - 1; + tcg_out_bfm(s, ext, rd, rn, a, b); } -static inline void tcg_out_cset(TCGContext *s, int ext, TCGReg rd, TCGCond c) +static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, + tcg_target_long b, bool const_b) { - /* Using CSET alias of CSINC 0x1a800400 Xd, XZR, XZR, invert(cond) */ - unsigned int base = ext ? 0x9a9f07e0 : 0x1a9f07e0; - tcg_out32(s, base | tcg_cond_to_aarch64[tcg_invert_cond(c)] << 12 | rd); + if (const_b) { + /* Using CMP or CMN aliases. */ + if (b >= 0) { + tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b); + } else { + tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b); + } + } else { + /* Using CMP alias SUBS wzr, Wn, Wm */ + tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b); + } } -static inline void tcg_out_goto(TCGContext *s, tcg_target_long target) +static inline void tcg_out_goto(TCGContext *s, intptr_t target) { - tcg_target_long offset; - offset = (target - (tcg_target_long)s->code_ptr) / 4; + intptr_t offset = (target - (intptr_t)s->code_ptr) / 4; if (offset < -0x02000000 || offset >= 0x02000000) { /* out of 26bit range */ @@ -582,11 +732,9 @@ static inline void tcg_out_goto_cond_noaddr(TCGContext *s, TCGCond c) tcg_out32(s, insn); } -static inline void tcg_out_goto_cond(TCGContext *s, TCGCond c, - tcg_target_long target) +static inline void tcg_out_goto_cond(TCGContext *s, TCGCond c, intptr_t target) { - tcg_target_long offset; - offset = (target - (tcg_target_long)s->code_ptr) / 4; + intptr_t offset = (target - (intptr_t)s->code_ptr) / 4; if (offset < -0x40000 || offset >= 0x40000) { /* out of 19bit range */ @@ -607,11 +755,9 @@ static inline void tcg_out_gotor(TCGContext *s, TCGReg reg) tcg_out32(s, 0xd61f0000 | reg << 5); } -static inline void tcg_out_call(TCGContext *s, tcg_target_long target) +static inline void tcg_out_call(TCGContext *s, intptr_t target) { - tcg_target_long offset; - - offset = (target - (tcg_target_long)s->code_ptr) / 4; + intptr_t offset = (target - (intptr_t)s->code_ptr) / 4; if (offset < -0x02000000 || offset >= 0x02000000) { /* out of 26bit rng */ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, target); @@ -621,40 +767,6 @@ static inline void tcg_out_call(TCGContext *s, tcg_target_long target) } } -/* encode a logical immediate, mapping user parameter - M=set bits pattern length to S=M-1 */ -static inline unsigned int -aarch64_limm(unsigned int m, unsigned int r) -{ - assert(m > 0); - return r << 16 | (m - 1) << 10; -} - -/* test a register against an immediate bit pattern made of - M set bits rotated right by R. - Examples: - to test a 32/64 reg against 0x00000007, pass M = 3, R = 0. - to test a 32/64 reg against 0x000000ff, pass M = 8, R = 0. - to test a 32bit reg against 0xff000000, pass M = 8, R = 8. - to test a 32bit reg against 0xff0000ff, pass M = 16, R = 8. - */ -static inline void tcg_out_tst(TCGContext *s, int ext, TCGReg rn, - unsigned int m, unsigned int r) -{ - /* using TST alias of ANDS XZR, Xn,#bimm64 0x7200001f */ - unsigned int base = ext ? 0xf240001f : 0x7200001f; - tcg_out32(s, base | aarch64_limm(m, r) | rn << 5); -} - -/* and a register with a bit pattern, similarly to TST, no flags change */ -static inline void tcg_out_andi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, - unsigned int m, unsigned int r) -{ - /* using AND 0x12000000 */ - unsigned int base = ext ? 0x92400000 : 0x12000000; - tcg_out32(s, base | aarch64_limm(m, r) | rn << 5 | rd); -} - static inline void tcg_out_ret(TCGContext *s) { /* emit RET { LR } */ @@ -663,9 +775,8 @@ static inline void tcg_out_ret(TCGContext *s) void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) { - tcg_target_long target, offset; - target = (tcg_target_long)addr; - offset = (target - (tcg_target_long)jmp_addr) / 4; + intptr_t target = addr; + intptr_t offset = (target - (intptr_t)jmp_addr) / 4; if (offset < -0x02000000 || offset >= 0x02000000) { /* out of 26bit range */ @@ -701,25 +812,26 @@ static inline void tcg_out_goto_label_cond(TCGContext *s, } } -static inline void tcg_out_rev(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +static inline void tcg_out_rev(TCGContext *s, TCGType ext, + TCGReg rd, TCGReg rm) { /* using REV 0x5ac00800 */ unsigned int base = ext ? 0xdac00c00 : 0x5ac00800; tcg_out32(s, base | rm << 5 | rd); } -static inline void tcg_out_rev16(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +static inline void tcg_out_rev16(TCGContext *s, TCGType ext, + TCGReg rd, TCGReg rm) { /* using REV16 0x5ac00400 */ unsigned int base = ext ? 0xdac00400 : 0x5ac00400; tcg_out32(s, base | rm << 5 | rd); } -static inline void tcg_out_sxt(TCGContext *s, int ext, int s_bits, +static inline void tcg_out_sxt(TCGContext *s, TCGType ext, int s_bits, TCGReg rd, TCGReg rn) { - /* using ALIASes SXTB 0x13001c00, SXTH 0x13003c00, SXTW 0x93407c00 - of SBFM Xd, Xn, #0, #7|15|31 */ + /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */ int bits = 8 * (1 << s_bits) - 1; tcg_out_sbfm(s, ext, rd, rn, 0, bits); } @@ -727,55 +839,91 @@ static inline void tcg_out_sxt(TCGContext *s, int ext, int s_bits, static inline void tcg_out_uxt(TCGContext *s, int s_bits, TCGReg rd, TCGReg rn) { - /* using ALIASes UXTB 0x53001c00, UXTH 0x53003c00 - of UBFM Wd, Wn, #0, #7|15 */ + /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */ int bits = 8 * (1 << s_bits) - 1; tcg_out_ubfm(s, 0, rd, rn, 0, bits); } -static inline void tcg_out_addi(TCGContext *s, int ext, - TCGReg rd, TCGReg rn, unsigned int aimm) +static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, + TCGReg rn, int64_t aimm) { - /* add immediate aimm unsigned 12bit value (with LSL 0 or 12) */ - /* using ADD 0x11000000 | (ext) | (aimm << 10) | (rn << 5) | rd */ - unsigned int base = ext ? 0x91000000 : 0x11000000; - - if (aimm <= 0xfff) { - aimm <<= 10; + if (aimm >= 0) { + tcg_out_insn(s, 3401, ADDI, ext, rd, rn, aimm); } else { - /* we can only shift left by 12, on assert we cannot represent */ - assert(!(aimm & 0xfff)); - assert(aimm <= 0xfff000); - base |= 1 << 22; /* apply LSL 12 */ - aimm >>= 2; + tcg_out_insn(s, 3401, SUBI, ext, rd, rn, -aimm); } - - tcg_out32(s, base | aimm | (rn << 5) | rd); } -static inline void tcg_out_subi(TCGContext *s, int ext, - TCGReg rd, TCGReg rn, unsigned int aimm) +/* This function is used for the Logical (immediate) instruction group. + The value of LIMM must satisfy IS_LIMM. See the comment above about + only supporting simplified logical immediates. */ +static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, uint64_t limm) { - /* sub immediate aimm unsigned 12bit value (with LSL 0 or 12) */ - /* using SUB 0x51000000 | (ext) | (aimm << 10) | (rn << 5) | rd */ - unsigned int base = ext ? 0xd1000000 : 0x51000000; + unsigned h, l, r, c; + + assert(is_limm(limm)); - if (aimm <= 0xfff) { - aimm <<= 10; + h = clz64(limm); + l = ctz64(limm); + if (l == 0) { + r = 0; /* form 0....01....1 */ + c = ctz64(~limm) - 1; + if (h == 0) { + r = clz64(~limm); /* form 1..10..01..1 */ + c += r; + } } else { - /* we can only shift left by 12, on assert we cannot represent */ - assert(!(aimm & 0xfff)); - assert(aimm <= 0xfff000); - base |= 1 << 22; /* apply LSL 12 */ - aimm >>= 2; + r = 64 - l; /* form 1....10....0 or 0..01..10..0 */ + c = r - h - 1; + } + if (ext == TCG_TYPE_I32) { + r &= 31; + c &= 31; } - tcg_out32(s, base | aimm | (rn << 5) | rd); + tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c); } -static inline void tcg_out_nop(TCGContext *s) +static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl, + TCGReg rh, TCGReg al, TCGReg ah, + tcg_target_long bl, tcg_target_long bh, + bool const_bl, bool const_bh, bool sub) { - tcg_out32(s, 0xd503201f); + TCGReg orig_rl = rl; + AArch64Insn insn; + + if (rl == ah || (!const_bh && rl == bh)) { + rl = TCG_REG_TMP; + } + + if (const_bl) { + insn = I3401_ADDSI; + if ((bl < 0) ^ sub) { + insn = I3401_SUBSI; + bl = -bl; + } + tcg_out_insn_3401(s, insn, ext, rl, al, bl); + } else { + tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl); + } + + insn = I3503_ADC; + if (const_bh) { + /* Note that the only two constants we support are 0 and -1, and + that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */ + if ((bh != 0) ^ sub) { + insn = I3503_SBC; + } + bh = TCG_REG_XZR; + } else if (sub) { + insn = I3503_SBC; + } + tcg_out_insn_3503(s, insn, ext, rh, ah, bh); + + if (rl != orig_rl) { + tcg_out_movr(s, ext, orig_rl, rl); + } } #ifdef CONFIG_SOFTMMU @@ -801,7 +949,8 @@ static const void * const qemu_st_helpers[4] = { static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr); + reloc_pc19(lb->label_ptr[0], (intptr_t)s->code_ptr); + tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0); tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index); @@ -815,23 +964,21 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_movr(s, 1, lb->datalo_reg, TCG_REG_X0); } - tcg_out_goto(s, (tcg_target_long)lb->raddr); + tcg_out_goto(s, (intptr_t)lb->raddr); } static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr); + reloc_pc19(lb->label_ptr[0], (intptr_t)s->code_ptr); tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0); tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg); tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_X4, (tcg_target_long)lb->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_X4, (intptr_t)lb->raddr); tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, - (tcg_target_long)qemu_st_helpers[lb->opc & 3]); + (intptr_t)qemu_st_helpers[lb->opc & 3]); tcg_out_callr(s, TCG_REG_TMP); - - tcg_out_nop(s); tcg_out_goto(s, (tcg_target_long)lb->raddr); } @@ -870,17 +1017,17 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, /* Store the page mask part of the address and the low s_bits into X3. Later this allows checking for equality and alignment at the same time. X3 = addr_reg & (PAGE_MASK | ((1 << s_bits) - 1)) */ - tcg_out_andi(s, (TARGET_LONG_BITS == 64), TCG_REG_X3, addr_reg, - (TARGET_LONG_BITS - TARGET_PAGE_BITS) + s_bits, - (TARGET_LONG_BITS - TARGET_PAGE_BITS)); + tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64, TCG_REG_X3, + addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); /* Add any "high bits" from the tlb offset to the env address into X2, - to take advantage of the LSL12 form of the addi instruction. + to take advantage of the LSL12 form of the ADDI instruction. X2 = env + (tlb_offset & 0xfff000) */ - tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000); + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_X2, base, + tlb_offset & 0xfff000); /* Merge the tlb index contribution into X2. X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */ - tcg_out_arith(s, ARITH_ADD, 1, TCG_REG_X2, TCG_REG_X2, - TCG_REG_X0, -CPU_TLB_ENTRY_BITS); + tcg_out_insn(s, 3502S, ADD_LSL, 1, TCG_REG_X2, TCG_REG_X2, + TCG_REG_X0, CPU_TLB_ENTRY_BITS); /* Merge "low bits" from tlb offset, load the tlb comparator into X0. X0 = load [X2 + (tlb_offset & 0x000fff)] */ tcg_out_ldst(s, TARGET_LONG_BITS == 64 ? LDST_64 : LDST_32, @@ -1088,16 +1235,27 @@ static inline void tcg_out_load_pair(TCGContext *s, TCGReg addr, } static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { - /* ext will be set in the switch below, which will fall through to the - common code. It triggers the use of extended regs where appropriate. */ - int ext = 0; + /* 99% of the time, we can signal the use of extension registers + by looking to see if the opcode handles 64-bit data. */ + TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0; + + /* Hoist the loads of the most common arguments. */ + TCGArg a0 = args[0]; + TCGArg a1 = args[1]; + TCGArg a2 = args[2]; + int c2 = const_args[2]; + + /* Some operands are defined with "rZ" constraint, a register or + the zero register. These need not actually test args[I] == 0. */ +#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I]) switch (opc) { case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, args[0]); - tcg_out_goto(s, (tcg_target_long)tb_ret_addr); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); + tcg_out_goto(s, (intptr_t)tb_ret_addr); break; case INDEX_op_goto_tb: @@ -1105,23 +1263,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, #error "USE_DIRECT_JUMP required for aarch64" #endif assert(s->tb_jmp_offset != NULL); /* consistency for USE_DIRECT_JUMP */ - s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; + s->tb_jmp_offset[a0] = s->code_ptr - s->code_buf; /* actual branch destination will be patched by aarch64_tb_set_jmp_target later, beware retranslation. */ tcg_out_goto_noaddr(s); - s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; + s->tb_next_offset[a0] = s->code_ptr - s->code_buf; break; case INDEX_op_call: if (const_args[0]) { - tcg_out_call(s, args[0]); + tcg_out_call(s, a0); } else { - tcg_out_callr(s, args[0]); + tcg_out_callr(s, a0); } break; case INDEX_op_br: - tcg_out_goto_label(s, args[0]); + tcg_out_goto_label(s, a0); break; case INDEX_op_ld_i32: @@ -1144,123 +1302,202 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_st16_i64: case INDEX_op_st32_i64: tcg_out_ldst(s, aarch64_ldst_get_data(opc), aarch64_ldst_get_type(opc), - args[0], args[1], args[2]); + a0, a1, a2); break; - case INDEX_op_mov_i64: - ext = 1; /* fall through */ - case INDEX_op_mov_i32: - tcg_out_movr(s, ext, args[0], args[1]); + case INDEX_op_add_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_add_i64: + if (c2) { + tcg_out_addsubi(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2); + } break; - case INDEX_op_movi_i64: - tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); - break; - case INDEX_op_movi_i32: - tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); + case INDEX_op_sub_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_sub_i64: + if (c2) { + tcg_out_addsubi(s, ext, a0, a1, -a2); + } else { + tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2); + } break; - case INDEX_op_add_i64: - ext = 1; /* fall through */ - case INDEX_op_add_i32: - tcg_out_arith(s, ARITH_ADD, ext, args[0], args[1], args[2], 0); + case INDEX_op_neg_i64: + case INDEX_op_neg_i32: + tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1); break; - case INDEX_op_sub_i64: - ext = 1; /* fall through */ - case INDEX_op_sub_i32: - tcg_out_arith(s, ARITH_SUB, ext, args[0], args[1], args[2], 0); + case INDEX_op_and_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_and_i64: + if (c2) { + tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3510, AND, ext, a0, a1, a2); + } break; - case INDEX_op_and_i64: - ext = 1; /* fall through */ - case INDEX_op_and_i32: - tcg_out_arith(s, ARITH_AND, ext, args[0], args[1], args[2], 0); + case INDEX_op_andc_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_andc_i64: + if (c2) { + tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2); + } else { + tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2); + } break; - case INDEX_op_or_i64: - ext = 1; /* fall through */ case INDEX_op_or_i32: - tcg_out_arith(s, ARITH_OR, ext, args[0], args[1], args[2], 0); + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_or_i64: + if (c2) { + tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2); + } + break; + + case INDEX_op_orc_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_orc_i64: + if (c2) { + tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2); + } else { + tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2); + } break; - case INDEX_op_xor_i64: - ext = 1; /* fall through */ case INDEX_op_xor_i32: - tcg_out_arith(s, ARITH_XOR, ext, args[0], args[1], args[2], 0); + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_xor_i64: + if (c2) { + tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2); + } + break; + + case INDEX_op_eqv_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_eqv_i64: + if (c2) { + tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2); + } else { + tcg_out_insn(s, 3510, EON, ext, a0, a1, a2); + } + break; + + case INDEX_op_not_i64: + case INDEX_op_not_i32: + tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1); break; case INDEX_op_mul_i64: - ext = 1; /* fall through */ case INDEX_op_mul_i32: - tcg_out_mul(s, ext, args[0], args[1], args[2]); + tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR); + break; + + case INDEX_op_div_i64: + case INDEX_op_div_i32: + tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2); + break; + case INDEX_op_divu_i64: + case INDEX_op_divu_i32: + tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2); + break; + + case INDEX_op_rem_i64: + case INDEX_op_rem_i32: + tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); + break; + case INDEX_op_remu_i64: + case INDEX_op_remu_i32: + tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); break; case INDEX_op_shl_i64: - ext = 1; /* fall through */ case INDEX_op_shl_i32: - if (const_args[2]) { /* LSL / UBFM Wd, Wn, (32 - m) */ - tcg_out_shl(s, ext, args[0], args[1], args[2]); - } else { /* LSL / LSLV */ - tcg_out_shiftrot_reg(s, SRR_SHL, ext, args[0], args[1], args[2]); + if (c2) { + tcg_out_shl(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, LSLV, ext, a0, a1, a2); } break; case INDEX_op_shr_i64: - ext = 1; /* fall through */ case INDEX_op_shr_i32: - if (const_args[2]) { /* LSR / UBFM Wd, Wn, m, 31 */ - tcg_out_shr(s, ext, args[0], args[1], args[2]); - } else { /* LSR / LSRV */ - tcg_out_shiftrot_reg(s, SRR_SHR, ext, args[0], args[1], args[2]); + if (c2) { + tcg_out_shr(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, LSRV, ext, a0, a1, a2); } break; case INDEX_op_sar_i64: - ext = 1; /* fall through */ case INDEX_op_sar_i32: - if (const_args[2]) { /* ASR / SBFM Wd, Wn, m, 31 */ - tcg_out_sar(s, ext, args[0], args[1], args[2]); - } else { /* ASR / ASRV */ - tcg_out_shiftrot_reg(s, SRR_SAR, ext, args[0], args[1], args[2]); + if (c2) { + tcg_out_sar(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2); } break; case INDEX_op_rotr_i64: - ext = 1; /* fall through */ case INDEX_op_rotr_i32: - if (const_args[2]) { /* ROR / EXTR Wd, Wm, Wm, m */ - tcg_out_rotr(s, ext, args[0], args[1], args[2]); - } else { /* ROR / RORV */ - tcg_out_shiftrot_reg(s, SRR_ROR, ext, args[0], args[1], args[2]); + if (c2) { + tcg_out_rotr(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2); } break; case INDEX_op_rotl_i64: - ext = 1; /* fall through */ - case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */ - if (const_args[2]) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */ - tcg_out_rotl(s, ext, args[0], args[1], args[2]); + case INDEX_op_rotl_i32: + if (c2) { + tcg_out_rotl(s, ext, a0, a1, a2); } else { - tcg_out_arith(s, ARITH_SUB, 0, - TCG_REG_TMP, TCG_REG_XZR, args[2], 0); - tcg_out_shiftrot_reg(s, SRR_ROR, ext, - args[0], args[1], TCG_REG_TMP); + tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2); + tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP); } break; + case INDEX_op_brcond_i32: + a1 = (int32_t)a1; + /* FALLTHRU */ case INDEX_op_brcond_i64: - ext = 1; /* fall through */ - case INDEX_op_brcond_i32: /* CMP 0, 1, cond(2), label 3 */ - tcg_out_cmp(s, ext, args[0], args[1], 0); - tcg_out_goto_label_cond(s, args[2], args[3]); + tcg_out_cmp(s, ext, a0, a1, const_args[1]); + tcg_out_goto_label_cond(s, a2, args[3]); break; - case INDEX_op_setcond_i64: - ext = 1; /* fall through */ case INDEX_op_setcond_i32: - tcg_out_cmp(s, ext, args[1], args[2], 0); - tcg_out_cset(s, 0, args[0], args[3]); + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_setcond_i64: + tcg_out_cmp(s, ext, a1, a2, c2); + /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */ + tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR, + TCG_REG_XZR, tcg_invert_cond(args[3])); + break; + + case INDEX_op_movcond_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_movcond_i64: + tcg_out_cmp(s, ext, a1, a2, c2); + tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]); break; case INDEX_op_qemu_ld8u: @@ -1300,45 +1537,84 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, 3); break; - case INDEX_op_bswap64_i64: - ext = 1; /* fall through */ case INDEX_op_bswap32_i64: + /* Despite the _i64, this is a 32-bit bswap. */ + ext = 0; + /* FALLTHRU */ + case INDEX_op_bswap64_i64: case INDEX_op_bswap32_i32: - tcg_out_rev(s, ext, args[0], args[1]); + tcg_out_rev(s, ext, a0, a1); break; case INDEX_op_bswap16_i64: case INDEX_op_bswap16_i32: - tcg_out_rev16(s, 0, args[0], args[1]); + tcg_out_rev16(s, 0, a0, a1); break; case INDEX_op_ext8s_i64: - ext = 1; /* fall through */ case INDEX_op_ext8s_i32: - tcg_out_sxt(s, ext, 0, args[0], args[1]); + tcg_out_sxt(s, ext, 0, a0, a1); break; case INDEX_op_ext16s_i64: - ext = 1; /* fall through */ case INDEX_op_ext16s_i32: - tcg_out_sxt(s, ext, 1, args[0], args[1]); + tcg_out_sxt(s, ext, 1, a0, a1); break; case INDEX_op_ext32s_i64: - tcg_out_sxt(s, 1, 2, args[0], args[1]); + tcg_out_sxt(s, 1, 2, a0, a1); break; case INDEX_op_ext8u_i64: case INDEX_op_ext8u_i32: - tcg_out_uxt(s, 0, args[0], args[1]); + tcg_out_uxt(s, 0, a0, a1); break; case INDEX_op_ext16u_i64: case INDEX_op_ext16u_i32: - tcg_out_uxt(s, 1, args[0], args[1]); + tcg_out_uxt(s, 1, a0, a1); break; case INDEX_op_ext32u_i64: - tcg_out_movr(s, 0, args[0], args[1]); + tcg_out_movr(s, 0, a0, a1); + break; + + case INDEX_op_deposit_i64: + case INDEX_op_deposit_i32: + tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]); break; + case INDEX_op_add2_i32: + tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), + (int32_t)args[4], args[5], const_args[4], + const_args[5], false); + break; + case INDEX_op_add2_i64: + tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4], + args[5], const_args[4], const_args[5], false); + break; + case INDEX_op_sub2_i32: + tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), + (int32_t)args[4], args[5], const_args[4], + const_args[5], true); + break; + case INDEX_op_sub2_i64: + tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4], + args[5], const_args[4], const_args[5], true); + break; + + case INDEX_op_muluh_i64: + tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_mulsh_i64: + tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); + break; + + case INDEX_op_mov_i64: + case INDEX_op_mov_i32: + case INDEX_op_movi_i64: + case INDEX_op_movi_i32: + /* Always implemented with tcg_out_mov/i, never with tcg_out_op. */ default: - tcg_abort(); /* opcode not implemented */ + /* Opcode not implemented. */ + tcg_abort(); } + +#undef REG0 } static const TCGTargetOpDef aarch64_op_defs[] = { @@ -1374,18 +1650,37 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_st32_i64, { "r", "r" } }, { INDEX_op_st_i64, { "r", "r" } }, - { INDEX_op_add_i32, { "r", "r", "r" } }, - { INDEX_op_add_i64, { "r", "r", "r" } }, - { INDEX_op_sub_i32, { "r", "r", "r" } }, - { INDEX_op_sub_i64, { "r", "r", "r" } }, + { INDEX_op_add_i32, { "r", "r", "rwA" } }, + { INDEX_op_add_i64, { "r", "r", "rA" } }, + { INDEX_op_sub_i32, { "r", "r", "rwA" } }, + { INDEX_op_sub_i64, { "r", "r", "rA" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mul_i64, { "r", "r", "r" } }, - { INDEX_op_and_i32, { "r", "r", "r" } }, - { INDEX_op_and_i64, { "r", "r", "r" } }, - { INDEX_op_or_i32, { "r", "r", "r" } }, - { INDEX_op_or_i64, { "r", "r", "r" } }, - { INDEX_op_xor_i32, { "r", "r", "r" } }, - { INDEX_op_xor_i64, { "r", "r", "r" } }, + { INDEX_op_div_i32, { "r", "r", "r" } }, + { INDEX_op_div_i64, { "r", "r", "r" } }, + { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_divu_i64, { "r", "r", "r" } }, + { INDEX_op_rem_i32, { "r", "r", "r" } }, + { INDEX_op_rem_i64, { "r", "r", "r" } }, + { INDEX_op_remu_i32, { "r", "r", "r" } }, + { INDEX_op_remu_i64, { "r", "r", "r" } }, + { INDEX_op_and_i32, { "r", "r", "rwL" } }, + { INDEX_op_and_i64, { "r", "r", "rL" } }, + { INDEX_op_or_i32, { "r", "r", "rwL" } }, + { INDEX_op_or_i64, { "r", "r", "rL" } }, + { INDEX_op_xor_i32, { "r", "r", "rwL" } }, + { INDEX_op_xor_i64, { "r", "r", "rL" } }, + { INDEX_op_andc_i32, { "r", "r", "rwL" } }, + { INDEX_op_andc_i64, { "r", "r", "rL" } }, + { INDEX_op_orc_i32, { "r", "r", "rwL" } }, + { INDEX_op_orc_i64, { "r", "r", "rL" } }, + { INDEX_op_eqv_i32, { "r", "r", "rwL" } }, + { INDEX_op_eqv_i64, { "r", "r", "rL" } }, + + { INDEX_op_neg_i32, { "r", "r" } }, + { INDEX_op_neg_i64, { "r", "r" } }, + { INDEX_op_not_i32, { "r", "r" } }, + { INDEX_op_not_i64, { "r", "r" } }, { INDEX_op_shl_i32, { "r", "r", "ri" } }, { INDEX_op_shr_i32, { "r", "r", "ri" } }, @@ -1398,10 +1693,12 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_rotl_i64, { "r", "r", "ri" } }, { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - { INDEX_op_brcond_i32, { "r", "r" } }, - { INDEX_op_setcond_i32, { "r", "r", "r" } }, - { INDEX_op_brcond_i64, { "r", "r" } }, - { INDEX_op_setcond_i64, { "r", "r", "r" } }, + { INDEX_op_brcond_i32, { "r", "rwA" } }, + { INDEX_op_brcond_i64, { "r", "rA" } }, + { INDEX_op_setcond_i32, { "r", "r", "rwA" } }, + { INDEX_op_setcond_i64, { "r", "r", "rA" } }, + { INDEX_op_movcond_i32, { "r", "r", "rwA", "rZ", "rZ" } }, + { INDEX_op_movcond_i64, { "r", "r", "rA", "rZ", "rZ" } }, { INDEX_op_qemu_ld8u, { "r", "l" } }, { INDEX_op_qemu_ld8s, { "r", "l" } }, @@ -1436,17 +1733,22 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_ext16u_i64, { "r", "r" } }, { INDEX_op_ext32u_i64, { "r", "r" } }, + { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, + { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, + + { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } }, + { INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, + { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } }, + { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, + + { INDEX_op_muluh_i64, { "r", "r", "r" } }, + { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { -1 }, }; static void tcg_target_init(TCGContext *s) { -#if !defined(CONFIG_USER_ONLY) - /* fail safe */ - if ((1ULL << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) { - tcg_abort(); - } -#endif tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); @@ -1500,9 +1802,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_store_pair(s, TCG_REG_FP, r, r + 1, idx); } - /* make stack space for TCG locals */ - tcg_out_subi(s, 1, TCG_REG_SP, TCG_REG_SP, + /* Make stack space for TCG locals. */ + tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN); + /* inform TCG about how to find TCG locals with register, offset, size */ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, CPU_TEMP_BUF_NLONGS * sizeof(long)); @@ -1519,8 +1822,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) tb_ret_addr = s->code_ptr; - /* remove TCG locals stack space */ - tcg_out_addi(s, 1, TCG_REG_SP, TCG_REG_SP, + /* Remove TCG locals stack space. */ + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN); /* restore registers x19..x28. diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 82ad919..988983e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -39,33 +39,33 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_div_i32 0 -#define TCG_TARGET_HAS_rem_i32 0 +#define TCG_TARGET_HAS_div_i32 1 +#define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_not_i32 0 -#define TCG_TARGET_HAS_neg_i32 0 +#define TCG_TARGET_HAS_not_i32 1 +#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 -#define TCG_TARGET_HAS_orc_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 +#define TCG_TARGET_HAS_orc_i32 1 +#define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_deposit_i32 0 -#define TCG_TARGET_HAS_movcond_i32 0 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_deposit_i32 1 +#define TCG_TARGET_HAS_movcond_i32 1 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 @@ -75,22 +75,22 @@ typedef enum { #define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 -#define TCG_TARGET_HAS_not_i64 0 -#define TCG_TARGET_HAS_neg_i64 0 +#define TCG_TARGET_HAS_not_i64 1 +#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_orc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_orc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_deposit_i64 0 -#define TCG_TARGET_HAS_movcond_i64 0 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_deposit_i64 1 +#define TCG_TARGET_HAS_movcond_i64 1 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 #define TCG_TARGET_HAS_muls2_i64 0 -#define TCG_TARGET_HAS_muluh_i64 0 -#define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_muluh_i64 1 +#define TCG_TARGET_HAS_mulsh_i64 1 enum { TCG_AREG0 = TCG_REG_X19, diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index cbd1c91..152335c 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -384,37 +384,47 @@ static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } -static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) { - if (check_fit_tl(arg, 13)) + tcg_target_long hi, lo; + + /* A 13-bit constant sign-extended to 64-bits. */ + if (check_fit_tl(arg, 13)) { tcg_out_movi_imm13(s, ret, arg); - else { - tcg_out_sethi(s, ret, arg); - if (arg & 0x3ff) - tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); + return; } -} -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ - /* All 32-bit constants, as well as 64-bit constants with - no high bits set go through movi_imm32. */ + /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32 - || (arg & ~(tcg_target_long)0xffffffff) == 0) { - tcg_out_movi_imm32(s, ret, arg); - } else if (check_fit_tl(arg, 13)) { - /* A 13-bit constant sign-extended to 64-bits. */ - tcg_out_movi_imm13(s, ret, arg); - } else if (check_fit_tl(arg, 32)) { - /* A 32-bit constant sign-extended to 64-bits. */ + || (arg & ~0xffffffffu) == 0) { + tcg_out_sethi(s, ret, arg); + if (arg & 0x3ff) { + tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); + } + return; + } + + /* A 32-bit constant sign-extended to 64-bits. */ + if (check_fit_tl(arg, 32)) { tcg_out_sethi(s, ret, ~arg); tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); + return; + } + + /* A 64-bit constant decomposed into 2 32-bit pieces. */ + lo = (int32_t)arg; + if (check_fit_tl(lo, 13)) { + hi = (arg - lo) >> 31 >> 1; + tcg_out_movi(s, TCG_TYPE_I32, ret, hi); + tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); + tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); } else { - tcg_out_movi_imm32(s, ret, arg >> (TCG_TARGET_REG_BITS / 2)); + hi = arg >> 31 >> 1; + tcg_out_movi(s, TCG_TYPE_I32, ret, hi); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); - tcg_out_movi_imm32(s, TCG_REG_T2, arg); tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); } } @@ -449,13 +459,14 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); } -static inline void tcg_out_ld_ptr(TCGContext *s, int ret, - tcg_target_long arg) +static inline void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) { + TCGReg base = TCG_REG_G0; if (!check_fit_tl(arg, 10)) { tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); + base = ret; } - tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); + tcg_out_ld(s, TCG_TYPE_PTR, ret, base, arg & 0x3ff); } static inline void tcg_out_sety(TCGContext *s, int rs) @@ -480,19 +491,6 @@ static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) } } -static inline void tcg_out_andi(TCGContext *s, int rd, int rs, - tcg_target_long val) -{ - if (val != 0) { - if (check_fit_tl(val, 13)) - tcg_out_arithi(s, rd, rs, val, ARITH_AND); - else { - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T1, val); - tcg_out_arith(s, rd, rs, TCG_REG_T1, ARITH_AND); - } - } -} - static void tcg_out_div32(TCGContext *s, int rd, int rs1, int val2, int val2const, int uns) { @@ -796,6 +794,110 @@ static void tcg_out_addsub2(TCGContext *s, TCGArg rl, TCGArg rh, tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); } +static inline void tcg_out_calli(TCGContext *s, uintptr_t dest) +{ + intptr_t disp = dest - (uintptr_t)s->code_ptr; + + if (disp == (int32_t)disp) { + tcg_out32(s, CALL | (uint32_t)disp >> 2); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, dest & ~0xfff); + tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, dest & 0xfff, JMPL); + } +} + +#ifdef CONFIG_SOFTMMU +static uintptr_t qemu_ld_trampoline[16]; +static uintptr_t qemu_st_trampoline[16]; + +static void build_trampolines(TCGContext *s) +{ + static uintptr_t const qemu_ld_helpers[16] = { + [MO_UB] = (uintptr_t)helper_ret_ldub_mmu, + [MO_SB] = (uintptr_t)helper_ret_ldsb_mmu, + [MO_LEUW] = (uintptr_t)helper_le_lduw_mmu, + [MO_LESW] = (uintptr_t)helper_le_ldsw_mmu, + [MO_LEUL] = (uintptr_t)helper_le_ldul_mmu, + [MO_LEQ] = (uintptr_t)helper_le_ldq_mmu, + [MO_BEUW] = (uintptr_t)helper_be_lduw_mmu, + [MO_BESW] = (uintptr_t)helper_be_ldsw_mmu, + [MO_BEUL] = (uintptr_t)helper_be_ldul_mmu, + [MO_BEQ] = (uintptr_t)helper_be_ldq_mmu, + }; + static uintptr_t const qemu_st_helpers[16] = { + [MO_UB] = (uintptr_t)helper_ret_stb_mmu, + [MO_LEUW] = (uintptr_t)helper_le_stw_mmu, + [MO_LEUL] = (uintptr_t)helper_le_stl_mmu, + [MO_LEQ] = (uintptr_t)helper_le_stq_mmu, + [MO_BEUW] = (uintptr_t)helper_be_stw_mmu, + [MO_BEUL] = (uintptr_t)helper_be_stl_mmu, + [MO_BEQ] = (uintptr_t)helper_be_stq_mmu, + }; + + int i; + TCGReg ra; + uintptr_t tramp; + + for (i = 0; i < 16; ++i) { + if (qemu_ld_helpers[i] == 0) { + continue; + } + + /* May as well align the trampoline. */ + tramp = (uintptr_t)s->code_ptr; + while (tramp & 15) { + tcg_out_nop(s); + tramp += 4; + } + qemu_ld_trampoline[i] = tramp; + + /* Find the retaddr argument register. */ + ra = TCG_REG_O3 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS); + + /* Set the retaddr operand. */ + tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); + /* Set the env operand. */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); + /* Tail call. */ + tcg_out_calli(s, qemu_ld_helpers[i]); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + } + + for (i = 0; i < 16; ++i) { + if (qemu_st_helpers[i] == 0) { + continue; + } + + /* May as well align the trampoline. */ + tramp = (uintptr_t)s->code_ptr; + while (tramp & 15) { + tcg_out_nop(s); + tramp += 4; + } + qemu_st_trampoline[i] = tramp; + + /* Find the retaddr argument. For 32-bit, this may be past the + last argument register, and need passing on the stack. */ + ra = (TCG_REG_O4 + + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) + + (TCG_TARGET_REG_BITS == 32 && (i & MO_SIZE) == MO_64)); + + /* Set the retaddr operand. */ + if (ra >= TCG_REG_O6) { + tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET); + ra = TCG_REG_G1; + } + tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); + /* Set the env operand. */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); + /* Tail call. */ + tcg_out_calli(s, qemu_st_helpers[i]); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + } +} +#endif + /* Generate global QEMU prologue and epilogue code */ static void tcg_target_qemu_prologue(TCGContext *s) { @@ -823,39 +925,22 @@ static void tcg_target_qemu_prologue(TCGContext *s) } #endif - tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) | - INSN_RS2(TCG_REG_G0)); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); /* delay slot */ tcg_out_nop(s); /* No epilogue required. We issue ret + restore directly in the TB. */ + +#ifdef CONFIG_SOFTMMU + build_trampolines(s); +#endif } #if defined(CONFIG_SOFTMMU) - -/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, - int mmu_idx) */ -static const void * const qemu_ld_helpers[4] = { - helper_ldb_mmu, - helper_ldw_mmu, - helper_ldl_mmu, - helper_ldq_mmu, -}; - -/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, - uintxx_t val, int mmu_idx) */ -static const void * const qemu_st_helpers[4] = { - helper_stb_mmu, - helper_stw_mmu, - helper_stl_mmu, - helper_stq_mmu, -}; - /* Perform the TLB load and compare. Inputs: - ADDRLO_IDX contains the index into ARGS of the low part of the - address; the high part of the address is at ADDR_LOW_IDX+1. + ADDRLO and ADDRHI contain the possible two parts of the address. MEM_INDEX and S_BITS are the memory context and log2 size of the load. @@ -865,32 +950,38 @@ static const void * const qemu_st_helpers[4] = { The result of the TLB comparison is in %[ix]cc. The sanitized address is in the returned register, maybe %o0. The TLB addend is in %o1. */ -static int tcg_out_tlb_load(TCGContext *s, int addrlo_idx, int mem_index, - int s_bits, const TCGArg *args, int which) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + int mem_index, TCGMemOp s_bits, int which) { - const int addrlo = args[addrlo_idx]; - const int r0 = TCG_REG_O0; - const int r1 = TCG_REG_O1; - const int r2 = TCG_REG_O2; - int addr = addrlo; + const TCGReg r0 = TCG_REG_O0; + const TCGReg r1 = TCG_REG_O1; + const TCGReg r2 = TCG_REG_O2; + TCGReg addr = addrlo; int tlb_ofs; if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) { /* Assemble the 64-bit address in R0. */ tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL); - tcg_out_arithi(s, r1, args[addrlo_idx + 1], 32, SHIFT_SLLX); + tcg_out_arithi(s, r1, addrhi, 32, SHIFT_SLLX); tcg_out_arith(s, r0, r0, r1, ARITH_OR); + addr = r0; } - /* Shift the page number down to tlb-entry. */ - tcg_out_arithi(s, r1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, SHIFT_SRL); + /* Shift the page number down. */ + tcg_out_arithi(s, r1, addrlo, TARGET_PAGE_BITS, SHIFT_SRL); /* Mask out the page offset, except for the required alignment. */ - tcg_out_andi(s, r0, addr, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_T1, + TARGET_PAGE_MASK | ((1 << s_bits) - 1)); - /* Compute tlb index, modulo tlb size. */ - tcg_out_andi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); + /* Mask the tlb index. */ + tcg_out_arithi(s, r1, r1, CPU_TLB_SIZE - 1, ARITH_AND); + + /* Mask page, part 2. */ + tcg_out_arith(s, r0, addr, TCG_REG_T1, ARITH_AND); + + /* Shift the tlb index into place. */ + tcg_out_arithi(s, r1, r1, CPU_TLB_ENTRY_BITS, SHIFT_SLL); /* Relative to the current ENV. */ tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD); @@ -898,8 +989,8 @@ static int tcg_out_tlb_load(TCGContext *s, int addrlo_idx, int mem_index, /* Find a base address that can load both tlb comparator and addend. */ tlb_ofs = offsetof(CPUArchState, tlb_table[mem_index][0]); if (!check_fit_tl(tlb_ofs + sizeof(CPUTLBEntry), 13)) { - tcg_out_addi(s, r1, tlb_ofs); - tlb_ofs = 0; + tcg_out_addi(s, r1, tlb_ofs & ~0x3ff); + tlb_ofs &= 0x3ff; } /* Load the tlb comparator and the addend. */ @@ -918,56 +1009,71 @@ static int tcg_out_tlb_load(TCGContext *s, int addrlo_idx, int mem_index, } #endif /* CONFIG_SOFTMMU */ -static const int qemu_ld_opc[8] = { -#ifdef TARGET_WORDS_BIGENDIAN - LDUB, LDUH, LDUW, LDX, LDSB, LDSH, LDSW, LDX -#else - LDUB, LDUH_LE, LDUW_LE, LDX_LE, LDSB, LDSH_LE, LDSW_LE, LDX_LE -#endif +static const int qemu_ld_opc[16] = { + [MO_UB] = LDUB, + [MO_SB] = LDSB, + + [MO_BEUW] = LDUH, + [MO_BESW] = LDSH, + [MO_BEUL] = LDUW, + [MO_BESL] = LDSW, + [MO_BEQ] = LDX, + + [MO_LEUW] = LDUH_LE, + [MO_LESW] = LDSH_LE, + [MO_LEUL] = LDUW_LE, + [MO_LESL] = LDSW_LE, + [MO_LEQ] = LDX_LE, }; -static const int qemu_st_opc[4] = { -#ifdef TARGET_WORDS_BIGENDIAN - STB, STH, STW, STX -#else - STB, STH_LE, STW_LE, STX_LE -#endif +static const int qemu_st_opc[16] = { + [MO_UB] = STB, + + [MO_BEUW] = STH, + [MO_BEUL] = STW, + [MO_BEQ] = STX, + + [MO_LEUW] = STH_LE, + [MO_LEUL] = STW_LE, + [MO_LEQ] = STX_LE, }; -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { - int addrlo_idx = 1, datalo, datahi, addr_reg; + TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGMemOp memop, s_bits; #if defined(CONFIG_SOFTMMU) - int memi_idx, memi, s_bits, n; + TCGReg addrz, param; + uintptr_t func; + int memi; uint32_t *label_ptr[2]; #endif - datahi = datalo = args[0]; - if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { - datahi = args[1]; - addrlo_idx = 2; - } + datalo = *args++; + datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); + memop = *args++; + s_bits = memop & MO_SIZE; #if defined(CONFIG_SOFTMMU) - memi_idx = addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS); - memi = args[memi_idx]; - s_bits = sizeop & 3; - - addr_reg = tcg_out_tlb_load(s, addrlo_idx, memi, s_bits, args, - offsetof(CPUTLBEntry, addr_read)); + memi = *args++; + addrz = tcg_out_tlb_load(s, addrlo, addrhi, memi, s_bits, + offsetof(CPUTLBEntry, addr_read)); - if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { + if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { int reg64; /* bne,pn %[xi]cc, label0 */ label_ptr[0] = (uint32_t *)s->code_ptr; tcg_out_bpcc0(s, COND_NE, BPCC_PN | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); + tcg_out_nop(s); /* TLB Hit. */ /* Load all 64-bits into an O/G register. */ reg64 = (datalo < 16 ? datalo : TCG_REG_O0); - tcg_out_ldst_rr(s, reg64, addr_reg, TCG_REG_O1, qemu_ld_opc[sizeop]); + tcg_out_ldst_rr(s, reg64, addrz, TCG_REG_O1, qemu_ld_opc[memop]); /* Move the two 32-bit pieces into the destination registers. */ tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX); @@ -989,7 +1095,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop) tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); /* delay slot */ - tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_O1, qemu_ld_opc[sizeop]); + tcg_out_ldst_rr(s, datalo, addrz, TCG_REG_O1, qemu_ld_opc[memop]); } /* TLB Miss. */ @@ -998,103 +1104,93 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop) *label_ptr[0] |= INSN_OFF19((unsigned long)s->code_ptr - (unsigned long)label_ptr[0]); } - n = 0; - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0); + + param = TCG_REG_O1; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], - args[addrlo_idx + 1]); + tcg_out_mov(s, TCG_TYPE_REG, param++, addrhi); } - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], - args[addrlo_idx]); + tcg_out_mov(s, TCG_TYPE_REG, param++, addrlo); - /* qemu_ld_helper[s_bits](arg0, arg1) */ - tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits] - - (tcg_target_ulong)s->code_ptr) >> 2) - & 0x3fffffff)); + /* We use the helpers to extend SB and SW data, leaving the case + of SL needing explicit extending below. */ + if ((memop & ~MO_BSWAP) == MO_SL) { + func = qemu_ld_trampoline[memop & ~MO_SIGN]; + } else { + func = qemu_ld_trampoline[memop]; + } + assert(func != 0); + tcg_out_calli(s, func); /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[n], memi); - - n = tcg_target_call_oarg_regs[0]; - /* datalo = sign_extend(arg0) */ - switch (sizeop) { - case 0 | 4: - /* Recall that SRA sign extends from bit 31 through bit 63. */ - tcg_out_arithi(s, datalo, n, 24, SHIFT_SLL); - tcg_out_arithi(s, datalo, datalo, 24, SHIFT_SRA); - break; - case 1 | 4: - tcg_out_arithi(s, datalo, n, 16, SHIFT_SLL); - tcg_out_arithi(s, datalo, datalo, 16, SHIFT_SRA); - break; - case 2 | 4: - tcg_out_arithi(s, datalo, n, 0, SHIFT_SRA); + tcg_out_movi(s, TCG_TYPE_I32, param, memi); + + switch (memop & ~MO_BSWAP) { + case MO_SL: + tcg_out_arithi(s, datalo, TCG_REG_O0, 0, SHIFT_SRA); break; - case 3: + case MO_Q: if (TCG_TARGET_REG_BITS == 32) { - tcg_out_mov(s, TCG_TYPE_REG, datahi, n); - tcg_out_mov(s, TCG_TYPE_REG, datalo, n + 1); + tcg_out_mov(s, TCG_TYPE_REG, datahi, TCG_REG_O0); + tcg_out_mov(s, TCG_TYPE_REG, datalo, TCG_REG_O1); break; } /* FALLTHRU */ - case 0: - case 1: - case 2: default: /* mov */ - tcg_out_mov(s, TCG_TYPE_REG, datalo, n); + tcg_out_mov(s, TCG_TYPE_REG, datalo, TCG_REG_O0); break; } *label_ptr[1] |= INSN_OFF19((unsigned long)s->code_ptr - (unsigned long)label_ptr[1]); #else - addr_reg = args[addrlo_idx]; if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) { - tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL); - addr_reg = TCG_REG_T1; + tcg_out_arithi(s, TCG_REG_T1, addrlo, 0, SHIFT_SRL); + addrlo = TCG_REG_T1; } - if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { + if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { int reg64 = (datalo < 16 ? datalo : TCG_REG_O0); - tcg_out_ldst_rr(s, reg64, addr_reg, + tcg_out_ldst_rr(s, reg64, addrlo, (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), - qemu_ld_opc[sizeop]); + qemu_ld_opc[memop]); tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX); if (reg64 != datalo) { tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64); } } else { - tcg_out_ldst_rr(s, datalo, addr_reg, + tcg_out_ldst_rr(s, datalo, addrlo, (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), - qemu_ld_opc[sizeop]); + qemu_ld_opc[memop]); } #endif /* CONFIG_SOFTMMU */ } -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { - int addrlo_idx = 1, datalo, datahi, addr_reg; + TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGMemOp memop, s_bits; #if defined(CONFIG_SOFTMMU) - int memi_idx, memi, n, datafull; + TCGReg addrz, datafull, param; + uintptr_t func; + int memi; uint32_t *label_ptr; #endif - datahi = datalo = args[0]; - if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { - datahi = args[1]; - addrlo_idx = 2; - } + datalo = *args++; + datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); + memop = *args++; + s_bits = memop & MO_SIZE; #if defined(CONFIG_SOFTMMU) - memi_idx = addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS); - memi = args[memi_idx]; - - addr_reg = tcg_out_tlb_load(s, addrlo_idx, memi, sizeop, args, - offsetof(CPUTLBEntry, addr_write)); + memi = *args++; + addrz = tcg_out_tlb_load(s, addrlo, addrhi, memi, s_bits, + offsetof(CPUTLBEntry, addr_write)); datafull = datalo; - if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { + if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { /* Reconstruct the full 64-bit value. */ tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL); tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX); @@ -1109,47 +1205,42 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop) tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); /* delay slot */ - tcg_out_ldst_rr(s, datafull, addr_reg, TCG_REG_O1, qemu_st_opc[sizeop]); + tcg_out_ldst_rr(s, datafull, addrz, TCG_REG_O1, qemu_st_opc[memop]); /* TLB Miss. */ - n = 0; - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0); + param = TCG_REG_O1; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], - args[addrlo_idx + 1]); + tcg_out_mov(s, TCG_TYPE_REG, param++, addrhi); } - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], - args[addrlo_idx]); - if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], datahi); + tcg_out_mov(s, TCG_TYPE_REG, param++, addrlo); + if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { + tcg_out_mov(s, TCG_TYPE_REG, param++, datahi); } - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], datalo); + tcg_out_mov(s, TCG_TYPE_REG, param++, datalo); - /* qemu_st_helper[s_bits](arg0, arg1, arg2) */ - tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[sizeop] - - (tcg_target_ulong)s->code_ptr) >> 2) - & 0x3fffffff)); + func = qemu_st_trampoline[memop]; + assert(func != 0); + tcg_out_calli(s, func); /* delay slot */ - tcg_out_movi(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n], memi); + tcg_out_movi(s, TCG_TYPE_REG, param, memi); *label_ptr |= INSN_OFF19((unsigned long)s->code_ptr - (unsigned long)label_ptr); #else - addr_reg = args[addrlo_idx]; if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) { - tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL); - addr_reg = TCG_REG_T1; + tcg_out_arithi(s, TCG_REG_T1, addrlo, 0, SHIFT_SRL); + addrlo = TCG_REG_T1; } - if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { + if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL); tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX); tcg_out_arith(s, TCG_REG_O2, TCG_REG_T1, TCG_REG_O2, ARITH_OR); datalo = TCG_REG_O2; } - tcg_out_ldst_rr(s, datalo, addr_reg, + tcg_out_ldst_rr(s, datalo, addrlo, (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), - qemu_st_opc[sizeop]); + qemu_st_opc[memop]); #endif /* CONFIG_SOFTMMU */ } @@ -1161,8 +1252,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, switch (opc) { case INDEX_op_exit_tb: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]); - tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | - INSN_IMM13(8)); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, JMPL); tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | INSN_RS2(TCG_REG_G0)); break; @@ -1175,24 +1265,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out32(s, CALL | (old_insn & ~INSN_OP(-1))); } else { /* indirect jump method */ - tcg_out_ld_ptr(s, TCG_REG_T1, - (tcg_target_long)(s->tb_next + args[0])); - tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_T1) | - INSN_RS2(TCG_REG_G0)); + tcg_out_ld_ptr(s, TCG_REG_T1, (uintptr_t)(s->tb_next + args[0])); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL); } tcg_out_nop(s); s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; break; case INDEX_op_call: if (const_args[0]) { - tcg_out32(s, CALL | ((((tcg_target_ulong)args[0] - - (tcg_target_ulong)s->code_ptr) >> 2) - & 0x3fffffff)); + tcg_out_calli(s, args[0]); } else { - tcg_out_ld_ptr(s, TCG_REG_T1, - (tcg_target_long)(s->tb_next + args[0])); - tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_T1) | - INSN_RS2(TCG_REG_G0)); + tcg_out_arithi(s, TCG_REG_O7, args[0], 0, JMPL); } /* delay slot */ tcg_out_nop(s); @@ -1294,15 +1377,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1); break; - case INDEX_op_rem_i32: - case INDEX_op_remu_i32: - tcg_out_div32(s, TCG_REG_T1, args[1], args[2], const_args[2], - opc == INDEX_op_remu_i32); - tcg_out_arithc(s, TCG_REG_T1, TCG_REG_T1, args[2], const_args[2], - ARITH_UMUL); - tcg_out_arith(s, args[0], args[1], TCG_REG_T1, ARITH_SUB); - break; - case INDEX_op_brcond_i32: tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1], args[3]); @@ -1345,44 +1419,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_rdy(s, args[1]); break; - case INDEX_op_qemu_ld8u: + case INDEX_op_qemu_ld_i32: tcg_out_qemu_ld(s, args, 0); break; - case INDEX_op_qemu_ld8s: - tcg_out_qemu_ld(s, args, 0 | 4); - break; - case INDEX_op_qemu_ld16u: + case INDEX_op_qemu_ld_i64: tcg_out_qemu_ld(s, args, 1); break; - case INDEX_op_qemu_ld16s: - tcg_out_qemu_ld(s, args, 1 | 4); - break; - case INDEX_op_qemu_ld32: -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_qemu_ld32u: -#endif - tcg_out_qemu_ld(s, args, 2); - break; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_qemu_ld32s: - tcg_out_qemu_ld(s, args, 2 | 4); - break; -#endif - case INDEX_op_qemu_ld64: - tcg_out_qemu_ld(s, args, 3); - break; - case INDEX_op_qemu_st8: + case INDEX_op_qemu_st_i32: tcg_out_qemu_st(s, args, 0); break; - case INDEX_op_qemu_st16: + case INDEX_op_qemu_st_i64: tcg_out_qemu_st(s, args, 1); break; - case INDEX_op_qemu_st32: - tcg_out_qemu_st(s, args, 2); - break; - case INDEX_op_qemu_st64: - tcg_out_qemu_st(s, args, 3); - break; #if TCG_TARGET_REG_BITS == 64 case INDEX_op_movi_i64: @@ -1418,27 +1466,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_divu_i64: c = ARITH_UDIVX; goto gen_arith; - case INDEX_op_rem_i64: - case INDEX_op_remu_i64: - tcg_out_arithc(s, TCG_REG_T1, args[1], args[2], const_args[2], - opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX); - tcg_out_arithc(s, TCG_REG_T1, TCG_REG_T1, args[2], const_args[2], - ARITH_MULX); - tcg_out_arith(s, args[0], args[1], TCG_REG_T1, ARITH_SUB); - break; case INDEX_op_ext32s_i64: - if (const_args[1]) { - tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]); - } else { - tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA); - } + tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA); break; case INDEX_op_ext32u_i64: - if (const_args[1]) { - tcg_out_movi_imm32(s, args[0], args[1]); - } else { - tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL); - } + tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL); break; case INDEX_op_brcond_i64: @@ -1489,8 +1521,6 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_mul_i32, { "r", "rZ", "rJ" } }, { INDEX_op_div_i32, { "r", "rZ", "rJ" } }, { INDEX_op_divu_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_rem_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_remu_i32, { "r", "rZ", "rJ" } }, { INDEX_op_sub_i32, { "r", "rZ", "rJ" } }, { INDEX_op_and_i32, { "r", "rZ", "rJ" } }, { INDEX_op_andc_i32, { "r", "rZ", "rJ" } }, @@ -1537,8 +1567,6 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_mul_i64, { "r", "rZ", "rJ" } }, { INDEX_op_div_i64, { "r", "rZ", "rJ" } }, { INDEX_op_divu_i64, { "r", "rZ", "rJ" } }, - { INDEX_op_rem_i64, { "r", "rZ", "rJ" } }, - { INDEX_op_remu_i64, { "r", "rZ", "rJ" } }, { INDEX_op_sub_i64, { "r", "rZ", "rJ" } }, { INDEX_op_and_i64, { "r", "rZ", "rJ" } }, { INDEX_op_andc_i64, { "r", "rZ", "rJ" } }, @@ -1553,8 +1581,8 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_neg_i64, { "r", "rJ" } }, { INDEX_op_not_i64, { "r", "rJ" } }, - { INDEX_op_ext32s_i64, { "r", "ri" } }, - { INDEX_op_ext32u_i64, { "r", "ri" } }, + { INDEX_op_ext32s_i64, { "r", "r" } }, + { INDEX_op_ext32u_i64, { "r", "r" } }, { INDEX_op_brcond_i64, { "rZ", "rJ" } }, { INDEX_op_setcond_i64, { "r", "rZ", "rJ" } }, @@ -1562,43 +1590,20 @@ static const TCGTargetOpDef sparc_op_defs[] = { #endif #if TCG_TARGET_REG_BITS == 64 - { INDEX_op_qemu_ld8u, { "r", "L" } }, - { INDEX_op_qemu_ld8s, { "r", "L" } }, - { INDEX_op_qemu_ld16u, { "r", "L" } }, - { INDEX_op_qemu_ld16s, { "r", "L" } }, - { INDEX_op_qemu_ld32, { "r", "L" } }, - { INDEX_op_qemu_ld32u, { "r", "L" } }, - { INDEX_op_qemu_ld32s, { "r", "L" } }, - { INDEX_op_qemu_ld64, { "r", "L" } }, - - { INDEX_op_qemu_st8, { "L", "L" } }, - { INDEX_op_qemu_st16, { "L", "L" } }, - { INDEX_op_qemu_st32, { "L", "L" } }, - { INDEX_op_qemu_st64, { "L", "L" } }, + { INDEX_op_qemu_ld_i32, { "r", "L" } }, + { INDEX_op_qemu_ld_i64, { "r", "L" } }, + { INDEX_op_qemu_st_i32, { "L", "L" } }, + { INDEX_op_qemu_st_i64, { "L", "L" } }, #elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS - { INDEX_op_qemu_ld8u, { "r", "L" } }, - { INDEX_op_qemu_ld8s, { "r", "L" } }, - { INDEX_op_qemu_ld16u, { "r", "L" } }, - { INDEX_op_qemu_ld16s, { "r", "L" } }, - { INDEX_op_qemu_ld32, { "r", "L" } }, - { INDEX_op_qemu_ld64, { "r", "r", "L" } }, - - { INDEX_op_qemu_st8, { "L", "L" } }, - { INDEX_op_qemu_st16, { "L", "L" } }, - { INDEX_op_qemu_st32, { "L", "L" } }, - { INDEX_op_qemu_st64, { "L", "L", "L" } }, + { INDEX_op_qemu_ld_i32, { "r", "L" } }, + { INDEX_op_qemu_ld_i64, { "r", "r", "L" } }, + { INDEX_op_qemu_st_i32, { "L", "L" } }, + { INDEX_op_qemu_st_i64, { "L", "L", "L" } }, #else - { INDEX_op_qemu_ld8u, { "r", "L", "L" } }, - { INDEX_op_qemu_ld8s, { "r", "L", "L" } }, - { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, - { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, - { INDEX_op_qemu_ld32, { "r", "L", "L" } }, - { INDEX_op_qemu_ld64, { "L", "L", "L", "L" } }, - - { INDEX_op_qemu_st8, { "L", "L", "L" } }, - { INDEX_op_qemu_st16, { "L", "L", "L" } }, - { INDEX_op_qemu_st32, { "L", "L", "L" } }, - { INDEX_op_qemu_st64, { "L", "L", "L", "L" } }, + { INDEX_op_qemu_ld_i32, { "r", "L", "L" } }, + { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } }, + { INDEX_op_qemu_st_i32, { "L", "L", "L" } }, + { INDEX_op_qemu_st_i64, { "L", "L", "L", "L" } }, #endif { -1 }, @@ -1679,7 +1684,7 @@ static DebugFrame debug_frame = { void tcg_register_jit(void *buf, size_t buf_size) { - debug_frame.fde.func_start = (tcg_target_long) buf; + debug_frame.fde.func_start = (uintptr_t)buf; debug_frame.fde.func_len = buf_size; tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); @@ -1688,14 +1693,12 @@ void tcg_register_jit(void *buf, size_t buf_size) void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) { uint32_t *ptr = (uint32_t *)jmp_addr; - tcg_target_long disp = (tcg_target_long)(addr - jmp_addr) >> 2; + uintptr_t disp = addr - jmp_addr; /* We can reach the entire address space for 32-bit. For 64-bit the code_gen_buffer can't be larger than 2GB. */ - if (TCG_TARGET_REG_BITS == 64 && !check_fit_tl(disp, 30)) { - tcg_abort(); - } + assert(disp == (int32_t)disp); - *ptr = CALL | (disp & 0x3fffffff); + *ptr = CALL | (uint32_t)disp >> 2; flush_icache_range(jmp_addr, jmp_addr + 4); } diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 00f3a18..3abf1b4 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -94,7 +94,7 @@ typedef enum { /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 -#define TCG_TARGET_HAS_rem_i32 1 +#define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_ext8s_i32 0 #define TCG_TARGET_HAS_ext16s_i32 0 @@ -120,7 +120,7 @@ typedef enum { #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_div_i64 1 -#define TCG_TARGET_HAS_rem_i64 1 +#define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_rot_i64 0 #define TCG_TARGET_HAS_ext8s_i64 0 #define TCG_TARGET_HAS_ext16s_i64 0 @@ -148,7 +148,7 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i64 0 #endif -#define TCG_TARGET_HAS_new_ldst 0 +#define TCG_TARGET_HAS_new_ldst 1 #define TCG_AREG0 TCG_REG_I0 diff --git a/tests/Makefile b/tests/Makefile index b17d41e..2d021fb 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -35,6 +35,7 @@ check-unit-y += tests/test-visitor-serialization$(EXESUF) check-unit-y += tests/test-iov$(EXESUF) gcov-files-test-iov-y = util/iov.c check-unit-y += tests/test-aio$(EXESUF) +check-unit-y += tests/test-rfifolock$(EXESUF) check-unit-y += tests/test-throttle$(EXESUF) gcov-files-test-aio-$(CONFIG_WIN32) = aio-win32.c gcov-files-test-aio-$(CONFIG_POSIX) = aio-posix.c @@ -69,9 +70,24 @@ gcov-files-ipack-y += hw/ipack/ipack.c check-qtest-ipack-y += tests/ipoctal232-test$(EXESUF) gcov-files-ipack-y += hw/char/ipoctal232.c +check-qtest-virtioserial-y += tests/virtio-console-test$(EXESUF) +gcov-files-virtioserial-y += hw/char/virtio-console.c + gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio.c check-qtest-virtio-y += tests/virtio-net-test$(EXESUF) gcov-files-virtio-y += i386-softmmu/hw/net/virtio-net.c +check-qtest-virtio-y += tests/virtio-balloon-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio-balloon.c +check-qtest-virtio-y += tests/virtio-blk-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/block/virtio-blk.c +check-qtest-virtio-y += tests/virtio-rng-test$(EXESUF) +gcov-files-virtio-y += hw/virtio/virtio-rng.c +check-qtest-virtio-y += tests/virtio-scsi-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/scsi/virtio-scsi.c +check-qtest-virtio-y += tests/virtio-serial-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/char/virtio-serial-bus.c +check-qtest-virtio-y += $(check-qtest-virtioserial-y) +gcov-files-virtio-y += $(gcov-files-virtioserial-y) check-qtest-pci-y += tests/e1000-test$(EXESUF) gcov-files-pci-y += hw/net/e1000.c @@ -87,9 +103,9 @@ gcov-files-pci-y += hw/net/ne2000.c check-qtest-pci-y += $(check-qtest-virtio-y) gcov-files-pci-y += $(gcov-files-virtio-y) hw/virtio/virtio-pci.c check-qtest-pci-y += tests/tpci200-test$(EXESUF) -gcov-files-pci-y += hw/char/tpci200.c +gcov-files-pci-y += hw/ipack/tpci200.c check-qtest-pci-y += $(check-qtest-ipack-y) -gcov-files-pci-y += $(gcov-files-ipack-y) hw/ipack/tpci200.c +gcov-files-pci-y += $(gcov-files-ipack-y) check-qtest-i386-y = tests/endianness-test$(EXESUF) check-qtest-i386-y += tests/fdc-test$(EXESUF) @@ -129,6 +145,8 @@ check-qtest-arm-y = tests/tmp105-test$(EXESUF) gcov-files-arm-y += hw/misc/tmp105.c check-qtest-ppc-y += tests/boot-order-test$(EXESUF) check-qtest-ppc64-y += tests/boot-order-test$(EXESUF) +check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF) +gcov-files-ppc64-y += ppc64-softmmu/hw/ppc/spapr_pci.c check-qtest-microblazeel-y = $(check-qtest-microblaze-y) check-qtest-xtensaeb-y = $(check-qtest-xtensa-y) @@ -142,7 +160,11 @@ check-qapi-schema-y := $(addprefix tests/qapi-schema/, \ missing-comma-object.json non-objects.json \ qapi-schema-test.json quoted-structural-chars.json \ trailing-comma-list.json trailing-comma-object.json \ - unclosed-list.json unclosed-object.json unclosed-string.json) + unclosed-list.json unclosed-object.json unclosed-string.json \ + duplicate-key.json union-invalid-base.json flat-union-no-base.json \ + flat-union-invalid-discriminator.json \ + flat-union-invalid-branch-key.json flat-union-reverse-define.json \ + flat-union-string-discriminator.json) GENERATED_HEADERS += tests/test-qapi-types.h tests/test-qapi-visit.h tests/test-qmp-commands.h @@ -172,6 +194,7 @@ tests/check-qjson$(EXESUF): tests/check-qjson.o libqemuutil.a libqemustub.a tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o $(qom-core-obj) libqemuutil.a libqemustub.a tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(block-obj-y) libqemuutil.a libqemustub.a tests/test-aio$(EXESUF): tests/test-aio.o $(block-obj-y) libqemuutil.a libqemustub.a +tests/test-rfifolock$(EXESUF): tests/test-rfifolock.o libqemuutil.a libqemustub.a tests/test-throttle$(EXESUF): tests/test-throttle.o $(block-obj-y) libqemuutil.a libqemustub.a tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(block-obj-y) libqemuutil.a libqemustub.a tests/test-iov$(EXESUF): tests/test-iov.o libqemuutil.a @@ -183,6 +206,7 @@ tests/test-int128$(EXESUF): tests/test-int128.o tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ hw/core/irq.o \ + hw/core/fw-path-provider.o \ $(qom-core-obj) \ $(test-qapi-obj-y) \ libqemuutil.a libqemustub.a @@ -221,6 +245,7 @@ libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o tests/rtc-test$(EXESUF): tests/rtc-test.o tests/m48t59-test$(EXESUF): tests/m48t59-test.o tests/endianness-test$(EXESUF): tests/endianness-test.o +tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y) tests/fdc-test$(EXESUF): tests/fdc-test.o tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y) tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o @@ -235,7 +260,13 @@ tests/pcnet-test$(EXESUF): tests/pcnet-test.o tests/eepro100-test$(EXESUF): tests/eepro100-test.o tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o tests/ne2000-test$(EXESUF): tests/ne2000-test.o +tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o +tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o +tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o +tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o +tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o +tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o tests/tpci200-test$(EXESUF): tests/tpci200-test.o tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o tests/qom-test$(EXESUF): tests/qom-test.o diff --git a/tests/libqtest.c b/tests/libqtest.c index f587d36..b03b57a 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -34,6 +34,7 @@ #include "qapi/qmp/json-parser.h" #define MAX_IRQ 256 +#define SOCKET_TIMEOUT 5 QTestState *global_qtest; @@ -78,12 +79,16 @@ static int socket_accept(int sock) struct sockaddr_un addr; socklen_t addrlen; int ret; + struct timeval timeout = { .tv_sec = SOCKET_TIMEOUT, + .tv_usec = 0 }; + + setsockopt(sock, SOL_SOCKET, SO_RCVTIMEO, (void *)&timeout, + sizeof(timeout)); addrlen = sizeof(addr); do { ret = accept(sock, (struct sockaddr *)&addr, &addrlen); } while (ret == -1 && errno == EINTR); - g_assert_no_errno(ret); close(sock); return ret; @@ -115,7 +120,7 @@ QTestState *qtest_init(const char *extra_args) qemu_binary = getenv("QTEST_QEMU_BINARY"); g_assert(qemu_binary != NULL); - s = g_malloc(sizeof(*s)); + global_qtest = s = g_malloc(sizeof(*s)); socket_path = g_strdup_printf("/tmp/qtest-%d.sock", getpid()); qmp_socket_path = g_strdup_printf("/tmp/qtest-%d.qmp", getpid()); @@ -147,12 +152,16 @@ QTestState *qtest_init(const char *extra_args) } s->fd = socket_accept(sock); - s->qmp_fd = socket_accept(qmpsock); + if (s->fd >= 0) { + s->qmp_fd = socket_accept(qmpsock); + } unlink(socket_path); unlink(qmp_socket_path); g_free(socket_path); g_free(qmp_socket_path); + g_assert(s->fd >= 0 && s->qmp_fd >= 0); + s->rx = g_string_new(""); for (i = 0; i < MAX_IRQ; i++) { s->irq_level[i] = false; @@ -172,6 +181,7 @@ QTestState *qtest_init(const char *extra_args) void qtest_quit(QTestState *s) { sigaction(SIGABRT, &s->sigact_old, NULL); + global_qtest = NULL; kill_qemu(s); close(s->fd); @@ -581,3 +591,23 @@ void qtest_memwrite(QTestState *s, uint64_t addr, const void *data, size_t size) qtest_sendf(s, "\n"); qtest_rsp(s, 0); } + +QDict *qmp(const char *fmt, ...) +{ + va_list ap; + QDict *response; + + va_start(ap, fmt); + response = qtest_qmpv(global_qtest, fmt, ap); + va_end(ap); + return response; +} + +void qmp_discard_response(const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + qtest_qmpv_discard_response(global_qtest, fmt, ap); + va_end(ap); +} diff --git a/tests/libqtest.h b/tests/libqtest.h index 9deebdc..27a58fd 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -335,8 +335,7 @@ void qtest_add_func(const char *str, void (*fn)); */ static inline QTestState *qtest_start(const char *args) { - global_qtest = qtest_init(args); - return global_qtest; + return qtest_init(args); } /** @@ -347,7 +346,6 @@ static inline QTestState *qtest_start(const char *args) static inline void qtest_end(void) { qtest_quit(global_qtest); - global_qtest = NULL; } /** @@ -356,16 +354,7 @@ static inline void qtest_end(void) * * Sends a QMP message to QEMU and returns the response. */ -static inline QDict *qmp(const char *fmt, ...) -{ - va_list ap; - QDict *response; - - va_start(ap, fmt); - response = qtest_qmpv(global_qtest, fmt, ap); - va_end(ap); - return response; -} +QDict *qmp(const char *fmt, ...); /** * qmp_discard_response: @@ -373,14 +362,7 @@ static inline QDict *qmp(const char *fmt, ...) * * Sends a QMP message to QEMU and consumes the response. */ -static inline void qmp_discard_response(const char *fmt, ...) -{ - va_list ap; - - va_start(ap, fmt); - qtest_qmpv_discard_response(global_qtest, fmt, ap); - va_end(ap); -} +void qmp_discard_response(const char *fmt, ...); /** * get_irq: diff --git a/tests/qapi-schema/comments.out b/tests/qapi-schema/comments.out index e3bd904..4ce3dcf 100644 --- a/tests/qapi-schema/comments.out +++ b/tests/qapi-schema/comments.out @@ -1,3 +1,3 @@ [OrderedDict([('enum', 'Status'), ('data', ['good', 'bad', 'ugly'])])] -['Status'] +[{'enum_name': 'Status', 'enum_values': ['good', 'bad', 'ugly']}] [] diff --git a/tests/qapi-schema/duplicate-key.err b/tests/qapi-schema/duplicate-key.err new file mode 100644 index 0000000..0801c6a --- /dev/null +++ b/tests/qapi-schema/duplicate-key.err @@ -0,0 +1 @@ +<stdin>:2:10: Duplicate key "key" diff --git a/tests/qapi-schema/duplicate-key.exit b/tests/qapi-schema/duplicate-key.exit new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/qapi-schema/duplicate-key.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/duplicate-key.json b/tests/qapi-schema/duplicate-key.json new file mode 100644 index 0000000..1b55d88 --- /dev/null +++ b/tests/qapi-schema/duplicate-key.json @@ -0,0 +1,2 @@ +{ 'key': 'value', + 'key': 'value' } diff --git a/tests/qapi-schema/duplicate-key.out b/tests/qapi-schema/duplicate-key.out new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/qapi-schema/duplicate-key.out diff --git a/tests/qapi-schema/flat-union-invalid-branch-key.err b/tests/qapi-schema/flat-union-invalid-branch-key.err new file mode 100644 index 0000000..1125caf --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-branch-key.err @@ -0,0 +1 @@ +<stdin>:13: Discriminator value 'value_wrong' is not found in enum 'TestEnum' diff --git a/tests/qapi-schema/flat-union-invalid-branch-key.exit b/tests/qapi-schema/flat-union-invalid-branch-key.exit new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-branch-key.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/flat-union-invalid-branch-key.json b/tests/qapi-schema/flat-union-invalid-branch-key.json new file mode 100644 index 0000000..a624282 --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-branch-key.json @@ -0,0 +1,17 @@ +{ 'enum': 'TestEnum', + 'data': [ 'value1', 'value2' ] } + +{ 'type': 'TestBase', + 'data': { 'enum1': 'TestEnum' } } + +{ 'type': 'TestTypeA', + 'data': { 'string': 'str' } } + +{ 'type': 'TestTypeB', + 'data': { 'integer': 'int' } } + +{ 'union': 'TestUnion', + 'base': 'TestBase', + 'discriminator': 'enum1', + 'data': { 'value_wrong': 'TestTypeA', + 'value2': 'TestTypeB' } } diff --git a/tests/qapi-schema/flat-union-invalid-branch-key.out b/tests/qapi-schema/flat-union-invalid-branch-key.out new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-branch-key.out diff --git a/tests/qapi-schema/flat-union-invalid-discriminator.err b/tests/qapi-schema/flat-union-invalid-discriminator.err new file mode 100644 index 0000000..cad9dbf --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-discriminator.err @@ -0,0 +1 @@ +<stdin>:13: Discriminator 'enum_wrong' is not a member of base type 'TestBase' diff --git a/tests/qapi-schema/flat-union-invalid-discriminator.exit b/tests/qapi-schema/flat-union-invalid-discriminator.exit new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-discriminator.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/flat-union-invalid-discriminator.json b/tests/qapi-schema/flat-union-invalid-discriminator.json new file mode 100644 index 0000000..887157e --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-discriminator.json @@ -0,0 +1,17 @@ +{ 'enum': 'TestEnum', + 'data': [ 'value1', 'value2' ] } + +{ 'type': 'TestBase', + 'data': { 'enum1': 'TestEnum' } } + +{ 'type': 'TestTypeA', + 'data': { 'string': 'str' } } + +{ 'type': 'TestTypeB', + 'data': { 'integer': 'int' } } + +{ 'union': 'TestUnion', + 'base': 'TestBase', + 'discriminator': 'enum_wrong', + 'data': { 'value1': 'TestTypeA', + 'value2': 'TestTypeB' } } diff --git a/tests/qapi-schema/flat-union-invalid-discriminator.out b/tests/qapi-schema/flat-union-invalid-discriminator.out new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/qapi-schema/flat-union-invalid-discriminator.out diff --git a/tests/qapi-schema/flat-union-no-base.err b/tests/qapi-schema/flat-union-no-base.err new file mode 100644 index 0000000..e2d7443 --- /dev/null +++ b/tests/qapi-schema/flat-union-no-base.err @@ -0,0 +1 @@ +<stdin>:7: Flat union 'TestUnion' must have a base field diff --git a/tests/qapi-schema/flat-union-no-base.exit b/tests/qapi-schema/flat-union-no-base.exit new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/qapi-schema/flat-union-no-base.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/flat-union-no-base.json b/tests/qapi-schema/flat-union-no-base.json new file mode 100644 index 0000000..50f2673 --- /dev/null +++ b/tests/qapi-schema/flat-union-no-base.json @@ -0,0 +1,10 @@ +{ 'type': 'TestTypeA', + 'data': { 'string': 'str' } } + +{ 'type': 'TestTypeB', + 'data': { 'integer': 'int' } } + +{ 'union': 'TestUnion', + 'discriminator': 'enum1', + 'data': { 'value1': 'TestTypeA', + 'value2': 'TestTypeB' } } diff --git a/tests/qapi-schema/flat-union-no-base.out b/tests/qapi-schema/flat-union-no-base.out new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/qapi-schema/flat-union-no-base.out diff --git a/tests/qapi-schema/flat-union-reverse-define.err b/tests/qapi-schema/flat-union-reverse-define.err new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/qapi-schema/flat-union-reverse-define.err diff --git a/tests/qapi-schema/flat-union-reverse-define.exit b/tests/qapi-schema/flat-union-reverse-define.exit new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/qapi-schema/flat-union-reverse-define.exit @@ -0,0 +1 @@ +0 diff --git a/tests/qapi-schema/flat-union-reverse-define.json b/tests/qapi-schema/flat-union-reverse-define.json new file mode 100644 index 0000000..9ea7e72 --- /dev/null +++ b/tests/qapi-schema/flat-union-reverse-define.json @@ -0,0 +1,17 @@ +{ 'union': 'TestUnion', + 'base': 'TestBase', + 'discriminator': 'enum1', + 'data': { 'value1': 'TestTypeA', + 'value2': 'TestTypeB' } } + +{ 'type': 'TestBase', + 'data': { 'enum1': 'TestEnum' } } + +{ 'enum': 'TestEnum', + 'data': [ 'value1', 'value2' ] } + +{ 'type': 'TestTypeA', + 'data': { 'string': 'str' } } + +{ 'type': 'TestTypeB', + 'data': { 'integer': 'int' } } diff --git a/tests/qapi-schema/flat-union-reverse-define.out b/tests/qapi-schema/flat-union-reverse-define.out new file mode 100644 index 0000000..03c952e --- /dev/null +++ b/tests/qapi-schema/flat-union-reverse-define.out @@ -0,0 +1,9 @@ +[OrderedDict([('union', 'TestUnion'), ('base', 'TestBase'), ('discriminator', 'enum1'), ('data', OrderedDict([('value1', 'TestTypeA'), ('value2', 'TestTypeB')]))]), + OrderedDict([('type', 'TestBase'), ('data', OrderedDict([('enum1', 'TestEnum')]))]), + OrderedDict([('enum', 'TestEnum'), ('data', ['value1', 'value2'])]), + OrderedDict([('type', 'TestTypeA'), ('data', OrderedDict([('string', 'str')]))]), + OrderedDict([('type', 'TestTypeB'), ('data', OrderedDict([('integer', 'int')]))])] +[{'enum_name': 'TestEnum', 'enum_values': ['value1', 'value2']}] +[OrderedDict([('type', 'TestBase'), ('data', OrderedDict([('enum1', 'TestEnum')]))]), + OrderedDict([('type', 'TestTypeA'), ('data', OrderedDict([('string', 'str')]))]), + OrderedDict([('type', 'TestTypeB'), ('data', OrderedDict([('integer', 'int')]))])] diff --git a/tests/qapi-schema/flat-union-string-discriminator.err b/tests/qapi-schema/flat-union-string-discriminator.err new file mode 100644 index 0000000..8748270 --- /dev/null +++ b/tests/qapi-schema/flat-union-string-discriminator.err @@ -0,0 +1 @@ +<stdin>:13: Discriminator 'kind' must be of enumeration type diff --git a/tests/qapi-schema/flat-union-string-discriminator.exit b/tests/qapi-schema/flat-union-string-discriminator.exit new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/qapi-schema/flat-union-string-discriminator.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/flat-union-string-discriminator.json b/tests/qapi-schema/flat-union-string-discriminator.json new file mode 100644 index 0000000..e966aeb --- /dev/null +++ b/tests/qapi-schema/flat-union-string-discriminator.json @@ -0,0 +1,17 @@ +{ 'enum': 'TestEnum', + 'data': [ 'value1', 'value2' ] } + +{ 'type': 'TestBase', + 'data': { 'enum1': 'TestEnum', 'kind': 'str' } } + +{ 'type': 'TestTypeA', + 'data': { 'string': 'str' } } + +{ 'type': 'TestTypeB', + 'data': { 'integer': 'int' } } + +{ 'union': 'TestUnion', + 'base': 'TestBase', + 'discriminator': 'kind', + 'data': { 'kind1': 'TestTypeA', + 'kind2': 'TestTypeB' } } diff --git a/tests/qapi-schema/flat-union-string-discriminator.out b/tests/qapi-schema/flat-union-string-discriminator.out new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/qapi-schema/flat-union-string-discriminator.out diff --git a/tests/qapi-schema/qapi-schema-test.json b/tests/qapi-schema/qapi-schema-test.json index 471ba47..818c06d 100644 --- a/tests/qapi-schema/qapi-schema-test.json +++ b/tests/qapi-schema/qapi-schema-test.json @@ -37,10 +37,13 @@ 'base': 'UserDefZero', 'data': { 'a' : 'UserDefA', 'b' : 'UserDefB' } } +{ 'type': 'UserDefUnionBase', + 'data': { 'string': 'str', 'enum1': 'EnumOne' } } + { 'union': 'UserDefFlatUnion', - 'base': 'UserDefOne', - 'discriminator': 'string', - 'data': { 'a' : 'UserDefA', 'b' : 'UserDefB' } } + 'base': 'UserDefUnionBase', + 'discriminator': 'enum1', + 'data': { 'value1' : 'UserDefA', 'value2' : 'UserDefB', 'value3' : 'UserDefB' } } # FIXME generated struct UserDefFlatUnion has members for direct base # UserDefOne, but lacks members for indirect base UserDefZero diff --git a/tests/qapi-schema/qapi-schema-test.out b/tests/qapi-schema/qapi-schema-test.out index 89b53d4..6cd03f3 100644 --- a/tests/qapi-schema/qapi-schema-test.out +++ b/tests/qapi-schema/qapi-schema-test.out @@ -7,7 +7,8 @@ OrderedDict([('type', 'UserDefA'), ('data', OrderedDict([('boolean', 'bool')]))]), OrderedDict([('type', 'UserDefB'), ('data', OrderedDict([('integer', 'int')]))]), OrderedDict([('union', 'UserDefUnion'), ('base', 'UserDefZero'), ('data', OrderedDict([('a', 'UserDefA'), ('b', 'UserDefB')]))]), - OrderedDict([('union', 'UserDefFlatUnion'), ('base', 'UserDefOne'), ('discriminator', 'string'), ('data', OrderedDict([('a', 'UserDefA'), ('b', 'UserDefB')]))]), + OrderedDict([('type', 'UserDefUnionBase'), ('data', OrderedDict([('string', 'str'), ('enum1', 'EnumOne')]))]), + OrderedDict([('union', 'UserDefFlatUnion'), ('base', 'UserDefUnionBase'), ('discriminator', 'enum1'), ('data', OrderedDict([('value1', 'UserDefA'), ('value2', 'UserDefB'), ('value3', 'UserDefB')]))]), OrderedDict([('union', 'UserDefAnonUnion'), ('discriminator', OrderedDict()), ('data', OrderedDict([('uda', 'UserDefA'), ('s', 'str'), ('i', 'int')]))]), OrderedDict([('union', 'UserDefNativeListUnion'), ('data', OrderedDict([('integer', ['int']), ('s8', ['int8']), ('s16', ['int16']), ('s32', ['int32']), ('s64', ['int64']), ('u8', ['uint8']), ('u16', ['uint16']), ('u32', ['uint32']), ('u64', ['uint64']), ('number', ['number']), ('boolean', ['bool']), ('string', ['str'])]))]), OrderedDict([('command', 'user_def_cmd'), ('data', OrderedDict())]), @@ -15,11 +16,10 @@ OrderedDict([('command', 'user_def_cmd2'), ('data', OrderedDict([('ud1a', 'UserDefOne'), ('*ud1b', 'UserDefOne')])), ('returns', 'UserDefTwo')]), OrderedDict([('command', 'user_def_cmd3'), ('data', OrderedDict([('a', 'int'), ('*b', 'int')])), ('returns', 'int')]), OrderedDict([('type', 'UserDefOptions'), ('data', OrderedDict([('*i64', ['int']), ('*u64', ['uint64']), ('*u16', ['uint16']), ('*i64x', 'int'), ('*u64x', 'uint64')]))])] -['EnumOne', - 'UserDefUnionKind', - 'UserDefFlatUnionKind', - 'UserDefAnonUnionKind', - 'UserDefNativeListUnionKind'] +[{'enum_name': 'EnumOne', 'enum_values': ['value1', 'value2', 'value3']}, + {'enum_name': 'UserDefUnionKind', 'enum_values': None}, + {'enum_name': 'UserDefAnonUnionKind', 'enum_values': None}, + {'enum_name': 'UserDefNativeListUnionKind', 'enum_values': None}] [OrderedDict([('type', 'NestedEnumsOne'), ('data', OrderedDict([('enum1', 'EnumOne'), ('*enum2', 'EnumOne'), ('enum3', 'EnumOne'), ('*enum4', 'EnumOne')]))]), OrderedDict([('type', 'UserDefZero'), ('data', OrderedDict([('integer', 'int')]))]), OrderedDict([('type', 'UserDefOne'), ('base', 'UserDefZero'), ('data', OrderedDict([('string', 'str'), ('*enum1', 'EnumOne')]))]), @@ -27,4 +27,5 @@ OrderedDict([('type', 'UserDefNested'), ('data', OrderedDict([('string0', 'str'), ('dict1', OrderedDict([('string1', 'str'), ('dict2', OrderedDict([('userdef1', 'UserDefOne'), ('string2', 'str')])), ('*dict3', OrderedDict([('userdef2', 'UserDefOne'), ('string3', 'str')]))]))]))]), OrderedDict([('type', 'UserDefA'), ('data', OrderedDict([('boolean', 'bool')]))]), OrderedDict([('type', 'UserDefB'), ('data', OrderedDict([('integer', 'int')]))]), + OrderedDict([('type', 'UserDefUnionBase'), ('data', OrderedDict([('string', 'str'), ('enum1', 'EnumOne')]))]), OrderedDict([('type', 'UserDefOptions'), ('data', OrderedDict([('*i64', ['int']), ('*u64', ['uint64']), ('*u16', ['uint16']), ('*i64x', 'int'), ('*u64x', 'uint64')]))])] diff --git a/tests/qapi-schema/union-invalid-base.err b/tests/qapi-schema/union-invalid-base.err new file mode 100644 index 0000000..dd8e3d1 --- /dev/null +++ b/tests/qapi-schema/union-invalid-base.err @@ -0,0 +1 @@ +<stdin>:7: Base 'TestBaseWrong' is not a valid type diff --git a/tests/qapi-schema/union-invalid-base.exit b/tests/qapi-schema/union-invalid-base.exit new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/qapi-schema/union-invalid-base.exit @@ -0,0 +1 @@ +1 diff --git a/tests/qapi-schema/union-invalid-base.json b/tests/qapi-schema/union-invalid-base.json new file mode 100644 index 0000000..1fa4930 --- /dev/null +++ b/tests/qapi-schema/union-invalid-base.json @@ -0,0 +1,10 @@ +{ 'type': 'TestTypeA', + 'data': { 'string': 'str' } } + +{ 'type': 'TestTypeB', + 'data': { 'integer': 'int' } } + +{ 'union': 'TestUnion', + 'base': 'TestBaseWrong', + 'data': { 'value1': 'TestTypeA', + 'value2': 'TestTypeB' } } diff --git a/tests/qapi-schema/union-invalid-base.out b/tests/qapi-schema/union-invalid-base.out new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/qapi-schema/union-invalid-base.out diff --git a/tests/qdev-monitor-test.c b/tests/qdev-monitor-test.c index ba7f9cc..e20ffd6 100644 --- a/tests/qdev-monitor-test.c +++ b/tests/qdev-monitor-test.c @@ -32,8 +32,7 @@ static void test_device_add(void) "}}"); g_assert(response); error = qdict_get_qdict(response, "error"); - g_assert(!strcmp(qdict_get_try_str(error, "desc") ?: "", - "Device needs media, but drive is empty")); + g_assert_cmpstr(qdict_get_try_str(error, "class"), ==, "GenericError"); QDECREF(response); /* Delete the drive */ @@ -42,7 +41,7 @@ static void test_device_add(void) " \"command-line\": \"drive_del drive0\"" "}}"); g_assert(response); - g_assert(!strcmp(qdict_get_try_str(response, "return") ?: "(null)", "")); + g_assert_cmpstr(qdict_get_try_str(response, "return"), ==, ""); QDECREF(response); /* Try to re-add the drive. This fails with duplicate IDs if a leaked @@ -53,8 +52,7 @@ static void test_device_add(void) " \"command-line\": \"drive_add pci-addr=auto if=none,id=drive0\"" "}}"); g_assert(response); - g_assert(!strcmp(qdict_get_try_str(response, "return") ?: "", - "OK\r\n")); + g_assert_cmpstr(qdict_get_try_str(response, "return"), ==, "OK\r\n"); QDECREF(response); qtest_end(); diff --git a/tests/qemu-iotests/060 b/tests/qemu-iotests/060 index af8ed9f..f0116aa 100755 --- a/tests/qemu-iotests/060 +++ b/tests/qemu-iotests/060 @@ -138,6 +138,32 @@ $QEMU_IMG snapshot -a foo "$TEST_IMG" _check_test_img $QEMU_IO -c "$OPEN_RO" -c "read -P 1 0 512" | _filter_qemu_io +echo +echo "=== Testing overlap while COW is in flight ===" +echo +# compat=0.10 is required in order to make the following discard actually +# unallocate the sector rather than make it a zero sector - we want COW, after +# all. +IMGOPTS='compat=0.10' _make_test_img 1G +# Write two clusters, the second one enforces creation of an L2 table after +# the first data cluster. +$QEMU_IO -c 'write 0k 64k' -c 'write 512M 64k' "$TEST_IMG" | _filter_qemu_io +# Discard the first cluster. This cluster will soon enough be reallocated and +# used for COW. +$QEMU_IO -c 'discard 0k 64k' "$TEST_IMG" | _filter_qemu_io +# Now, corrupt the image by marking the second L2 table cluster as free. +poke_file "$TEST_IMG" '131084' "\x00\x00" # 0x2000c +# Start a write operation requiring COW on the image stopping it right before +# doing the read; then, trigger the corruption prevention by writing anything to +# any unallocated cluster, leading to an attempt to overwrite the second L2 +# table. Finally, resume the COW write and see it fail (but not crash). +echo "open -o file.driver=blkdebug $TEST_IMG +break cow_read 0 +aio_write 0k 1k +wait_break 0 +write 64k 64k +resume 0" | $QEMU_IO | _filter_qemu_io + # success, all done echo "*** done" rm -f $seq.full diff --git a/tests/qemu-iotests/060.out b/tests/qemu-iotests/060.out index 6c7bdbb..a517948 100644 --- a/tests/qemu-iotests/060.out +++ b/tests/qemu-iotests/060.out @@ -78,4 +78,19 @@ read 512/512 bytes at offset 0 No errors were found on the image. read 512/512 bytes at offset 0 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) + +=== Testing overlap while COW is in flight === + +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 +wrote 65536/65536 bytes at offset 0 +64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +wrote 65536/65536 bytes at offset 536870912 +64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +discard 65536/65536 bytes at offset 0 +64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +qcow2: Preventing invalid write on metadata (overlaps with active L2 table); image marked as corrupt. +blkdebug: Suspended request '0' +write failed: Input/output error +blkdebug: Resuming request '0' +aio_write failed: No medium found *** done diff --git a/tests/qemu-iotests/083 b/tests/qemu-iotests/083 new file mode 100755 index 0000000..f764534 --- /dev/null +++ b/tests/qemu-iotests/083 @@ -0,0 +1,129 @@ +#!/bin/bash +# +# Test NBD client unexpected disconnect +# +# Copyright Red Hat, Inc. 2014 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +# creator +owner=stefanha@redhat.com + +seq=`basename $0` +echo "QA output created by $seq" + +here=`pwd` +tmp=/tmp/$$ +status=1 # failure is the default! + +# get standard environment, filters and checks +. ./common.rc +. ./common.filter + +_supported_fmt generic +_supported_proto nbd +_supported_os Linux + +# Pick a TCP port based on our pid. This way multiple instances of this test +# can run in parallel without conflicting. +choose_tcp_port() { + echo $((($$ % 31744) + 1024)) # 1024 <= port < 32768 +} + +wait_for_tcp_port() { + while ! (netstat --tcp --listening --numeric | \ + grep "$1.*0.0.0.0:\*.*LISTEN") 2>&1 >/dev/null; do + sleep 0.1 + done +} + +filter_nbd() { + # nbd.c error messages contain function names and line numbers that are prone + # to change. Message ordering depends on timing between send and receive + # callbacks sometimes, making them unreliable. + # + # Filter out the TCP port number since this changes between runs. + sed -e 's#^nbd.c:.*##g' \ + -e 's#nbd:127.0.0.1:[^:]*:#nbd:127.0.0.1:PORT:#g' +} + +check_disconnect() { + event=$1 + when=$2 + negotiation=$3 + echo "=== Check disconnect $when $event ===" + echo + + port=$(choose_tcp_port) + + cat > "$TEST_DIR/nbd-fault-injector.conf" <<EOF +[inject-error] +event=$event +when=$when +EOF + + if [ "$negotiation" = "--classic-negotiation" ]; then + extra_args=--classic-negotiation + nbd_url="nbd:127.0.0.1:$port" + else + nbd_url="nbd:127.0.0.1:$port:exportname=foo" + fi + + ./nbd-fault-injector.py $extra_args "127.0.0.1:$port" "$TEST_DIR/nbd-fault-injector.conf" 2>&1 >/dev/null & + wait_for_tcp_port "127.0.0.1:$port" + $QEMU_IO -c "read 0 512" "$nbd_url" 2>&1 | _filter_qemu_io | filter_nbd + + echo +} + +for event in neg1 "export" neg2 request reply data; do + for when in before after; do + check_disconnect "$event" "$when" + done + + # Also inject short replies from the NBD server + case "$event" in + neg1) + for when in 8 16; do + check_disconnect "$event" "$when" + done + ;; + "export") + for when in 4 12 16; do + check_disconnect "$event" "$when" + done + ;; + neg2) + for when in 8 10; do + check_disconnect "$event" "$when" + done + ;; + reply) + for when in 4 8; do + check_disconnect "$event" "$when" + done + ;; + esac +done + +# Also check classic negotiation without export information +for when in before 8 16 24 28 after; do + check_disconnect "neg-classic" "$when" --classic-negotiation +done + +# success, all done +echo "*** done" +rm -f $seq.full +status=0 diff --git a/tests/qemu-iotests/083.out b/tests/qemu-iotests/083.out new file mode 100644 index 0000000..85ee8d6 --- /dev/null +++ b/tests/qemu-iotests/083.out @@ -0,0 +1,163 @@ +QA output created by 083 +=== Check disconnect before neg1 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect after neg1 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 8 neg1 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 16 neg1 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect before export === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect after export === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 4 export === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 12 export === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 16 export === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect before neg2 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect after neg2 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect 8 neg2 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 10 neg2 === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect before request === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect after request === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect before reply === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect after reply === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect 4 reply === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect 8 reply === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect before data === + + +qemu-io: can't open device nbd:127.0.0.1:PORT:exportname=foo: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +=== Check disconnect after data === + + +read failed: Input/output error + +=== Check disconnect before neg-classic === + + +qemu-io: can't open device nbd:127.0.0.1:PORT: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 8 neg-classic === + + +qemu-io: can't open device nbd:127.0.0.1:PORT: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 16 neg-classic === + + +qemu-io: can't open device nbd:127.0.0.1:PORT: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 24 neg-classic === + + +qemu-io: can't open device nbd:127.0.0.1:PORT: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect 28 neg-classic === + + +qemu-io: can't open device nbd:127.0.0.1:PORT: Could not open image: Invalid argument +no file open, try 'help open' + +=== Check disconnect after neg-classic === + + +qemu-io: can't open device nbd:127.0.0.1:PORT: Could not read image for determining its format: Input/output error +no file open, try 'help open' + +*** done diff --git a/tests/qemu-iotests/087 b/tests/qemu-iotests/087 index 53b6c43..a38bb70 100755 --- a/tests/qemu-iotests/087 +++ b/tests/qemu-iotests/087 @@ -99,6 +99,23 @@ echo === Encrypted image === echo _make_test_img -o encryption=on $size +run_qemu -S <<EOF +{ "execute": "qmp_capabilities" } +{ "execute": "blockdev-add", + "arguments": { + "options": { + "driver": "$IMGFMT", + "id": "disk", + "file": { + "driver": "file", + "filename": "$TEST_IMG" + } + } + } + } +{ "execute": "quit" } +EOF + run_qemu <<EOF { "execute": "qmp_capabilities" } { "execute": "blockdev-add", diff --git a/tests/qemu-iotests/087.out b/tests/qemu-iotests/087.out index b871032..e65dcdf 100644 --- a/tests/qemu-iotests/087.out +++ b/tests/qemu-iotests/087.out @@ -28,7 +28,7 @@ QMP_VERSION === Encrypted image === Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 encryption=on -Testing: +Testing: -S QMP_VERSION {"return": {}} {"error": {"class": "GenericError", "desc": "blockdev-add doesn't support encrypted devices"}} @@ -37,4 +37,13 @@ QMP_VERSION {"timestamp": {"seconds": TIMESTAMP, "microseconds": TIMESTAMP}, "event": "DEVICE_TRAY_MOVED", "data": {"device": "ide1-cd0", "tray-open": true}} {"timestamp": {"seconds": TIMESTAMP, "microseconds": TIMESTAMP}, "event": "DEVICE_TRAY_MOVED", "data": {"device": "floppy0", "tray-open": true}} +Testing: +QMP_VERSION +{"return": {}} +{"error": {"class": "GenericError", "desc": "could not open disk image disk: Guest must be stopped for opening of encrypted image"}} +{"return": {}} +{"timestamp": {"seconds": TIMESTAMP, "microseconds": TIMESTAMP}, "event": "SHUTDOWN"} +{"timestamp": {"seconds": TIMESTAMP, "microseconds": TIMESTAMP}, "event": "DEVICE_TRAY_MOVED", "data": {"device": "ide1-cd0", "tray-open": true}} +{"timestamp": {"seconds": TIMESTAMP, "microseconds": TIMESTAMP}, "event": "DEVICE_TRAY_MOVED", "data": {"device": "floppy0", "tray-open": true}} + *** done diff --git a/tests/qemu-iotests/group b/tests/qemu-iotests/group index e96eafd..ee09ebc 100644 --- a/tests/qemu-iotests/group +++ b/tests/qemu-iotests/group @@ -85,6 +85,7 @@ 079 rw auto 081 rw auto 082 rw auto quick -085 rw auto quick +083 rw auto +085 rw auto 086 rw auto quick -087 rw auto quick +087 rw auto diff --git a/tests/qemu-iotests/nbd-fault-injector.py b/tests/qemu-iotests/nbd-fault-injector.py new file mode 100755 index 0000000..6c07191 --- /dev/null +++ b/tests/qemu-iotests/nbd-fault-injector.py @@ -0,0 +1,264 @@ +#!/usr/bin/env python +# NBD server - fault injection utility +# +# Configuration file syntax: +# [inject-error "disconnect-neg1"] +# event=neg1 +# io=readwrite +# when=before +# +# Note that Python's ConfigParser squashes together all sections with the same +# name, so give each [inject-error] a unique name. +# +# inject-error options: +# event - name of the trigger event +# "neg1" - first part of negotiation struct +# "export" - export struct +# "neg2" - second part of negotiation struct +# "request" - NBD request struct +# "reply" - NBD reply struct +# "data" - request/reply data +# io - I/O direction that triggers this rule: +# "read", "write", or "readwrite" +# default: readwrite +# when - after how many bytes to inject the fault +# -1 - inject error after I/O +# 0 - inject error before I/O +# integer - inject error after integer bytes +# "before" - alias for 0 +# "after" - alias for -1 +# default: before +# +# Currently the only error injection action is to terminate the server process. +# This resets the TCP connection and thus forces the client to handle +# unexpected connection termination. +# +# Other error injection actions could be added in the future. +# +# Copyright Red Hat, Inc. 2014 +# +# Authors: +# Stefan Hajnoczi <stefanha@redhat.com> +# +# This work is licensed under the terms of the GNU GPL, version 2 or later. +# See the COPYING file in the top-level directory. + +import sys +import socket +import struct +import collections +import ConfigParser + +FAKE_DISK_SIZE = 8 * 1024 * 1024 * 1024 # 8 GB + +# Protocol constants +NBD_CMD_READ = 0 +NBD_CMD_WRITE = 1 +NBD_CMD_DISC = 2 +NBD_REQUEST_MAGIC = 0x25609513 +NBD_REPLY_MAGIC = 0x67446698 +NBD_PASSWD = 0x4e42444d41474943 +NBD_OPTS_MAGIC = 0x49484156454F5054 +NBD_CLIENT_MAGIC = 0x0000420281861253 +NBD_OPT_EXPORT_NAME = 1 << 0 + +# Protocol structs +neg_classic_struct = struct.Struct('>QQQI124x') +neg1_struct = struct.Struct('>QQH') +export_tuple = collections.namedtuple('Export', 'reserved magic opt len') +export_struct = struct.Struct('>IQII') +neg2_struct = struct.Struct('>QH124x') +request_tuple = collections.namedtuple('Request', 'magic type handle from_ len') +request_struct = struct.Struct('>IIQQI') +reply_struct = struct.Struct('>IIQ') + +def err(msg): + sys.stderr.write(msg + '\n') + sys.exit(1) + +def recvall(sock, bufsize): + received = 0 + chunks = [] + while received < bufsize: + chunk = sock.recv(bufsize - received) + if len(chunk) == 0: + raise Exception('unexpected disconnect') + chunks.append(chunk) + received += len(chunk) + return ''.join(chunks) + +class Rule(object): + def __init__(self, name, event, io, when): + self.name = name + self.event = event + self.io = io + self.when = when + + def match(self, event, io): + if event != self.event: + return False + if io != self.io and self.io != 'readwrite': + return False + return True + +class FaultInjectionSocket(object): + def __init__(self, sock, rules): + self.sock = sock + self.rules = rules + + def check(self, event, io, bufsize=None): + for rule in self.rules: + if rule.match(event, io): + if rule.when == 0 or bufsize is None: + print 'Closing connection on rule match %s' % rule.name + sys.exit(0) + if rule.when != -1: + return rule.when + return bufsize + + def send(self, buf, event): + bufsize = self.check(event, 'write', bufsize=len(buf)) + self.sock.sendall(buf[:bufsize]) + self.check(event, 'write') + + def recv(self, bufsize, event): + bufsize = self.check(event, 'read', bufsize=bufsize) + data = recvall(self.sock, bufsize) + self.check(event, 'read') + return data + + def close(self): + self.sock.close() + +def negotiate_classic(conn): + buf = neg_classic_struct.pack(NBD_PASSWD, NBD_CLIENT_MAGIC, + FAKE_DISK_SIZE, 0) + conn.send(buf, event='neg-classic') + +def negotiate_export(conn): + # Send negotiation part 1 + buf = neg1_struct.pack(NBD_PASSWD, NBD_OPTS_MAGIC, 0) + conn.send(buf, event='neg1') + + # Receive export option + buf = conn.recv(export_struct.size, event='export') + export = export_tuple._make(export_struct.unpack(buf)) + assert export.magic == NBD_OPTS_MAGIC + assert export.opt == NBD_OPT_EXPORT_NAME + name = conn.recv(export.len, event='export-name') + + # Send negotiation part 2 + buf = neg2_struct.pack(FAKE_DISK_SIZE, 0) + conn.send(buf, event='neg2') + +def negotiate(conn, use_export): + '''Negotiate export with client''' + if use_export: + negotiate_export(conn) + else: + negotiate_classic(conn) + +def read_request(conn): + '''Parse NBD request from client''' + buf = conn.recv(request_struct.size, event='request') + req = request_tuple._make(request_struct.unpack(buf)) + assert req.magic == NBD_REQUEST_MAGIC + return req + +def write_reply(conn, error, handle): + buf = reply_struct.pack(NBD_REPLY_MAGIC, error, handle) + conn.send(buf, event='reply') + +def handle_connection(conn, use_export): + negotiate(conn, use_export) + while True: + req = read_request(conn) + if req.type == NBD_CMD_READ: + write_reply(conn, 0, req.handle) + conn.send('\0' * req.len, event='data') + elif req.type == NBD_CMD_WRITE: + _ = conn.recv(req.len, event='data') + write_reply(conn, 0, req.handle) + elif req.type == NBD_CMD_DISC: + break + else: + print 'unrecognized command type %#02x' % req.type + break + conn.close() + +def run_server(sock, rules, use_export): + while True: + conn, _ = sock.accept() + handle_connection(FaultInjectionSocket(conn, rules), use_export) + +def parse_inject_error(name, options): + if 'event' not in options: + err('missing \"event\" option in %s' % name) + event = options['event'] + if event not in ('neg-classic', 'neg1', 'export', 'neg2', 'request', 'reply', 'data'): + err('invalid \"event\" option value \"%s\" in %s' % (event, name)) + io = options.get('io', 'readwrite') + if io not in ('read', 'write', 'readwrite'): + err('invalid \"io\" option value \"%s\" in %s' % (io, name)) + when = options.get('when', 'before') + try: + when = int(when) + except ValueError: + if when == 'before': + when = 0 + elif when == 'after': + when = -1 + else: + err('invalid \"when\" option value \"%s\" in %s' % (when, name)) + return Rule(name, event, io, when) + +def parse_config(config): + rules = [] + for name in config.sections(): + if name.startswith('inject-error'): + options = dict(config.items(name)) + rules.append(parse_inject_error(name, options)) + else: + err('invalid config section name: %s' % name) + return rules + +def load_rules(filename): + config = ConfigParser.RawConfigParser() + with open(filename, 'rt') as f: + config.readfp(f, filename) + return parse_config(config) + +def open_socket(path): + '''Open a TCP or UNIX domain listen socket''' + if ':' in path: + host, port = path.split(':', 1) + sock = socket.socket() + sock.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1) + sock.bind((host, int(port))) + else: + sock = socket.socket(socket.AF_UNIX) + sock.bind(path) + sock.listen(0) + print 'Listening on %s' % path + return sock + +def usage(args): + sys.stderr.write('usage: %s [--classic-negotiation] <tcp-port>|<unix-path> <config-file>\n' % args[0]) + sys.stderr.write('Run an fault injector NBD server with rules defined in a config file.\n') + sys.exit(1) + +def main(args): + if len(args) != 3 and len(args) != 4: + usage(args) + use_export = True + if args[1] == '--classic-negotiation': + use_export = False + elif len(args) == 4: + usage(args) + sock = open_socket(args[1 if use_export else 2]) + rules = load_rules(args[2 if use_export else 3]) + run_server(sock, rules, use_export) + return 0 + +if __name__ == '__main__': + sys.exit(main(sys.argv)) diff --git a/tests/qom-test.c b/tests/qom-test.c index b6671fb..6d9a00b 100644 --- a/tests/qom-test.c +++ b/tests/qom-test.c @@ -10,6 +10,7 @@ #include <glib.h> #include <string.h> +#include "qemu-common.h" #include "libqtest.h" #include "qemu/osdep.h" #include "qapi/qmp/types.h" @@ -43,6 +44,40 @@ static bool is_blacklisted(const char *arch, const char *mach) return false; } +static void test_properties(const char *path) +{ + char *child_path; + QDict *response, *tuple; + QList *list; + QListEntry *entry; + + g_test_message("Obtaining properties of %s", path); + response = qmp("{ 'execute': 'qom-list'," + " 'arguments': { 'path': '%s' } }", path); + g_assert(response); + + g_assert(qdict_haskey(response, "return")); + list = qobject_to_qlist(qdict_get(response, "return")); + QLIST_FOREACH_ENTRY(list, entry) { + tuple = qobject_to_qdict(qlist_entry_obj(entry)); + if (strstart(qdict_get_str(tuple, "type"), "child<", NULL)) { + child_path = g_strdup_printf("%s/%s", + path, qdict_get_str(tuple, "name")); + test_properties(child_path); + g_free(child_path); + } else { + const char *prop = qdict_get_str(tuple, "name"); + g_test_message("Testing property %s.%s", path, prop); + response = qmp("{ 'execute': 'qom-get'," + " 'arguments': { 'path': '%s'," + " 'property': '%s' } }", + path, prop); + /* qom-get may fail but should not, e.g., segfault. */ + g_assert(response); + } + } +} + static void test_machine(gconstpointer data) { const char *machine = data; @@ -51,8 +86,12 @@ static void test_machine(gconstpointer data) args = g_strdup_printf("-machine %s", machine); qtest_start(args); + + test_properties("/machine"); + response = qmp("{ 'execute': 'quit' }"); g_assert(qdict_haskey(response, "return")); + qtest_end(); g_free(args); } diff --git a/tests/spapr-phb-test.c b/tests/spapr-phb-test.c new file mode 100644 index 0000000..b629de4 --- /dev/null +++ b/tests/spapr-phb-test.c @@ -0,0 +1,35 @@ +/* + * QTest testcase for SPAPR PHB + * + * Authors: + * Alexey Kardashevskiy <aik@ozlabs.ru> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#include <glib.h> + +#include "libqtest.h" + +#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" + +/* Tests only initialization so far. TODO: Replace with functional tests */ +static void test_phb_device(void) +{ +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/spapr-phb/device", test_phb_device); + + qtest_start("-device " TYPE_SPAPR_PCI_HOST_BRIDGE ",index=100"); + + ret = g_test_run(); + + qtest_end(); + + return ret; +} diff --git a/tests/tcg/test_path.c b/tests/tcg/test_path.c index a064eea..f8dd36a 100644 --- a/tests/tcg/test_path.c +++ b/tests/tcg/test_path.c @@ -1,12 +1,15 @@ /* Test path override code */ #define _GNU_SOURCE #include "config-host.h" -#include "iov.c" -#include "cutils.c" -#include "path.c" -#include "trace.c" +#include "util/cutils.c" +#include "util/hexdump.c" +#include "util/iov.c" +#include "util/path.c" +#include "util/qemu-timer-common.c" +#include "trace/control.c" +#include "../trace/generated-events.c" #ifdef CONFIG_TRACE_SIMPLE -#include "../trace/simple.c" +#include "trace/simple.c" #endif #include <stdarg.h> diff --git a/tests/test-aio.c b/tests/test-aio.c index 592721e..56f4288 100644 --- a/tests/test-aio.c +++ b/tests/test-aio.c @@ -112,6 +112,64 @@ static void test_notify(void) g_assert(!aio_poll(ctx, false)); } +typedef struct { + QemuMutex start_lock; + bool thread_acquired; +} AcquireTestData; + +static void *test_acquire_thread(void *opaque) +{ + AcquireTestData *data = opaque; + + /* Wait for other thread to let us start */ + qemu_mutex_lock(&data->start_lock); + qemu_mutex_unlock(&data->start_lock); + + aio_context_acquire(ctx); + aio_context_release(ctx); + + data->thread_acquired = true; /* success, we got here */ + + return NULL; +} + +static void dummy_notifier_read(EventNotifier *unused) +{ + g_assert(false); /* should never be invoked */ +} + +static void test_acquire(void) +{ + QemuThread thread; + EventNotifier notifier; + AcquireTestData data; + + /* Dummy event notifier ensures aio_poll() will block */ + event_notifier_init(¬ifier, false); + aio_set_event_notifier(ctx, ¬ifier, dummy_notifier_read); + g_assert(!aio_poll(ctx, false)); /* consume aio_notify() */ + + qemu_mutex_init(&data.start_lock); + qemu_mutex_lock(&data.start_lock); + data.thread_acquired = false; + + qemu_thread_create(&thread, "test_acquire_thread", + test_acquire_thread, + &data, QEMU_THREAD_JOINABLE); + + /* Block in aio_poll(), let other thread kick us and acquire context */ + aio_context_acquire(ctx); + qemu_mutex_unlock(&data.start_lock); /* let the thread run */ + g_assert(!aio_poll(ctx, true)); + aio_context_release(ctx); + + qemu_thread_join(&thread); + aio_set_event_notifier(ctx, ¬ifier, NULL); + event_notifier_cleanup(¬ifier); + + g_assert(data.thread_acquired); +} + static void test_bh_schedule(void) { BHTestData data = { .n = 0 }; @@ -775,6 +833,7 @@ int main(int argc, char **argv) g_test_init(&argc, &argv, NULL); g_test_add_func("/aio/notify", test_notify); + g_test_add_func("/aio/acquire", test_acquire); g_test_add_func("/aio/bh/schedule", test_bh_schedule); g_test_add_func("/aio/bh/schedule10", test_bh_schedule10); g_test_add_func("/aio/bh/cancel", test_bh_cancel); diff --git a/tests/test-qmp-commands.c b/tests/test-qmp-commands.c index 8e62c2d..554e222 100644 --- a/tests/test-qmp-commands.c +++ b/tests/test-qmp-commands.c @@ -141,7 +141,7 @@ static void test_dispatch_cmd_io(void) ret3 = qobject_to_qint(test_qmp_dispatch(req)); assert(qint_get_int(ret3) == 66); - QDECREF(ret); + QDECREF(ret3); QDECREF(req); } diff --git a/tests/test-qmp-input-strict.c b/tests/test-qmp-input-strict.c index 64d72f6..38b5e95 100644 --- a/tests/test-qmp-input-strict.c +++ b/tests/test-qmp-input-strict.c @@ -146,7 +146,10 @@ static void test_validate_union_flat(TestInputVisitorData *data, Visitor *v; Error *errp = NULL; - v = validate_test_init(data, "{ 'string': 'a', 'boolean': true }"); + v = validate_test_init(data, + "{ 'enum1': 'value1', " + "'string': 'str', " + "'boolean': true }"); /* TODO when generator bug is fixed, add 'integer': 41 */ visit_type_UserDefFlatUnion(v, &tmp, NULL, &errp); diff --git a/tests/test-qmp-input-visitor.c b/tests/test-qmp-input-visitor.c index 2dffafc..1729667 100644 --- a/tests/test-qmp-input-visitor.c +++ b/tests/test-qmp-input-visitor.c @@ -310,14 +310,18 @@ static void test_visitor_in_union_flat(TestInputVisitorData *data, Error *err = NULL; UserDefFlatUnion *tmp; - v = visitor_input_test_init(data, "{ 'string': 'a', 'boolean': true }"); + v = visitor_input_test_init(data, + "{ 'enum1': 'value1', " + "'string': 'str', " + "'boolean': true }"); /* TODO when generator bug is fixed, add 'integer': 41 */ visit_type_UserDefFlatUnion(v, &tmp, NULL, &err); g_assert(err == NULL); - g_assert_cmpint(tmp->kind, ==, USER_DEF_UNION_KIND_A); + g_assert_cmpint(tmp->kind, ==, ENUM_ONE_VALUE1); + g_assert_cmpstr(tmp->string, ==, "str"); /* TODO g_assert_cmpint(tmp->integer, ==, 41); */ - g_assert_cmpint(tmp->a->boolean, ==, true); + g_assert_cmpint(tmp->value1->boolean, ==, true); qapi_free_UserDefFlatUnion(tmp); } diff --git a/tests/test-qmp-output-visitor.c b/tests/test-qmp-output-visitor.c index 105f4cf..da27971 100644 --- a/tests/test-qmp-output-visitor.c +++ b/tests/test-qmp-output-visitor.c @@ -449,10 +449,11 @@ static void test_visitor_out_union_flat(TestOutputVisitorData *data, Error *err = NULL; UserDefFlatUnion *tmp = g_malloc0(sizeof(UserDefFlatUnion)); - tmp->kind = USER_DEF_UNION_KIND_A; - tmp->a = g_malloc0(sizeof(UserDefA)); + tmp->kind = ENUM_ONE_VALUE1; + tmp->string = g_strdup("str"); + tmp->value1 = g_malloc0(sizeof(UserDefA)); /* TODO when generator bug is fixed: tmp->integer = 41; */ - tmp->a->boolean = true; + tmp->value1->boolean = true; visit_type_UserDefFlatUnion(data->ov, &tmp, NULL, &err); g_assert(err == NULL); @@ -461,7 +462,8 @@ static void test_visitor_out_union_flat(TestOutputVisitorData *data, g_assert(qobject_type(arg) == QTYPE_QDICT); qdict = qobject_to_qdict(arg); - g_assert_cmpstr(qdict_get_str(qdict, "string"), ==, "a"); + g_assert_cmpstr(qdict_get_str(qdict, "enum1"), ==, "value1"); + g_assert_cmpstr(qdict_get_str(qdict, "string"), ==, "str"); /* TODO g_assert_cmpint(qdict_get_int(qdict, "integer"), ==, 41); */ g_assert_cmpint(qdict_get_bool(qdict, "boolean"), ==, true); diff --git a/tests/test-rfifolock.c b/tests/test-rfifolock.c new file mode 100644 index 0000000..0572ebb --- /dev/null +++ b/tests/test-rfifolock.c @@ -0,0 +1,91 @@ +/* + * RFifoLock tests + * + * Copyright Red Hat, Inc. 2013 + * + * Authors: + * Stefan Hajnoczi <stefanha@redhat.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2 or later. + * See the COPYING.LIB file in the top-level directory. + */ + +#include <glib.h> +#include "qemu-common.h" +#include "qemu/rfifolock.h" + +static void test_nesting(void) +{ + RFifoLock lock; + + /* Trivial test, ensure the lock is recursive */ + rfifolock_init(&lock, NULL, NULL); + rfifolock_lock(&lock); + rfifolock_lock(&lock); + rfifolock_lock(&lock); + rfifolock_unlock(&lock); + rfifolock_unlock(&lock); + rfifolock_unlock(&lock); + rfifolock_destroy(&lock); +} + +typedef struct { + RFifoLock lock; + int fd[2]; +} CallbackTestData; + +static void rfifolock_cb(void *opaque) +{ + CallbackTestData *data = opaque; + int ret; + char c = 0; + + ret = write(data->fd[1], &c, sizeof(c)); + g_assert(ret == 1); +} + +static void *callback_thread(void *opaque) +{ + CallbackTestData *data = opaque; + + /* The other thread holds the lock so the contention callback will be + * invoked... + */ + rfifolock_lock(&data->lock); + rfifolock_unlock(&data->lock); + return NULL; +} + +static void test_callback(void) +{ + CallbackTestData data; + QemuThread thread; + int ret; + char c; + + rfifolock_init(&data.lock, rfifolock_cb, &data); + ret = qemu_pipe(data.fd); + g_assert(ret == 0); + + /* Hold lock but allow the callback to kick us by writing to the pipe */ + rfifolock_lock(&data.lock); + qemu_thread_create(&thread, "callback_thread", + callback_thread, &data, QEMU_THREAD_JOINABLE); + ret = read(data.fd[0], &c, sizeof(c)); + g_assert(ret == 1); + rfifolock_unlock(&data.lock); + /* If we got here then the callback was invoked, as expected */ + + qemu_thread_join(&thread); + close(data.fd[0]); + close(data.fd[1]); + rfifolock_destroy(&data.lock); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + g_test_add_func("/nesting", test_nesting); + g_test_add_func("/callback", test_callback); + return g_test_run(); +} diff --git a/tests/virtio-balloon-test.c b/tests/virtio-balloon-test.c new file mode 100644 index 0000000..becebb5 --- /dev/null +++ b/tests/virtio-balloon-test.c @@ -0,0 +1,33 @@ +/* + * QTest testcase for VirtIO Balloon + * + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include <glib.h> +#include <string.h> +#include "libqtest.h" +#include "qemu/osdep.h" + +/* Tests only initialization so far. TODO: Replace with functional tests */ +static void pci_nop(void) +{ +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/virtio/balloon/pci/nop", pci_nop); + + qtest_start("-device virtio-balloon-pci"); + ret = g_test_run(); + + qtest_end(); + + return ret; +} diff --git a/tests/virtio-blk-test.c b/tests/virtio-blk-test.c new file mode 100644 index 0000000..d53f875 --- /dev/null +++ b/tests/virtio-blk-test.c @@ -0,0 +1,34 @@ +/* + * QTest testcase for VirtIO Block Device + * + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include <glib.h> +#include <string.h> +#include "libqtest.h" +#include "qemu/osdep.h" + +/* Tests only initialization so far. TODO: Replace with functional tests */ +static void pci_nop(void) +{ +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/virtio/blk/pci/nop", pci_nop); + + qtest_start("-drive id=drv0,if=none,file=/dev/null " + "-device virtio-blk-pci,drive=drv0"); + ret = g_test_run(); + + qtest_end(); + + return ret; +} diff --git a/tests/virtio-console-test.c b/tests/virtio-console-test.c new file mode 100644 index 0000000..6be96e8 --- /dev/null +++ b/tests/virtio-console-test.c @@ -0,0 +1,41 @@ +/* + * QTest testcase for VirtIO Console + * + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include <glib.h> +#include <string.h> +#include "libqtest.h" +#include "qemu/osdep.h" + +/* Tests only initialization so far. TODO: Replace with functional tests */ +static void console_pci_nop(void) +{ + qtest_start("-device virtio-serial-pci,id=vser0 " + "-device virtconsole,bus=vser0.0"); + qtest_end(); +} + +static void serialport_pci_nop(void) +{ + qtest_start("-device virtio-serial-pci,id=vser0 " + "-device virtserialport,bus=vser0.0"); + qtest_end(); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/virtio/console/pci/nop", console_pci_nop); + qtest_add_func("/virtio/serialport/pci/nop", serialport_pci_nop); + + ret = g_test_run(); + + return ret; +} diff --git a/tests/virtio-rng-test.c b/tests/virtio-rng-test.c new file mode 100644 index 0000000..402c206 --- /dev/null +++ b/tests/virtio-rng-test.c @@ -0,0 +1,33 @@ +/* + * QTest testcase for VirtIO RNG + * + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include <glib.h> +#include <string.h> +#include "libqtest.h" +#include "qemu/osdep.h" + +/* Tests only initialization so far. TODO: Replace with functional tests */ +static void pci_nop(void) +{ +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/virtio/rng/pci/nop", pci_nop); + + qtest_start("-device virtio-rng-pci"); + ret = g_test_run(); + + qtest_end(); + + return ret; +} diff --git a/tests/virtio-scsi-test.c b/tests/virtio-scsi-test.c new file mode 100644 index 0000000..3230908 --- /dev/null +++ b/tests/virtio-scsi-test.c @@ -0,0 +1,35 @@ +/* + * QTest testcase for VirtIO SCSI + * + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include <glib.h> +#include <string.h> +#include "libqtest.h" +#include "qemu/osdep.h" + +/* Tests only initialization so far. TODO: Replace with functional tests */ +static void pci_nop(void) +{ +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/virtio/scsi/pci/nop", pci_nop); + + qtest_start("-drive id=drv0,if=none,file=/dev/null " + "-device virtio-scsi-pci,id=vscsi0 " + "-device scsi-hd,bus=vscsi0.0,drive=drv0"); + ret = g_test_run(); + + qtest_end(); + + return ret; +} diff --git a/tests/virtio-serial-test.c b/tests/virtio-serial-test.c new file mode 100644 index 0000000..e743875 --- /dev/null +++ b/tests/virtio-serial-test.c @@ -0,0 +1,33 @@ +/* + * QTest testcase for VirtIO Serial + * + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include <glib.h> +#include <string.h> +#include "libqtest.h" +#include "qemu/osdep.h" + +/* Tests only initialization so far. TODO: Replace with functional tests */ +static void pci_nop(void) +{ +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/virtio/serial/pci/nop", pci_nop); + + qtest_start("-device virtio-serial-pci"); + ret = g_test_run(); + + qtest_end(); + + return ret; +} diff --git a/trace-events b/trace-events index aec4202..002c260 100644 --- a/trace-events +++ b/trace-events @@ -486,6 +486,7 @@ runstate_set(int new_state) "new state %d" g_malloc(size_t size, void *ptr) "size %zu ptr %p" g_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p" g_free(void *ptr) "ptr %p" +system_wakeup_request(int reason) "reason=%d" # block/qcow2.c qcow2_writev_start_req(void *co, int64_t sector, int nb_sectors) "co %p sector %" PRIx64 " nb_sectors %d" @@ -1039,8 +1040,8 @@ vmware_scratch_write(uint32_t index, uint32_t value) "index %d, value 0x%x" vmware_setmode(uint32_t w, uint32_t h, uint32_t bpp) "%dx%d @ %d bpp" # savevm.c -savevm_section_start(void) "" -savevm_section_end(unsigned int section_id) "section_id %u" +savevm_section_start(const char *id, unsigned int section_id) "%s, section_id %u" +savevm_section_end(const char *id, unsigned int section_id) "%s, section_id %u" # arch_init.c migration_bitmap_sync_start(void) "" diff --git a/trace/control-internal.h b/trace/control-internal.h index cce2da4..b3f587e 100644 --- a/trace/control-internal.h +++ b/trace/control-internal.h @@ -16,15 +16,15 @@ extern TraceEvent trace_events[]; -static inline TraceEvent *trace_event_id(TraceEventID id) +static inline TraceEventID trace_event_count(void) { - assert(id < trace_event_count()); - return &trace_events[id]; + return TRACE_EVENT_COUNT; } -static inline TraceEventID trace_event_count(void) +static inline TraceEvent *trace_event_id(TraceEventID id) { - return TRACE_EVENT_COUNT; + assert(id < trace_event_count()); + return &trace_events[id]; } static inline bool trace_event_is_pattern(const char *str) diff --git a/translate-all.c b/translate-all.c index 1ac0246..f243c10 100644 --- a/translate-all.c +++ b/translate-all.c @@ -197,9 +197,10 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr /* The cpu state corresponding to 'searched_pc' is restored. */ -static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, +static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc) { + CPUArchState *env = cpu->env_ptr; TCGContext *s = &tcg_ctx; int j; uintptr_t tc_ptr; @@ -216,9 +217,9 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, if (use_icount) { /* Reset the cycle counter to the start of the block. */ - env->icount_decr.u16.low += tb->icount; + cpu->icount_decr.u16.low += tb->icount; /* Clear the IO flag. */ - env->can_do_io = 0; + cpu->can_do_io = 0; } /* find opc index corresponding to search_pc */ @@ -241,7 +242,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, while (s->gen_opc_instr_start[j] == 0) { j--; } - env->icount_decr.u16.low -= s->gen_opc_icount[j]; + cpu->icount_decr.u16.low -= s->gen_opc_icount[j]; restore_state_to_opc(env, tb, j); @@ -252,13 +253,13 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, return 0; } -bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr) +bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) { TranslationBlock *tb; tb = tb_find_pc(retaddr); if (tb) { - cpu_restore_state_from_tb(tb, env, retaddr); + cpu_restore_state_from_tb(cpu, tb, retaddr); return true; } return false; @@ -687,7 +688,7 @@ static void page_flush_tb(void) /* XXX: tb_flush is currently not thread safe */ void tb_flush(CPUArchState *env1) { - CPUState *cpu; + CPUState *cpu = ENV_GET_CPU(env1); #if defined(DEBUG_FLUSH) printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", @@ -698,14 +699,12 @@ void tb_flush(CPUArchState *env1) #endif if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { - cpu_abort(env1, "Internal error: code buffer overflow\n"); + cpu_abort(cpu, "Internal error: code buffer overflow\n"); } tcg_ctx.tb_ctx.nb_tbs = 0; CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - - memset(env->tb_jmp_cache, 0, sizeof(env->tb_jmp_cache)); + memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); } memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash)); @@ -856,10 +855,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) /* remove the TB from the hash list */ h = tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - - if (env->tb_jmp_cache[h] == tb) { - env->tb_jmp_cache[h] = NULL; + if (cpu->tb_jmp_cache[h] == tb) { + cpu->tb_jmp_cache[h] = NULL; } } @@ -941,10 +938,11 @@ static void build_page_bitmap(PageDesc *p) } } -TranslationBlock *tb_gen_code(CPUArchState *env, +TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, int cflags) { + CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; uint8_t *tc_ptr; tb_page_addr_t phys_pc, phys_page2; @@ -1009,7 +1007,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, { TranslationBlock *tb, *tb_next, *saved_tb; CPUState *cpu = current_cpu; -#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) +#if defined(TARGET_HAS_PRECISE_SMC) CPUArchState *env = NULL; #endif tb_page_addr_t tb_start, tb_end; @@ -1034,7 +1032,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, /* build code bitmap */ build_page_bitmap(p); } -#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) +#if defined(TARGET_HAS_PRECISE_SMC) if (cpu != NULL) { env = cpu->env_ptr; } @@ -1063,9 +1061,9 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, if (current_tb_not_found) { current_tb_not_found = 0; current_tb = NULL; - if (env->mem_io_pc) { + if (cpu->mem_io_pc) { /* now we have a real cpu fault */ - current_tb = tb_find_pc(env->mem_io_pc); + current_tb = tb_find_pc(cpu->mem_io_pc); } } if (current_tb == tb && @@ -1077,7 +1075,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, restore the CPU state */ current_tb_modified = 1; - cpu_restore_state_from_tb(current_tb, env, env->mem_io_pc); + cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } @@ -1104,7 +1102,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, if (!p->first_tb) { invalidate_page_bitmap(p); if (is_cpu_write_access) { - tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); + tlb_unprotect_code_phys(cpu, start, cpu->mem_io_vaddr); } } #endif @@ -1114,8 +1112,8 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); - cpu_resume_from_signal(env, NULL); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); + cpu_resume_from_signal(cpu, NULL); } #endif } @@ -1196,7 +1194,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr, restore the CPU state */ current_tb_modified = 1; - cpu_restore_state_from_tb(current_tb, env, pc); + cpu_restore_state_from_tb(cpu, current_tb, pc); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } @@ -1211,11 +1209,11 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr, modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); if (locked) { mmap_unlock(); } - cpu_resume_from_signal(env, puc); + cpu_resume_from_signal(cpu, puc); } #endif } @@ -1374,16 +1372,16 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) } #endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */ -void tb_check_watchpoint(CPUArchState *env) +void tb_check_watchpoint(CPUState *cpu) { TranslationBlock *tb; - tb = tb_find_pc(env->mem_io_pc); + tb = tb_find_pc(cpu->mem_io_pc); if (!tb) { - cpu_abort(env, "check_watchpoint: could not find TB for pc=%p", - (void *)env->mem_io_pc); + cpu_abort(cpu, "check_watchpoint: could not find TB for pc=%p", + (void *)cpu->mem_io_pc); } - cpu_restore_state_from_tb(tb, env, env->mem_io_pc); + cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc); tb_phys_invalidate(tb, -1); } @@ -1391,7 +1389,6 @@ void tb_check_watchpoint(CPUArchState *env) /* mask must never be zero, except for A20 change call */ static void tcg_handle_interrupt(CPUState *cpu, int mask) { - CPUArchState *env = cpu->env_ptr; int old_mask; old_mask = cpu->interrupt_request; @@ -1407,10 +1404,10 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) } if (use_icount) { - env->icount_decr.u16.high = 0xffff; - if (!can_do_io(env) + cpu->icount_decr.u16.high = 0xffff; + if (!cpu_can_do_io(cpu) && (mask & ~old_mask) != 0) { - cpu_abort(env, "Raised interrupt while not in I/O function"); + cpu_abort(cpu, "Raised interrupt while not in I/O function"); } } else { cpu->tcg_exit_req = 1; @@ -1421,8 +1418,11 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; /* in deterministic execution mode, instructions doing device I/Os must be at the end of the TB */ -void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) +void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) { +#if defined(TARGET_MIPS) || defined(TARGET_SH4) + CPUArchState *env = cpu->env_ptr; +#endif TranslationBlock *tb; uint32_t n, cflags; target_ulong pc, cs_base; @@ -1430,14 +1430,14 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) tb = tb_find_pc(retaddr); if (!tb) { - cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", + cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", (void *)retaddr); } - n = env->icount_decr.u16.low + tb->icount; - cpu_restore_state_from_tb(tb, env, retaddr); + n = cpu->icount_decr.u16.low + tb->icount; + cpu_restore_state_from_tb(cpu, tb, retaddr); /* Calculate how many instructions had been executed before the fault occurred. */ - n = n - env->icount_decr.u16.low; + n = n - cpu->icount_decr.u16.low; /* Generate a new TB ending on the I/O insn. */ n++; /* On MIPS and SH, delay slot instructions can only be restarted if @@ -1447,20 +1447,20 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) #if defined(TARGET_MIPS) if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { env->active_tc.PC -= 4; - env->icount_decr.u16.low++; + cpu->icount_decr.u16.low++; env->hflags &= ~MIPS_HFLAG_BMASK; } #elif defined(TARGET_SH4) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 && n > 1) { env->pc -= 2; - env->icount_decr.u16.low++; + cpu->icount_decr.u16.low++; env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); } #endif /* This should never happen. */ if (n > CF_COUNT_MASK) { - cpu_abort(env, "TB too big during recompile"); + cpu_abort(cpu, "TB too big during recompile"); } cflags = n | CF_LAST_IO; @@ -1470,27 +1470,27 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) tb_phys_invalidate(tb, -1); /* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ - tb_gen_code(env, pc, cs_base, flags, cflags); + tb_gen_code(cpu, pc, cs_base, flags, cflags); /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not the first in the TB) then we end up generating a whole new TB and repeating the fault, which is horribly inefficient. Better would be to execute just this insn uncached, or generate a second new TB. */ - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); } -void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr) +void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) { unsigned int i; /* Discard jump cache entries for any tb which might potentially overlap the flushed page. */ i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); - memset(&env->tb_jmp_cache[i], 0, + memset(&cpu->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); i = tb_jmp_cache_hash_page(addr); - memset(&env->tb_jmp_cache[i], 0, + memset(&cpu->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); } diff --git a/translate-all.h b/translate-all.h index f7e5932..02832b2 100644 --- a/translate-all.h +++ b/translate-all.h @@ -22,6 +22,6 @@ /* translate-all.c */ void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len); void cpu_unlink_tb(CPUState *cpu); -void tb_check_watchpoint(CPUArchState *env); +void tb_check_watchpoint(CPUState *cpu); #endif /* TRANSLATE_ALL_H */ diff --git a/ui/console.c b/ui/console.c index 4df251d..e057755 100644 --- a/ui/console.c +++ b/ui/console.c @@ -1180,7 +1180,10 @@ static QemuConsole *new_console(DisplayState *ds, console_type_t console_type) obj = object_new(TYPE_QEMU_CONSOLE); s = QEMU_CONSOLE(obj); object_property_add_link(obj, "device", TYPE_DEVICE, - (Object **)&s->device, &local_err); + (Object **)&s->device, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &local_err); object_property_add_uint32_ptr(obj, "head", &s->head, &local_err); @@ -340,13 +340,17 @@ static void gd_mouse_set(DisplayChangeListener *dcl, GdkDeviceManager *mgr; gint x_root, y_root; + if (qemu_input_is_absolute()) { + return; + } + dpy = gtk_widget_get_display(s->drawing_area); mgr = gdk_display_get_device_manager(dpy); gdk_window_get_root_coords(gtk_widget_get_window(s->drawing_area), x, y, &x_root, &y_root); gdk_device_warp(gdk_device_manager_get_client_pointer(mgr), gtk_widget_get_screen(s->drawing_area), - x, y); + x_root, y_root); } #else static void gd_mouse_set(DisplayChangeListener *dcl, @@ -355,6 +359,10 @@ static void gd_mouse_set(DisplayChangeListener *dcl, GtkDisplayState *s = container_of(dcl, GtkDisplayState, dcl); gint x_root, y_root; + if (qemu_input_is_absolute()) { + return; + } + gdk_window_get_root_coords(gtk_widget_get_window(s->drawing_area), x, y, &x_root, &y_root); gdk_display_warp_pointer(gtk_widget_get_display(s->drawing_area), @@ -683,6 +691,27 @@ static gboolean gd_button_event(GtkWidget *widget, GdkEventButton *button, return TRUE; } +static gboolean gd_scroll_event(GtkWidget *widget, GdkEventScroll *scroll, + void *opaque) +{ + GtkDisplayState *s = opaque; + InputButton btn; + + if (scroll->direction == GDK_SCROLL_UP) { + btn = INPUT_BUTTON_WHEEL_UP; + } else if (scroll->direction == GDK_SCROLL_DOWN) { + btn = INPUT_BUTTON_WHEEL_DOWN; + } else { + return TRUE; + } + + qemu_input_queue_btn(s->dcl.con, btn, true); + qemu_input_event_sync(); + qemu_input_queue_btn(s->dcl.con, btn, false); + qemu_input_event_sync(); + return TRUE; +} + static gboolean gd_key_event(GtkWidget *widget, GdkEventKey *key, void *opaque) { GtkDisplayState *s = opaque; @@ -1229,6 +1258,8 @@ static void gd_connect_signals(GtkDisplayState *s) G_CALLBACK(gd_button_event), s); g_signal_connect(s->drawing_area, "button-release-event", G_CALLBACK(gd_button_event), s); + g_signal_connect(s->drawing_area, "scroll-event", + G_CALLBACK(gd_scroll_event), s); g_signal_connect(s->drawing_area, "key-press-event", G_CALLBACK(gd_key_event), s); g_signal_connect(s->drawing_area, "key-release-event", @@ -1415,7 +1446,7 @@ static const DisplayChangeListenerOps dcl_ops = { .dpy_cursor_define = gd_cursor_define, }; -void gtk_display_init(DisplayState *ds, bool full_screen) +void gtk_display_init(DisplayState *ds, bool full_screen, bool grab_on_hover) { GtkDisplayState *s = g_malloc0(sizeof(*s)); char *filename; @@ -1494,6 +1525,9 @@ void gtk_display_init(DisplayState *ds, bool full_screen) if (full_screen) { gtk_menu_item_activate(GTK_MENU_ITEM(s->full_screen_item)); } + if (grab_on_hover) { + gtk_menu_item_activate(GTK_MENU_ITEM(s->grab_on_hover_item)); + } register_displaychangelistener(&s->dcl); diff --git a/ui/input-legacy.c b/ui/input-legacy.c index f38984b..1aa2605 100644 --- a/ui/input-legacy.c +++ b/ui/input-legacy.c @@ -333,6 +333,7 @@ QEMUPutKbdEntry *qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque) entry->opaque = opaque; entry->s = qemu_input_handler_register((DeviceState *)entry, &legacy_kbd_handler); + qemu_input_handler_activate(entry->s); return entry; } @@ -359,6 +360,20 @@ static void legacy_mouse_event(DeviceState *dev, QemuConsole *src, } else { s->buttons &= ~bmap[evt->btn->button]; } + if (evt->btn->down && evt->btn->button == INPUT_BUTTON_WHEEL_UP) { + s->qemu_put_mouse_event(s->qemu_put_mouse_event_opaque, + s->axis[INPUT_AXIS_X], + s->axis[INPUT_AXIS_Y], + -1, + s->buttons); + } + if (evt->btn->down && evt->btn->button == INPUT_BUTTON_WHEEL_DOWN) { + s->qemu_put_mouse_event(s->qemu_put_mouse_event_opaque, + s->axis[INPUT_AXIS_X], + s->axis[INPUT_AXIS_Y], + 1, + s->buttons); + } break; case INPUT_EVENT_KIND_ABS: s->axis[evt->abs->axis] = evt->abs->value; @@ -455,13 +455,17 @@ static void sdl_send_mouse_event(int dx, int dy, int x, int y, int state) real_screen->w); qemu_input_queue_abs(dcl->con, INPUT_AXIS_Y, y, real_screen->h); - } else if (guest_cursor) { - x -= guest_x; - y -= guest_y; - guest_x += x; - guest_y += y; - qemu_input_queue_rel(dcl->con, INPUT_AXIS_X, x); - qemu_input_queue_rel(dcl->con, INPUT_AXIS_Y, y); + } else { + if (guest_cursor) { + x -= guest_x; + y -= guest_y; + guest_x += x; + guest_y += y; + dx = x; + dy = y; + } + qemu_input_queue_rel(dcl->con, INPUT_AXIS_X, dx); + qemu_input_queue_rel(dcl->con, INPUT_AXIS_Y, dy); } qemu_input_event_sync(); } diff --git a/ui/spice-display.c b/ui/spice-display.c index 9bb42f1..e28698c 100644 --- a/ui/spice-display.c +++ b/ui/spice-display.c @@ -354,6 +354,7 @@ void qemu_spice_display_switch(SimpleSpiceDisplay *ssd, DisplaySurface *surface) { SimpleSpiceUpdate *update; + bool need_destroy; dprint(1, "%s/%d:\n", __func__, ssd->qxl.id); @@ -366,14 +367,19 @@ void qemu_spice_display_switch(SimpleSpiceDisplay *ssd, } qemu_mutex_lock(&ssd->lock); + need_destroy = (ssd->ds != NULL); ssd->ds = surface; while ((update = QTAILQ_FIRST(&ssd->updates)) != NULL) { QTAILQ_REMOVE(&ssd->updates, update, next); qemu_spice_destroy_update(ssd, update); } qemu_mutex_unlock(&ssd->lock); - qemu_spice_destroy_host_primary(ssd); - qemu_spice_create_host_primary(ssd); + if (need_destroy) { + qemu_spice_destroy_host_primary(ssd); + } + if (ssd->ds) { + qemu_spice_create_host_primary(ssd); + } memset(&ssd->dirty, 0, sizeof(ssd->dirty)); ssd->notify++; @@ -537,10 +543,29 @@ static void interface_set_client_capabilities(QXLInstance *sin, } static int interface_client_monitors_config(QXLInstance *sin, - VDAgentMonitorsConfig *monitors_config) + VDAgentMonitorsConfig *mc) { - dprint(3, "%s:\n", __func__); - return 0; /* == not supported by guest */ + SimpleSpiceDisplay *ssd = container_of(sin, SimpleSpiceDisplay, qxl); + QemuUIInfo info; + int rc; + + /* + * FIXME: multihead is tricky due to the way + * spice has multihead implemented. + */ + memset(&info, 0, sizeof(info)); + if (mc->num_of_monitors > 0) { + info.width = mc->monitors[0].width; + info.height = mc->monitors[0].height; + } + rc = dpy_set_ui_info(ssd->dcl.con, &info); + dprint(1, "%s/%d: size %dx%d, rc %d <--- ==========================\n", + __func__, ssd->qxl.id, info.width, info.height, rc); + if (rc != 0) { + return 0; /* == not supported by guest */ + } else { + return 1; + } } static const QXLInterface dpy_interface = { @@ -610,8 +635,6 @@ static void qemu_spice_display_init_one(QemuConsole *con) ssd->dcl.ops = &display_listener_ops; ssd->dcl.con = con; register_displaychangelistener(&ssd->dcl); - - qemu_spice_create_host_primary(ssd); } void qemu_spice_display_init(void) diff --git a/ui/spice-input.c b/ui/spice-input.c index 6dab23b..c342e0d 100644 --- a/ui/spice-input.c +++ b/ui/spice-input.c @@ -176,7 +176,7 @@ static void tablet_position(SpiceTabletInstance* sin, int x, int y, spice_update_buttons(pointer, 0, buttons_state); qemu_input_queue_abs(NULL, INPUT_AXIS_X, x, pointer->width); - qemu_input_queue_abs(NULL, INPUT_AXIS_Y, y, pointer->width); + qemu_input_queue_abs(NULL, INPUT_AXIS_Y, y, pointer->height); qemu_input_event_sync(); } diff --git a/ui/vnc-enc-tight.c b/ui/vnc-enc-tight.c index e6966ae..59b59c0 100644 --- a/ui/vnc-enc-tight.c +++ b/ui/vnc-enc-tight.c @@ -330,7 +330,7 @@ tight_detect_smooth_image(VncState *vs, int w, int h) } else { errors = tight_detect_smooth_image16(vs, w, h); } - if (quality != -1) { + if (quality != (uint8_t)-1) { return (errors < tight_conf[quality].jpeg_threshold); } return (errors < tight_conf[compression].gradient_threshold); diff --git a/ui/vnc-jobs.c b/ui/vnc-jobs.c index 3f3c47b..68f3d77 100644 --- a/ui/vnc-jobs.c +++ b/ui/vnc-jobs.c @@ -252,6 +252,8 @@ static int vnc_worker_thread_loop(VncJobQueue *queue) if (job->vs->csock == -1) { vnc_unlock_display(job->vs->vd); + /* Copy persistent encoding data */ + vnc_async_encoding_end(job->vs, &vs); goto disconnected; } @@ -278,6 +280,9 @@ static int vnc_worker_thread_loop(VncJobQueue *queue) vnc_async_encoding_end(job->vs, &vs); qemu_bh_schedule(job->vs->bh); + } else { + /* Copy persistent encoding data */ + vnc_async_encoding_end(job->vs, &vs); } vnc_unlock_output(job->vs); @@ -417,8 +417,7 @@ out_error: 3) resolutions > 1024 */ -static int vnc_update_client(VncState *vs, int has_dirty); -static int vnc_update_client_sync(VncState *vs, int has_dirty); +static int vnc_update_client(VncState *vs, int has_dirty, bool sync); static void vnc_disconnect_start(VncState *vs); static void vnc_colordepth(VncState *vs); @@ -431,29 +430,25 @@ static int vnc_refresh_server_surface(VncDisplay *vd); static void vnc_dpy_update(DisplayChangeListener *dcl, int x, int y, int w, int h) { - int i; VncDisplay *vd = container_of(dcl, VncDisplay, dcl); struct VncSurface *s = &vd->guest; int width = surface_width(vd->ds); int height = surface_height(vd->ds); - h += y; - - /* round x down to ensure the loop only spans one 16-pixel block per, - iteration. otherwise, if (x % 16) != 0, the last iteration may span - two 16-pixel blocks but we only mark the first as dirty - */ - w += (x % 16); - x -= (x % 16); + /* this is needed this to ensure we updated all affected + * blocks if x % VNC_DIRTY_PIXELS_PER_BIT != 0 */ + w += (x % VNC_DIRTY_PIXELS_PER_BIT); + x -= (x % VNC_DIRTY_PIXELS_PER_BIT); x = MIN(x, width); y = MIN(y, height); w = MIN(x + w, width) - x; - h = MIN(h, height); + h = MIN(y + h, height); - for (; y < h; y++) - for (i = 0; i < w; i += 16) - set_bit((x + i) / 16, s->dirty[y]); + for (; y < h; y++) { + bitmap_set(s->dirty[y], x / VNC_DIRTY_PIXELS_PER_BIT, + DIV_ROUND_UP(w, VNC_DIRTY_PIXELS_PER_BIT)); + } } void vnc_framebuffer_update(VncState *vs, int x, int y, int w, int h, @@ -571,6 +566,15 @@ void *vnc_server_fb_ptr(VncDisplay *vd, int x, int y) ptr += x * VNC_SERVER_FB_BYTES; return ptr; } +/* this sets only the visible pixels of a dirty bitmap */ +#define VNC_SET_VISIBLE_PIXELS_DIRTY(bitmap, w, h) {\ + int y;\ + memset(bitmap, 0x00, sizeof(bitmap));\ + for (y = 0; y < h; y++) {\ + bitmap_set(bitmap[y], 0,\ + DIV_ROUND_UP(w, VNC_DIRTY_PIXELS_PER_BIT));\ + } \ + } static void vnc_dpy_switch(DisplayChangeListener *dcl, DisplaySurface *surface) @@ -596,7 +600,9 @@ static void vnc_dpy_switch(DisplayChangeListener *dcl, qemu_pixman_image_unref(vd->guest.fb); vd->guest.fb = pixman_image_ref(surface->image); vd->guest.format = surface->format; - memset(vd->guest.dirty, 0xFF, sizeof(vd->guest.dirty)); + VNC_SET_VISIBLE_PIXELS_DIRTY(vd->guest.dirty, + surface_width(vd->ds), + surface_height(vd->ds)); QTAILQ_FOREACH(vs, &vd->clients, next) { vnc_colordepth(vs); @@ -604,7 +610,9 @@ static void vnc_dpy_switch(DisplayChangeListener *dcl, if (vs->vd->cursor) { vnc_cursor_define(vs); } - memset(vs->dirty, 0xFF, sizeof(vs->dirty)); + VNC_SET_VISIBLE_PIXELS_DIRTY(vs->dirty, + surface_width(vd->ds), + surface_height(vd->ds)); } } @@ -751,7 +759,7 @@ static void vnc_dpy_copy(DisplayChangeListener *dcl, QTAILQ_FOREACH_SAFE(vs, &vd->clients, next, vn) { if (vnc_has_feature(vs, VNC_FEATURE_COPYRECT)) { vs->force_update = 1; - vnc_update_client_sync(vs, 1); + vnc_update_client(vs, 1, true); /* vs might be free()ed here */ } } @@ -770,11 +778,12 @@ static void vnc_dpy_copy(DisplayChangeListener *dcl, y = dst_y + h - 1; inc = -1; } - w_lim = w - (16 - (dst_x % 16)); - if (w_lim < 0) + w_lim = w - (VNC_DIRTY_PIXELS_PER_BIT - (dst_x % VNC_DIRTY_PIXELS_PER_BIT)); + if (w_lim < 0) { w_lim = w; - else - w_lim = w - (w_lim % 16); + } else { + w_lim = w - (w_lim % VNC_DIRTY_PIXELS_PER_BIT); + } for (i = 0; i < h; i++) { for (x = 0; x <= w_lim; x += s, src_row += cmp_bytes, dst_row += cmp_bytes) { @@ -782,10 +791,11 @@ static void vnc_dpy_copy(DisplayChangeListener *dcl, if ((s = w - w_lim) == 0) break; } else if (!x) { - s = (16 - (dst_x % 16)); + s = (VNC_DIRTY_PIXELS_PER_BIT - + (dst_x % VNC_DIRTY_PIXELS_PER_BIT)); s = MIN(s, w_lim); } else { - s = 16; + s = VNC_DIRTY_PIXELS_PER_BIT; } cmp_bytes = s * VNC_SERVER_FB_BYTES; if (memcmp(src_row, dst_row, cmp_bytes) == 0) @@ -793,7 +803,8 @@ static void vnc_dpy_copy(DisplayChangeListener *dcl, memmove(dst_row, src_row, cmp_bytes); QTAILQ_FOREACH(vs, &vd->clients, next) { if (!vnc_has_feature(vs, VNC_FEATURE_COPYRECT)) { - set_bit(((x + dst_x) / 16), vs->dirty[y]); + set_bit(((x + dst_x) / VNC_DIRTY_PIXELS_PER_BIT), + vs->dirty[y]); } } } @@ -862,35 +873,24 @@ static int find_and_clear_dirty_height(struct VncState *vs, int h; for (h = 1; h < (height - y); h++) { - int tmp_x; if (!test_bit(last_x, vs->dirty[y + h])) { break; } - for (tmp_x = last_x; tmp_x < x; tmp_x++) { - clear_bit(tmp_x, vs->dirty[y + h]); - } + bitmap_clear(vs->dirty[y + h], last_x, x - last_x); } return h; } -static int vnc_update_client_sync(VncState *vs, int has_dirty) -{ - int ret = vnc_update_client(vs, has_dirty); - vnc_jobs_join(vs); - return ret; -} - -static int vnc_update_client(VncState *vs, int has_dirty) +static int vnc_update_client(VncState *vs, int has_dirty, bool sync) { if (vs->need_update && vs->csock != -1) { VncDisplay *vd = vs->vd; VncJob *job; int y; - int width, height; + int height, width; int n = 0; - if (vs->output.offset && !vs->audio_cap && !vs->force_update) /* kernel send buffers are full -> drop frames to throttle */ return 0; @@ -906,32 +906,30 @@ static int vnc_update_client(VncState *vs, int has_dirty) */ job = vnc_job_new(vs); - width = MIN(pixman_image_get_width(vd->server), vs->client_width); height = MIN(pixman_image_get_height(vd->server), vs->client_height); + width = MIN(pixman_image_get_width(vd->server), vs->client_width); - for (y = 0; y < height; y++) { - int x; - int last_x = -1; - for (x = 0; x < width / 16; x++) { - if (test_and_clear_bit(x, vs->dirty[y])) { - if (last_x == -1) { - last_x = x; - } - } else { - if (last_x != -1) { - int h = find_and_clear_dirty_height(vs, y, last_x, x, - height); - - n += vnc_job_add_rect(job, last_x * 16, y, - (x - last_x) * 16, h); - } - last_x = -1; - } + y = 0; + for (;;) { + int x, h; + unsigned long x2; + unsigned long offset = find_next_bit((unsigned long *) &vs->dirty, + height * VNC_DIRTY_BPL(vs), + y * VNC_DIRTY_BPL(vs)); + if (offset == height * VNC_DIRTY_BPL(vs)) { + /* no more dirty bits */ + break; } - if (last_x != -1) { - int h = find_and_clear_dirty_height(vs, y, last_x, x, height); - n += vnc_job_add_rect(job, last_x * 16, y, - (x - last_x) * 16, h); + y = offset / VNC_DIRTY_BPL(vs); + x = offset % VNC_DIRTY_BPL(vs); + x2 = find_next_zero_bit((unsigned long *) &vs->dirty[y], + VNC_DIRTY_BPL(vs), x); + bitmap_clear(vs->dirty[y], x, x2 - x); + h = find_and_clear_dirty_height(vs, y, x, x2, height); + x2 = MIN(x2, width / VNC_DIRTY_PIXELS_PER_BIT); + if (x2 > x) { + n += vnc_job_add_rect(job, x * VNC_DIRTY_PIXELS_PER_BIT, y, + (x2 - x) * VNC_DIRTY_PIXELS_PER_BIT, h); } } @@ -940,8 +938,11 @@ static int vnc_update_client(VncState *vs, int has_dirty) return n; } - if (vs->csock == -1) + if (vs->csock == -1) { vnc_disconnect_finish(vs); + } else if (sync) { + vnc_jobs_join(vs); + } return 0; } @@ -1846,7 +1847,7 @@ static void framebuffer_update_request(VncState *vs, int incremental, int w, int h) { int i; - const size_t width = surface_width(vs->vd->ds) / 16; + const size_t width = surface_width(vs->vd->ds) / VNC_DIRTY_PIXELS_PER_BIT; const size_t height = surface_height(vs->vd->ds); if (y_position > height) { @@ -2548,7 +2549,9 @@ static int vnc_refresh_lossy_rect(VncDisplay *vd, int x, int y) vs->lossy_rect[sty][stx] = 0; for (j = 0; j < VNC_STAT_RECT; ++j) { - bitmap_set(vs->dirty[y + j], x / 16, VNC_STAT_RECT / 16); + bitmap_set(vs->dirty[y + j], + x / VNC_DIRTY_PIXELS_PER_BIT, + VNC_STAT_RECT / VNC_DIRTY_PIXELS_PER_BIT); } has_dirty++; } @@ -2652,8 +2655,8 @@ static int vnc_refresh_server_surface(VncDisplay *vd) int width = pixman_image_get_width(vd->guest.fb); int height = pixman_image_get_height(vd->guest.fb); int y; - uint8_t *guest_row; - uint8_t *server_row; + uint8_t *guest_row0 = NULL, *server_row0; + int guest_stride = 0, server_stride; int cmp_bytes; VncState *vs; int has_dirty = 0; @@ -2671,47 +2674,64 @@ static int vnc_refresh_server_surface(VncDisplay *vd) * Check and copy modified bits from guest to server surface. * Update server dirty map. */ - cmp_bytes = 64; + cmp_bytes = VNC_DIRTY_PIXELS_PER_BIT * VNC_SERVER_FB_BYTES; if (cmp_bytes > vnc_server_fb_stride(vd)) { cmp_bytes = vnc_server_fb_stride(vd); } if (vd->guest.format != VNC_SERVER_FB_FORMAT) { int width = pixman_image_get_width(vd->server); tmpbuf = qemu_pixman_linebuf_create(VNC_SERVER_FB_FORMAT, width); - } - guest_row = (uint8_t *)pixman_image_get_data(vd->guest.fb); - server_row = (uint8_t *)pixman_image_get_data(vd->server); - for (y = 0; y < height; y++) { - if (!bitmap_empty(vd->guest.dirty[y], VNC_DIRTY_BITS)) { - int x; - uint8_t *guest_ptr; - uint8_t *server_ptr; - - if (vd->guest.format != VNC_SERVER_FB_FORMAT) { - qemu_pixman_linebuf_fill(tmpbuf, vd->guest.fb, width, 0, y); - guest_ptr = (uint8_t *)pixman_image_get_data(tmpbuf); - } else { - guest_ptr = guest_row; - } - server_ptr = server_row; + } else { + guest_row0 = (uint8_t *)pixman_image_get_data(vd->guest.fb); + guest_stride = pixman_image_get_stride(vd->guest.fb); + } + server_row0 = (uint8_t *)pixman_image_get_data(vd->server); + server_stride = pixman_image_get_stride(vd->server); + + y = 0; + for (;;) { + int x; + uint8_t *guest_ptr, *server_ptr; + unsigned long offset = find_next_bit((unsigned long *) &vd->guest.dirty, + height * VNC_DIRTY_BPL(&vd->guest), + y * VNC_DIRTY_BPL(&vd->guest)); + if (offset == height * VNC_DIRTY_BPL(&vd->guest)) { + /* no more dirty bits */ + break; + } + y = offset / VNC_DIRTY_BPL(&vd->guest); + x = offset % VNC_DIRTY_BPL(&vd->guest); - for (x = 0; x + 15 < width; - x += 16, guest_ptr += cmp_bytes, server_ptr += cmp_bytes) { - if (!test_and_clear_bit((x / 16), vd->guest.dirty[y])) - continue; - if (memcmp(server_ptr, guest_ptr, cmp_bytes) == 0) - continue; - memcpy(server_ptr, guest_ptr, cmp_bytes); - if (!vd->non_adaptive) - vnc_rect_updated(vd, x, y, &tv); - QTAILQ_FOREACH(vs, &vd->clients, next) { - set_bit((x / 16), vs->dirty[y]); - } - has_dirty++; + server_ptr = server_row0 + y * server_stride + x * cmp_bytes; + + if (vd->guest.format != VNC_SERVER_FB_FORMAT) { + qemu_pixman_linebuf_fill(tmpbuf, vd->guest.fb, width, 0, y); + guest_ptr = (uint8_t *)pixman_image_get_data(tmpbuf); + } else { + guest_ptr = guest_row0 + y * guest_stride; + } + guest_ptr += x * cmp_bytes; + + for (; x < DIV_ROUND_UP(width, VNC_DIRTY_PIXELS_PER_BIT); + x++, guest_ptr += cmp_bytes, server_ptr += cmp_bytes) { + if (!test_and_clear_bit(x, vd->guest.dirty[y])) { + continue; + } + if (memcmp(server_ptr, guest_ptr, cmp_bytes) == 0) { + continue; + } + memcpy(server_ptr, guest_ptr, cmp_bytes); + if (!vd->non_adaptive) { + vnc_rect_updated(vd, x * VNC_DIRTY_PIXELS_PER_BIT, + y, &tv); } + QTAILQ_FOREACH(vs, &vd->clients, next) { + set_bit(x, vs->dirty[y]); + } + has_dirty++; } - guest_row += pixman_image_get_stride(vd->guest.fb); - server_row += pixman_image_get_stride(vd->server); + + y++; } qemu_pixman_image_unref(tmpbuf); return has_dirty; @@ -2734,7 +2754,7 @@ static void vnc_refresh(DisplayChangeListener *dcl) vnc_unlock_display(vd); QTAILQ_FOREACH_SAFE(vs, &vd->clients, next, vn) { - rects += vnc_update_client(vs, has_dirty); + rects += vnc_update_client(vs, has_dirty, false); /* vs might be free()ed here */ } @@ -3134,7 +3154,9 @@ void vnc_display_open(DisplayState *ds, const char *display, Error **errp) acl = 1; #endif } else if (strncmp(options, "lossy", 5) == 0) { +#ifdef CONFIG_VNC_JPEG vs->lossy = true; +#endif } else if (strncmp(options, "non-adaptive", 12) == 0) { vs->non_adaptive = true; } else if (strncmp(options, "share=", 6) == 0) { @@ -3151,6 +3173,13 @@ void vnc_display_open(DisplayState *ds, const char *display, Error **errp) } } + /* adaptive updates are only used with tight encoding and + * if lossy updates are enabled so we can disable all the + * calculations otherwise */ + if (!vs->lossy) { + vs->non_adaptive = true; + } + #ifdef CONFIG_VNC_TLS if (acl && x509 && vs->tls.x509verify) { if (!(vs->tls.acl = qemu_acl_init("vnc.x509dname"))) { @@ -81,8 +81,16 @@ typedef void VncSendHextileTile(VncState *vs, #define VNC_MAX_WIDTH 2560 #define VNC_MAX_HEIGHT 2048 +/* VNC_DIRTY_PIXELS_PER_BIT is the number of dirty pixels represented + * by one bit in the dirty bitmap */ +#define VNC_DIRTY_PIXELS_PER_BIT 16 + /* VNC_DIRTY_BITS is the number of bits in the dirty bitmap. */ -#define VNC_DIRTY_BITS (VNC_MAX_WIDTH / 16) +#define VNC_DIRTY_BITS (VNC_MAX_WIDTH / VNC_DIRTY_PIXELS_PER_BIT) + +/* VNC_DIRTY_BPL (BPL = bits per line) might be greater than + * VNC_DIRTY_BITS due to alignment */ +#define VNC_DIRTY_BPL(x) (sizeof((x)->dirty) / VNC_MAX_HEIGHT * BITS_PER_BYTE) #define VNC_STAT_RECT 64 #define VNC_STAT_COLS (VNC_MAX_WIDTH / VNC_STAT_RECT) diff --git a/user-exec.c b/user-exec.c index 82bfa66..bc58056 100644 --- a/user-exec.c +++ b/user-exec.c @@ -38,19 +38,22 @@ //#define DEBUG_SIGNAL -static void exception_action(CPUArchState *env1) +static void exception_action(CPUState *cpu) { #if defined(TARGET_I386) - raise_exception_err(env1, env1->exception_index, env1->error_code); + X86CPU *x86_cpu = X86_CPU(cpu); + CPUX86State *env1 = &x86_cpu->env; + + raise_exception_err(env1, cpu->exception_index, env1->error_code); #else - cpu_loop_exit(env1); + cpu_loop_exit(cpu); #endif } /* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ -void cpu_resume_from_signal(CPUArchState *env1, void *puc) +void cpu_resume_from_signal(CPUState *cpu, void *puc) { #ifdef __linux__ struct ucontext *uc = puc; @@ -70,8 +73,8 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc) sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); #endif } - env1->exception_index = -1; - siglongjmp(env1->jmp_env, 1); + cpu->exception_index = -1; + siglongjmp(cpu->jmp_env, 1); } /* 'pc' is the host PC at which the exception was raised. 'address' is @@ -82,7 +85,8 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, int is_write, sigset_t *old_set, void *puc) { - CPUArchState *env; + CPUState *cpu; + CPUClass *cc; int ret; #if defined(DEBUG_SIGNAL) @@ -99,9 +103,11 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, are still valid segv ones */ address = h2g_nocheck(address); - env = current_cpu->env_ptr; + cpu = current_cpu; + cc = CPU_GET_CLASS(cpu); /* see if it is an MMU fault */ - ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX); + g_assert(cc->handle_mmu_fault); + ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX); if (ret < 0) { return 0; /* not an MMU fault */ } @@ -109,12 +115,12 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, return 1; /* the MMU fault was handled without causing real CPU fault */ } /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cpu, pc); /* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ sigprocmask(SIG_SETMASK, old_set, NULL); - exception_action(env); + exception_action(cpu); /* never comes here */ return 1; diff --git a/util/Makefile.objs b/util/Makefile.objs index 937376b..df83b62 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -14,3 +14,4 @@ util-obj-y += crc32c.o util-obj-y += throttle.o util-obj-y += getauxval.o util-obj-y += readline.o +util-obj-y += rfifolock.o diff --git a/util/oslib-posix.c b/util/oslib-posix.c index c2eeb4f..8e9c770 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -63,6 +63,10 @@ extern int daemon(int, int); #include <sys/syscall.h> #endif +#ifdef __FreeBSD__ +#include <sys/sysctl.h> +#endif + int qemu_get_thread_id(void) { #if defined(__linux__) diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c index 45113b4..960d7f5 100644 --- a/util/qemu-thread-posix.c +++ b/util/qemu-thread-posix.c @@ -420,7 +420,7 @@ void qemu_thread_create(QemuThread *thread, const char *name, if (err) error_exit(err, __func__); -#ifdef _GNU_SOURCE +#if defined(__GLIBC__) && (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 12)) if (name_threads) { pthread_setname_np(thread->thread, name); } diff --git a/util/rfifolock.c b/util/rfifolock.c new file mode 100644 index 0000000..afbf748 --- /dev/null +++ b/util/rfifolock.c @@ -0,0 +1,78 @@ +/* + * Recursive FIFO lock + * + * Copyright Red Hat, Inc. 2013 + * + * Authors: + * Stefan Hajnoczi <stefanha@redhat.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2 or later. + * See the COPYING.LIB file in the top-level directory. + * + */ + +#include <assert.h> +#include "qemu/rfifolock.h" + +void rfifolock_init(RFifoLock *r, void (*cb)(void *), void *opaque) +{ + qemu_mutex_init(&r->lock); + r->head = 0; + r->tail = 0; + qemu_cond_init(&r->cond); + r->nesting = 0; + r->cb = cb; + r->cb_opaque = opaque; +} + +void rfifolock_destroy(RFifoLock *r) +{ + qemu_cond_destroy(&r->cond); + qemu_mutex_destroy(&r->lock); +} + +/* + * Theory of operation: + * + * In order to ensure FIFO ordering, implement a ticketlock. Threads acquiring + * the lock enqueue themselves by incrementing the tail index. When the lock + * is unlocked, the head is incremented and waiting threads are notified. + * + * Recursive locking does not take a ticket since the head is only incremented + * when the outermost recursive caller unlocks. + */ +void rfifolock_lock(RFifoLock *r) +{ + qemu_mutex_lock(&r->lock); + + /* Take a ticket */ + unsigned int ticket = r->tail++; + + if (r->nesting > 0 && qemu_thread_is_self(&r->owner_thread)) { + r->tail--; /* put ticket back, we're nesting */ + } else { + while (ticket != r->head) { + /* Invoke optional contention callback */ + if (r->cb) { + r->cb(r->cb_opaque); + } + qemu_cond_wait(&r->cond, &r->lock); + } + } + + qemu_thread_get_self(&r->owner_thread); + r->nesting++; + qemu_mutex_unlock(&r->lock); +} + +void rfifolock_unlock(RFifoLock *r) +{ + qemu_mutex_lock(&r->lock); + assert(r->nesting > 0); + assert(qemu_thread_is_self(&r->owner_thread)); + if (--r->nesting == 0) { + r->head++; + qemu_cond_broadcast(&r->cond); + } + qemu_mutex_unlock(&r->lock); +} @@ -58,6 +58,7 @@ int main(int argc, char **argv) #include <glib.h> +#include "qemu/sockets.h" #include "hw/hw.h" #include "hw/boards.h" #include "hw/usb.h" @@ -103,7 +104,6 @@ int main(int argc, char **argv) #include "disas/disas.h" -#include "qemu/sockets.h" #include "slirp/libslirp.h" @@ -143,6 +143,9 @@ int vga_interface_type = VGA_NONE; static int full_screen = 0; static int no_frame = 0; int no_quit = 0; +#ifdef CONFIG_GTK +static bool grab_on_hover; +#endif CharDriverState *serial_hds[MAX_SERIAL_PORTS]; CharDriverState *parallel_hds[MAX_PARALLEL_PORTS]; CharDriverState *virtcon_hds[MAX_VIRTIO_CONSOLES]; @@ -213,6 +216,7 @@ uint32_t xen_domid; enum xen_mode xen_mode = XEN_EMULATE; static int tcg_tb_size; +static int has_defaults = 1; static int default_serial = 1; static int default_parallel = 1; static int default_virtcon = 1; @@ -973,7 +977,8 @@ static void parse_name(QemuOpts *opts) bool usb_enabled(bool default_usb) { - return qemu_opt_get_bool(qemu_get_machine_opts(), "usb", default_usb); + return qemu_opt_get_bool(qemu_get_machine_opts(), "usb", + has_defaults && default_usb); } #ifndef _WIN32 @@ -1204,7 +1209,7 @@ DeviceState *get_boot_device(uint32_t position) * memory pointed by "size" is assigned total length of the array in bytes * */ -char *get_boot_devices_list(size_t *size) +char *get_boot_devices_list(size_t *size, bool ignore_suffixes) { FWBootEntry *i; size_t total = 0; @@ -1219,7 +1224,7 @@ char *get_boot_devices_list(size_t *size) assert(devpath); } - if (i->suffix && devpath) { + if (i->suffix && !ignore_suffixes && devpath) { size_t bootpathlen = strlen(devpath) + strlen(i->suffix) + 1; bootpath = g_malloc(bootpathlen); @@ -1227,9 +1232,11 @@ char *get_boot_devices_list(size_t *size) g_free(devpath); } else if (devpath) { bootpath = devpath; - } else { + } else if (!ignore_suffixes) { assert(i->suffix); bootpath = g_strdup(i->suffix); + } else { + bootpath = g_strdup(""); } if (total) { @@ -1571,54 +1578,84 @@ void pcmcia_info(Monitor *mon, const QDict *qdict) /***********************************************************/ /* machine registration */ -static QEMUMachine *first_machine = NULL; -QEMUMachine *current_machine = NULL; +MachineState *current_machine; + +static void machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->qemu_machine = data; +} int qemu_register_machine(QEMUMachine *m) { - QEMUMachine **pm; - pm = &first_machine; - while (*pm != NULL) - pm = &(*pm)->next; - m->next = NULL; - *pm = m; + char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); + TypeInfo ti = { + .name = name, + .parent = TYPE_MACHINE, + .class_init = machine_class_init, + .class_data = (void *)m, + }; + + type_register(&ti); + g_free(name); + return 0; } -static QEMUMachine *find_machine(const char *name) +static MachineClass *find_machine(const char *name) { - QEMUMachine *m; + GSList *el, *machines = object_class_get_list(TYPE_MACHINE, false); + MachineClass *mc = NULL; + + for (el = machines; el; el = el->next) { + MachineClass *temp = el->data; - for(m = first_machine; m != NULL; m = m->next) { - if (!strcmp(m->name, name)) - return m; - if (m->alias && !strcmp(m->alias, name)) - return m; + if (!strcmp(temp->qemu_machine->name, name)) { + mc = temp; + break; + } + if (temp->qemu_machine->alias && + !strcmp(temp->qemu_machine->alias, name)) { + mc = temp; + break; + } } - return NULL; + + g_slist_free(machines); + return mc; } -QEMUMachine *find_default_machine(void) +MachineClass *find_default_machine(void) { - QEMUMachine *m; + GSList *el, *machines = object_class_get_list(TYPE_MACHINE, false); + MachineClass *mc = NULL; - for(m = first_machine; m != NULL; m = m->next) { - if (m->is_default) { - return m; + for (el = machines; el; el = el->next) { + MachineClass *temp = el->data; + + if (temp->qemu_machine->is_default) { + mc = temp; + break; } } - return NULL; + + g_slist_free(machines); + return mc; } MachineInfoList *qmp_query_machines(Error **errp) { + GSList *el, *machines = object_class_get_list(TYPE_MACHINE, false); MachineInfoList *mach_list = NULL; QEMUMachine *m; - for (m = first_machine; m; m = m->next) { + for (el = machines; el; el = el->next) { + MachineClass *mc = el->data; MachineInfoList *entry; MachineInfo *info; + m = mc->qemu_machine; info = g_malloc0(sizeof(*info)); if (m->is_default) { info->has_is_default = true; @@ -1639,6 +1676,7 @@ MachineInfoList *qmp_query_machines(Error **errp) mach_list = entry; } + g_slist_free(machines); return mach_list; } @@ -1832,8 +1870,12 @@ void qemu_devices_reset(void) void qemu_system_reset(bool report) { - if (current_machine && current_machine->reset) { - current_machine->reset(); + MachineClass *mc; + + mc = current_machine ? MACHINE_GET_CLASS(current_machine) : NULL; + + if (mc && mc->qemu_machine->reset) { + mc->qemu_machine->reset(); } else { qemu_devices_reset(); } @@ -1879,6 +1921,8 @@ void qemu_register_suspend_notifier(Notifier *notifier) void qemu_system_wakeup_request(WakeupReason reason) { + trace_system_wakeup_request(reason); + if (!runstate_check(RUN_STATE_SUSPENDED)) { return; } @@ -2087,7 +2131,7 @@ static void select_vgahw (const char *p) { const char *opts; - vga_interface_type = VGA_NONE; + assert(vga_interface_type == VGA_NONE); if (strstart(p, "std", &opts)) { if (vga_available()) { vga_interface_type = VGA_STD; @@ -2239,6 +2283,25 @@ static DisplayType select_display(const char *p) } else if (strstart(p, "gtk", &opts)) { #ifdef CONFIG_GTK display = DT_GTK; + while (*opts) { + const char *nextopt; + + if (strstart(opts, ",grab_on_hover=", &nextopt)) { + opts = nextopt; + if (strstart(opts, "on", &nextopt)) { + grab_on_hover = true; + } else if (strstart(opts, "off", &nextopt)) { + grab_on_hover = false; + } else { + goto invalid_gtk_args; + } + } else { + invalid_gtk_args: + fprintf(stderr, "Invalid GTK option string: %s\n", p); + exit(1); + } + opts = nextopt; + } #else fprintf(stderr, "GTK support is disabled\n"); exit(1); @@ -2603,24 +2666,34 @@ static int debugcon_parse(const char *devname) return 0; } -static QEMUMachine *machine_parse(const char *name) +static MachineClass *machine_parse(const char *name) { - QEMUMachine *m, *machine = NULL; + MachineClass *mc = NULL; + GSList *el, *machines = object_class_get_list(TYPE_MACHINE, false); if (name) { - machine = find_machine(name); + mc = find_machine(name); } - if (machine) { - return machine; + if (mc) { + return mc; } - printf("Supported machines are:\n"); - for (m = first_machine; m != NULL; m = m->next) { - if (m->alias) { - printf("%-20s %s (alias of %s)\n", m->alias, m->desc, m->name); + if (name && !is_help_option(name)) { + error_report("Unsupported machine type"); + error_printf("Use -machine help to list supported machines!\n"); + } else { + printf("Supported machines are:\n"); + for (el = machines; el; el = el->next) { + MachineClass *mc = el->data; + QEMUMachine *m = mc->qemu_machine; + if (m->alias) { + printf("%-20s %s (alias of %s)\n", m->alias, m->desc, m->name); + } + printf("%-20s %s%s\n", m->name, m->desc, + m->is_default ? " (default)" : ""); } - printf("%-20s %s%s\n", m->name, m->desc, - m->is_default ? " (default)" : ""); } + + g_slist_free(machines); exit(!name || !is_help_option(name)); } @@ -2869,9 +2942,10 @@ int main(int argc, char **argv, char **envp) int optind; const char *optarg; const char *loadvm = NULL; + MachineClass *machine_class; QEMUMachine *machine; const char *cpu_model; - const char *vga_model = "none"; + const char *vga_model = NULL; const char *qtest_chrdev = NULL; const char *qtest_log = NULL; const char *pid_file = NULL; @@ -2943,7 +3017,7 @@ int main(int argc, char **argv, char **envp) os_setup_early_signal_handling(); module_call_init(MODULE_INIT_MACHINE); - machine = find_default_machine(); + machine_class = find_default_machine(); cpu_model = NULL; ram_size = 0; snapshot = 0; @@ -3009,7 +3083,7 @@ int main(int argc, char **argv, char **envp) } switch(popt->index) { case QEMU_OPTION_M: - machine = machine_parse(optarg); + machine_class = machine_parse(optarg); break; case QEMU_OPTION_no_kvm_irqchip: { olist = qemu_find_opts("machine"); @@ -3565,7 +3639,7 @@ int main(int argc, char **argv, char **envp) } optarg = qemu_opt_get(opts, "type"); if (optarg) { - machine = machine_parse(optarg); + machine_class = machine_parse(optarg); } break; case QEMU_OPTION_no_kvm: @@ -3721,16 +3795,7 @@ int main(int argc, char **argv, char **envp) runstate_set(RUN_STATE_INMIGRATE); break; case QEMU_OPTION_nodefaults: - default_serial = 0; - default_parallel = 0; - default_virtcon = 0; - default_sclp = 0; - default_monitor = 0; - default_net = 0; - default_floppy = 0; - default_cdrom = 0; - default_sdcard = 0; - default_vga = 0; + has_defaults = 0; break; case QEMU_OPTION_xen_domid: if (!(xen_available())) { @@ -3871,11 +3936,17 @@ int main(int argc, char **argv, char **envp) } #endif - if (machine == NULL) { + if (machine_class == NULL) { fprintf(stderr, "No machine found.\n"); exit(1); } + current_machine = MACHINE(object_new(object_class_get_name( + OBJECT_CLASS(machine_class)))); + object_property_add_child(object_get_root(), "machine", + OBJECT(current_machine), &error_abort); + + machine = machine_class->qemu_machine; if (machine->hw_version) { qemu_set_version(machine->hw_version); } @@ -3957,27 +4028,35 @@ int main(int argc, char **argv, char **envp) qemu_opts_foreach(qemu_find_opts("device"), default_driver_check, NULL, 0); qemu_opts_foreach(qemu_find_opts("global"), default_driver_check, NULL, 0); - if (machine->no_serial) { + if (!vga_model && !default_vga) { + vga_interface_type = VGA_DEVICE; + } + if (!has_defaults || machine->no_serial) { default_serial = 0; } - if (machine->no_parallel) { + if (!has_defaults || machine->no_parallel) { default_parallel = 0; } - if (!machine->use_virtcon) { + if (!has_defaults || !machine->use_virtcon) { default_virtcon = 0; } - if (!machine->use_sclp) { + if (!has_defaults || !machine->use_sclp) { default_sclp = 0; } - if (machine->no_floppy) { + if (!has_defaults || machine->no_floppy) { default_floppy = 0; } - if (machine->no_cdrom) { + if (!has_defaults || machine->no_cdrom) { default_cdrom = 0; } - if (machine->no_sdcard) { + if (!has_defaults || machine->no_sdcard) { default_sdcard = 0; } + if (!has_defaults) { + default_monitor = 0; + default_net = 0; + default_vga = 0; + } if (is_daemonized()) { /* According to documentation and historically, -nographic redirects @@ -4282,7 +4361,9 @@ int main(int argc, char **argv, char **envp) vga_model = "std"; } } - select_vgahw(vga_model); + if (vga_model) { + select_vgahw(vga_model); + } if (watchdog) { i = select_watchdog(watchdog); @@ -4304,7 +4385,9 @@ int main(int argc, char **argv, char **envp) .kernel_cmdline = kernel_cmdline, .initrd_filename = initrd_filename, .cpu_model = cpu_model }; - machine->init(&args); + + current_machine->init_args = args; + machine->init(¤t_machine->init_args); audio_init(); @@ -4312,8 +4395,6 @@ int main(int argc, char **argv, char **envp) set_numa_modes(); - current_machine = machine; - /* init USB devices */ if (usb_enabled(false)) { if (foreach_device_config(DEV_USB, usb_parse) < 0) @@ -4349,7 +4430,7 @@ int main(int argc, char **argv, char **envp) #endif #if defined(CONFIG_GTK) case DT_GTK: - gtk_display_init(ds, full_screen); + gtk_display_init(ds, full_screen, grab_on_hover); break; #endif default: |
