diff options
29 files changed, 253 insertions, 224 deletions
diff --git a/block/iscsi.c b/block/iscsi.c index ed375fc..12ddbfb 100644 --- a/block/iscsi.c +++ b/block/iscsi.c @@ -1286,7 +1286,7 @@ static int iscsi_open(BlockDriverState *bs, QDict *options, int flags, QemuOpts *opts; Error *local_err = NULL; const char *filename; - int i, ret; + int i, ret = 0; if ((BDRV_SECTOR_SIZE % 512) != 0) { error_setg(errp, "iSCSI: Invalid BDRV_SECTOR_SIZE. " diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt index 9b57d5e..c6732fe 100644 --- a/docs/specs/pci-ids.txt +++ b/docs/specs/pci-ids.txt @@ -45,7 +45,7 @@ PCI devices (other than virtio): 1b36:0003 PCI Dual-port 16550A adapter (docs/specs/pci-serial.txt) 1b36:0004 PCI Quad-port 16550A adapter (docs/specs/pci-serial.txt) 1b36:0005 PCI test device (docs/specs/pci-testdev.txt) -1b36:0006 PCI SD Card Host Controller Interface (SDHCI) +1b36:0007 PCI SD Card Host Controller Interface (SDHCI) All these devices are documented in docs/specs. diff --git a/hw/char/serial.c b/hw/char/serial.c index 6d522ff..3aca874 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -645,8 +645,17 @@ static int serial_post_load(void *opaque, int version_id) static bool serial_thr_ipending_needed(void *opaque) { SerialState *s = opaque; - bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); - return s->thr_ipending != expected_value; + + if (s->ier & UART_IER_THRI) { + bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); + return s->thr_ipending != expected_value; + } else { + /* LSR.THRE will be sampled again when the interrupt is + * enabled. thr_ipending is not used in this case, do + * not migrate it. + */ + return false; + } } const VMStateDescription vmstate_serial_thr_ipending = { diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 2b0cd3d..9b9a7d7 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -101,6 +101,12 @@ #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */ #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */ +/* OSes typically write 0xdd/0xdf to turn the A20 line off and on. + * We make the default value of the outport include these four bits, + * so that the subsection is rarely necessary. + */ +#define KBD_OUT_ONES 0xcc + /* Mouse Commands */ #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ @@ -367,13 +373,13 @@ static void kbd_reset(void *opaque) s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; - s->outport = KBD_OUT_RESET | KBD_OUT_A20; + s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES; s->outport_present = false; } static uint8_t kbd_outport_default(KBDState *s) { - return KBD_OUT_RESET | KBD_OUT_A20 + return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0) | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0); } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 38a8a09..6a15448 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -142,10 +142,12 @@ struct TranslationBlock { uint64_t flags; /* flags defining in which context the code was generated */ uint16_t size; /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ - uint16_t cflags; /* compile flags */ + uint16_t icount; + uint32_t cflags; /* compile flags */ #define CF_COUNT_MASK 0x7fff #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ #define CF_NOCACHE 0x10000 /* To be freed after execution */ +#define CF_USE_ICOUNT 0x20000 void *tc_ptr; /* pointer to the translated code */ /* next matching tb for physical address. */ @@ -169,7 +171,6 @@ struct TranslationBlock { jmp_first */ struct TranslationBlock *jmp_next[2]; struct TranslationBlock *jmp_first; - uint32_t icount; }; #include "exec/spinlock.h" diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index da53395..221aad0 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -9,7 +9,7 @@ static TCGArg *icount_arg; static int icount_label; static int exitreq_label; -static inline void gen_tb_start(void) +static inline void gen_tb_start(TranslationBlock *tb) { TCGv_i32 count; TCGv_i32 flag; @@ -21,7 +21,7 @@ static inline void gen_tb_start(void) tcg_gen_brcondi_i32(TCG_COND_NE, flag, 0, exitreq_label); tcg_temp_free_i32(flag); - if (!use_icount) + if (!(tb->cflags & CF_USE_ICOUNT)) return; icount_label = gen_new_label(); @@ -43,7 +43,7 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns) gen_set_label(exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); - if (use_icount) { + if (tb->cflags & CF_USE_ICOUNT) { *icount_arg = num_insns; gen_set_label(icount_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_ICOUNT_EXPIRED); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 97e4257..97a83d3 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -88,7 +88,7 @@ #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 -#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0006 +#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 #define FMT_PCIBUS PRIx64 diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 492bce1..93c2ae2 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -122,11 +122,11 @@ #endif #ifndef atomic_read -#define atomic_read(ptr) (*(__typeof__(*ptr) *volatile) (ptr)) +#define atomic_read(ptr) (*(__typeof__(*ptr) volatile*) (ptr)) #endif #ifndef atomic_set -#define atomic_set(ptr, i) ((*(__typeof__(*ptr) *volatile) (ptr)) = (i)) +#define atomic_set(ptr, i) ((*(__typeof__(*ptr) volatile*) (ptr)) = (i)) #endif /* These have the same semantics as Java volatile variables. diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 76658a0..f888367 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1285,7 +1285,7 @@ static int cpu_pr_data(int pr) return 0; } -static ExitStatus gen_mfpr(TCGv va, int regno) +static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) { int data = cpu_pr_data(regno); @@ -1295,7 +1295,7 @@ static ExitStatus gen_mfpr(TCGv va, int regno) if (regno == 249) { helper = gen_helper_get_vmtime; } - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); helper(va); gen_io_end(); @@ -2283,7 +2283,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) case 0xC000: /* RPCC */ va = dest_gpr(ctx, ra); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); @@ -2317,7 +2317,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); va = dest_gpr(ctx, ra); - ret = gen_mfpr(va, insn & 0xffff); + ret = gen_mfpr(ctx, va, insn & 0xffff); break; #else goto invalid_opc; @@ -2828,7 +2828,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, pc_mask = ~TARGET_PAGE_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 80d2c07..80d2359 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1372,7 +1372,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, break; } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -1403,7 +1403,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, } } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->is_jmp = DISAS_UPDATE; @@ -10962,7 +10962,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); tcg_clear_temp_count(); diff --git a/target-arm/translate.c b/target-arm/translate.c index b52c758..bdfcdf1 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7170,7 +7170,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) break; } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -7261,7 +7261,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); gen_lookup_tb(s); @@ -11080,7 +11080,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); tcg_clear_temp_count(); diff --git a/target-cris/translate.c b/target-cris/translate.c index 76406af..b675ed0 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3202,7 +3202,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { check_breakpoint(env, dc); diff --git a/target-i386/translate.c b/target-i386/translate.c index fc75da7..ebdc350 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1168,8 +1168,9 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot) static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_string_movl_A0_EDI(s); /* Note: we must do this dummy write first to be restartable in case of page fault. */ @@ -1181,14 +1182,16 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot) gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); + } } static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); @@ -1199,8 +1202,9 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); + } } /* same method as Valgrind : we generate jumps to current or next @@ -6278,7 +6282,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6293,7 +6297,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_outs(s, ot); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6309,12 +6313,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_movi_tl(cpu_T[0], val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6328,12 +6333,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T[1], R_EAX); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6344,12 +6350,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6362,12 +6369,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T[1], R_EAX); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7065,10 +7073,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_rdtsc(cpu_env); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7451,10 +7460,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op; gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_rdtscp(cpu_env); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7962,7 +7972,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, record/replay modes and there will always be an additional step for ecx=0 when icount is enabled. */ - dc->repz_opt = !dc->jmp_opt && !use_icount; + dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -7992,7 +8002,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); for(;;) { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { @@ -8040,7 +8050,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - if (use_icount + if ((tb->cflags & CF_USE_ICOUNT) && ((pc_ptr & TARGET_PAGE_MASK) != ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) || (pc_ptr & ~TARGET_PAGE_MASK) == 0)) { diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 8454e8b..a7579dc 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -865,24 +865,24 @@ static void dec_wcsr(DisasContext *dc) break; case CSR_IM: /* mark as an io operation because it could cause an interrupt */ - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp = DISAS_UPDATE; break; case CSR_IP: /* mark as an io operation because it could cause an interrupt */ - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp = DISAS_UPDATE; @@ -1095,7 +1095,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { check_breakpoint(env, dc); diff --git a/target-m68k/translate.c b/target-m68k/translate.c index efd4cfc..47edc7a 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3010,7 +3010,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); do { pc_offset = dc->pc - pc_start; gen_throws_exception = NULL; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index fd2b771..69ce4df 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1720,7 +1720,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); do { #if SIM_COMPAT diff --git a/target-mips/translate.c b/target-mips/translate.c index 1205909..e9d86b2 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5123,10 +5123,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_mfc0_count(arg, cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -5499,8 +5500,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS32); - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } switch (reg) { case 0: @@ -6118,7 +6120,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) (void)rn; /* avoid a compiler warning */ LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); ctx->bstate = BS_STOP; } @@ -6369,10 +6371,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_mfc0_count(arg, cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -6738,8 +6741,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS64); - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } switch (reg) { case 0: @@ -7045,11 +7049,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) save_cpu_state(ctx, 1); /* Mark as an IO operation because we may trigger a software interrupt. */ - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mtc0_cause(cpu_env, arg); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } /* Stop translation as we may have triggered an intetrupt */ @@ -7358,7 +7362,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) (void)rn; /* avoid a compiler warning */ LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); ctx->bstate = BS_STOP; } @@ -19126,7 +19130,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, if (max_insns == 0) max_insns = CF_COUNT_MASK; LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); - gen_tb_start(); + gen_tb_start(tb); while (ctx.bstate == BS_NONE) { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-moxie/translate.c b/target-moxie/translate.c index 4541b9b..564f3ee 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -843,7 +843,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, ctx.bstate = BS_NONE; num_insns = 0; - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 407bd97..7dea405 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1675,7 +1675,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { check_breakpoint(cpu, dc); diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 068fcb2..f42589c 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -320,6 +320,7 @@ typedef struct opc_handler_t opc_handler_t; /*****************************************************************************/ /* Types used to describe some PowerPC registers */ typedef struct CPUPPCState CPUPPCState; +typedef struct DisasContext DisasContext; typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_spr_t ppc_spr_t; typedef struct ppc_dcr_t ppc_dcr_t; @@ -328,13 +329,13 @@ typedef union ppc_tlb_t ppc_tlb_t; /* SPR access micro-ops generations callbacks */ struct ppc_spr_t { - void (*uea_read)(void *opaque, int gpr_num, int spr_num); - void (*uea_write)(void *opaque, int spr_num, int gpr_num); + void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num); + void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num); #if !defined(CONFIG_USER_ONLY) - void (*oea_read)(void *opaque, int gpr_num, int spr_num); - void (*oea_write)(void *opaque, int spr_num, int gpr_num); - void (*hea_read)(void *opaque, int gpr_num, int spr_num); - void (*hea_write)(void *opaque, int spr_num, int gpr_num); + void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num); + void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); + void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); + void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); #endif const char *name; target_ulong default_value; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d381632..2e32e8d 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -183,7 +183,7 @@ void ppc_translate_init(void) } /* internal defines */ -typedef struct DisasContext { +struct DisasContext { struct TranslationBlock *tb; target_ulong nip; uint32_t opcode; @@ -207,7 +207,7 @@ typedef struct DisasContext { int singlestep_enabled; uint64_t insns_flags; uint64_t insns_flags2; -} DisasContext; +}; /* Return true iff byteswap is needed in a scalar memop */ static inline bool need_byteswap(const DisasContext *ctx) @@ -4206,7 +4206,7 @@ static void gen_mfmsr(DisasContext *ctx) #endif } -static void spr_noaccess(void *opaque, int gprn, int sprn) +static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) { #if 0 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); @@ -4218,7 +4218,7 @@ static void spr_noaccess(void *opaque, int gprn, int sprn) /* mfspr */ static inline void gen_op_mfspr(DisasContext *ctx) { - void (*read_cb)(void *opaque, int gprn, int sprn); + void (*read_cb)(DisasContext *ctx, int gprn, int sprn); uint32_t sprn = SPR(ctx->opcode); #if !defined(CONFIG_USER_ONLY) @@ -4369,7 +4369,7 @@ static void gen_mtmsr(DisasContext *ctx) /* mtspr */ static void gen_mtspr(DisasContext *ctx) { - void (*write_cb)(void *opaque, int sprn, int gprn); + void (*write_cb)(DisasContext *ctx, int sprn, int gprn); uint32_t sprn = SPR(ctx->opcode); #if !defined(CONFIG_USER_ONLY) @@ -11329,7 +11329,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); tcg_clear_temp_count(); /* Set env in case of segfault during code fetch */ while (ctx.exception == POWERPC_EXCP_NONE diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 1fece7b..f0a2999 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -65,7 +65,7 @@ static void spr_load_dump_spr(int sprn) #endif } -static void spr_read_generic (void *opaque, int gprn, int sprn) +static void spr_read_generic (DisasContext *ctx, int gprn, int sprn) { gen_load_spr(cpu_gpr[gprn], sprn); spr_load_dump_spr(sprn); @@ -80,14 +80,14 @@ static void spr_store_dump_spr(int sprn) #endif } -static void spr_write_generic (void *opaque, int sprn, int gprn) +static void spr_write_generic (DisasContext *ctx, int sprn, int gprn) { gen_store_spr(sprn, cpu_gpr[gprn]); spr_store_dump_spr(sprn); } #if !defined(CONFIG_USER_ONLY) -static void spr_write_generic32(void *opaque, int sprn, int gprn) +static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { #ifdef TARGET_PPC64 TCGv t0 = tcg_temp_new(); @@ -96,11 +96,11 @@ static void spr_write_generic32(void *opaque, int sprn, int gprn) tcg_temp_free(t0); spr_store_dump_spr(sprn); #else - spr_write_generic(opaque, sprn, gprn); + spr_write_generic(ctx, sprn, gprn); #endif } -static void spr_write_clear (void *opaque, int sprn, int gprn) +static void spr_write_clear (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -112,7 +112,7 @@ static void spr_write_clear (void *opaque, int sprn, int gprn) tcg_temp_free(t1); } -static void spr_access_nop(void *opaque, int sprn, int gprn) +static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) { } @@ -120,47 +120,47 @@ static void spr_access_nop(void *opaque, int sprn, int gprn) /* SPR common to all PowerPC */ /* XER */ -static void spr_read_xer (void *opaque, int gprn, int sprn) +static void spr_read_xer (DisasContext *ctx, int gprn, int sprn) { gen_read_xer(cpu_gpr[gprn]); } -static void spr_write_xer (void *opaque, int sprn, int gprn) +static void spr_write_xer (DisasContext *ctx, int sprn, int gprn) { gen_write_xer(cpu_gpr[gprn]); } /* LR */ -static void spr_read_lr (void *opaque, int gprn, int sprn) +static void spr_read_lr (DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); } -static void spr_write_lr (void *opaque, int sprn, int gprn) +static void spr_write_lr (DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); } /* CFAR */ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -static void spr_read_cfar (void *opaque, int gprn, int sprn) +static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); } -static void spr_write_cfar (void *opaque, int sprn, int gprn) +static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); } #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ /* CTR */ -static void spr_read_ctr (void *opaque, int gprn, int sprn) +static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); } -static void spr_write_ctr (void *opaque, int sprn, int gprn) +static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); } @@ -171,13 +171,13 @@ static void spr_write_ctr (void *opaque, int sprn, int gprn) /* UPMCx */ /* USIA */ /* UDECR */ -static void spr_read_ureg (void *opaque, int gprn, int sprn) +static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn) { gen_load_spr(cpu_gpr[gprn], sprn + 0x10); } #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -static void spr_write_ureg(void *opaque, int sprn, int gprn) +static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) { gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); } @@ -186,109 +186,109 @@ static void spr_write_ureg(void *opaque, int sprn, int gprn) /* SPR common to all non-embedded PowerPC */ /* DECR */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_decr (void *opaque, int gprn, int sprn) +static void spr_read_decr (DisasContext *ctx, int gprn, int sprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_decr(cpu_gpr[gprn], cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } -static void spr_write_decr (void *opaque, int sprn, int gprn) +static void spr_write_decr (DisasContext *ctx, int sprn, int gprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } #endif /* SPR common to all non-embedded PowerPC, except 601 */ /* Time base */ -static void spr_read_tbl (void *opaque, int gprn, int sprn) +static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } -static void spr_read_tbu (void *opaque, int gprn, int sprn) +static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } __attribute__ (( unused )) -static void spr_read_atbl (void *opaque, int gprn, int sprn) +static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); } __attribute__ (( unused )) -static void spr_read_atbu (void *opaque, int gprn, int sprn) +static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); } #if !defined(CONFIG_USER_ONLY) -static void spr_write_tbl (void *opaque, int sprn, int gprn) +static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } -static void spr_write_tbu (void *opaque, int sprn, int gprn) +static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } __attribute__ (( unused )) -static void spr_write_atbl (void *opaque, int sprn, int gprn) +static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); } __attribute__ (( unused )) -static void spr_write_atbu (void *opaque, int sprn, int gprn) +static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); } #if defined(TARGET_PPC64) __attribute__ (( unused )) -static void spr_read_purr (void *opaque, int gprn, int sprn) +static void spr_read_purr (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_purr(cpu_gpr[gprn], cpu_env); } @@ -298,38 +298,38 @@ static void spr_read_purr (void *opaque, int gprn, int sprn) #if !defined(CONFIG_USER_ONLY) /* IBAT0U...IBAT0U */ /* IBAT0L...IBAT7L */ -static void spr_read_ibat (void *opaque, int gprn, int sprn) +static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); } -static void spr_read_ibat_h (void *opaque, int gprn, int sprn) +static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2])); } -static void spr_write_ibatu (void *opaque, int sprn, int gprn) +static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) +static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_ibatl (void *opaque, int sprn, int gprn) +static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) +static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); @@ -338,38 +338,38 @@ static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) /* DBAT0U...DBAT7U */ /* DBAT0L...DBAT7L */ -static void spr_read_dbat (void *opaque, int gprn, int sprn) +static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); } -static void spr_read_dbat_h (void *opaque, int gprn, int sprn) +static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); } -static void spr_write_dbatu (void *opaque, int sprn, int gprn) +static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_dbatu_h (void *opaque, int sprn, int gprn) +static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_dbatl (void *opaque, int sprn, int gprn) +static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) +static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); @@ -377,19 +377,19 @@ static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) } /* SDR1 */ -static void spr_write_sdr1 (void *opaque, int sprn, int gprn) +static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); } /* 64 bits PowerPC specific SPRs */ #if defined(TARGET_PPC64) -static void spr_read_hior (void *opaque, int gprn, int sprn) +static void spr_read_hior (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); } -static void spr_write_hior (void *opaque, int sprn, int gprn) +static void spr_write_hior (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); @@ -401,31 +401,29 @@ static void spr_write_hior (void *opaque, int sprn, int gprn) /* PowerPC 601 specific registers */ /* RTC */ -static void spr_read_601_rtcl (void *opaque, int gprn, int sprn) +static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); } -static void spr_read_601_rtcu (void *opaque, int gprn, int sprn) +static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); } #if !defined(CONFIG_USER_ONLY) -static void spr_write_601_rtcu (void *opaque, int sprn, int gprn) +static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); } -static void spr_write_601_rtcl (void *opaque, int sprn, int gprn) +static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); } -static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) +static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn) { - DisasContext *ctx = opaque; - gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); /* Must stop the translation as endianness may have changed */ gen_stop_exception(ctx); @@ -434,19 +432,19 @@ static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) /* Unified bats */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_601_ubat (void *opaque, int gprn, int sprn) +static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); } -static void spr_write_601_ubatu (void *opaque, int sprn, int gprn) +static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) +static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); @@ -456,36 +454,34 @@ static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) /* PowerPC 40x specific registers */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_40x_pit (void *opaque, int gprn, int sprn) +static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); } -static void spr_write_40x_pit (void *opaque, int sprn, int gprn) +static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); } -static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) +static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn) { - DisasContext *ctx = opaque; - gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); /* We must stop translation as we may have rebooted */ gen_stop_exception(ctx); } -static void spr_write_40x_sler (void *opaque, int sprn, int gprn) +static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); } -static void spr_write_booke_tcr (void *opaque, int sprn, int gprn) +static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); } -static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) +static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); } @@ -494,19 +490,19 @@ static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) /* PowerPC 403 specific registers */ /* PBL1 / PBU1 / PBL2 / PBU2 */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_403_pbr (void *opaque, int gprn, int sprn) +static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); } -static void spr_write_403_pbr (void *opaque, int sprn, int gprn) +static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_pir (void *opaque, int sprn, int gprn) +static void spr_write_pir (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); @@ -516,7 +512,7 @@ static void spr_write_pir (void *opaque, int sprn, int gprn) #endif /* SPE specific registers */ -static void spr_read_spefscr (void *opaque, int gprn, int sprn) +static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn) { TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); @@ -524,7 +520,7 @@ static void spr_read_spefscr (void *opaque, int gprn, int sprn) tcg_temp_free_i32(t0); } -static void spr_write_spefscr (void *opaque, int sprn, int gprn) +static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); @@ -534,7 +530,7 @@ static void spr_write_spefscr (void *opaque, int sprn, int gprn) #if !defined(CONFIG_USER_ONLY) /* Callback used to write the exception vector base */ -static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) +static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); @@ -544,9 +540,8 @@ static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) tcg_temp_free(t0); } -static void spr_write_excp_vector (void *opaque, int sprn, int gprn) +static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn) { - DisasContext *ctx = opaque; int sprn_offs; if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { @@ -604,12 +599,12 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val) static inline void _spr_register(CPUPPCState *env, int num, const char *name, - void (*uea_read)(void *opaque, int gprn, int sprn), - void (*uea_write)(void *opaque, int sprn, int gprn), + void (*uea_read)(DisasContext *ctx, int gprn, int sprn), + void (*uea_write)(DisasContext *ctx, int sprn, int gprn), #if !defined(CONFIG_USER_ONLY) - void (*oea_read)(void *opaque, int gprn, int sprn), - void (*oea_write)(void *opaque, int sprn, int gprn), + void (*oea_read)(DisasContext *ctx, int gprn, int sprn), + void (*oea_write)(DisasContext *ctx, int sprn, int gprn), #endif #if defined(CONFIG_KVM) uint64_t one_reg_id, @@ -1040,19 +1035,19 @@ static void gen_spr_7xx (CPUPPCState *env) #ifdef TARGET_PPC64 #ifndef CONFIG_USER_ONLY -static void spr_read_uamr (void *opaque, int gprn, int sprn) +static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn) { gen_load_spr(cpu_gpr[gprn], SPR_AMR); spr_load_dump_spr(SPR_AMR); } -static void spr_write_uamr (void *opaque, int sprn, int gprn) +static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn) { gen_store_spr(SPR_AMR, cpu_gpr[gprn]); spr_store_dump_spr(SPR_AMR); } -static void spr_write_uamr_pr (void *opaque, int sprn, int gprn) +static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); @@ -1454,7 +1449,7 @@ static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) } #if !defined(CONFIG_USER_ONLY) -static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) +static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); @@ -1463,7 +1458,7 @@ static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) tcg_temp_free(t0); } -static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn) +static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); @@ -1472,12 +1467,12 @@ static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn) tcg_temp_free(t0); } -static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) +static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn) { gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); } -static void spr_write_booke_pid (void *opaque, int sprn, int gprn) +static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(sprn); gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); @@ -1693,7 +1688,7 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, /* TLB assist registers */ /* XXX : not implemented */ for (i = 0; i < 8; i++) { - void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32; + void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32; if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { uea_write = &spr_write_generic; } @@ -4680,7 +4675,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) } #if !defined(CONFIG_USER_ONLY) -static void spr_write_mas73(void *opaque, int sprn, int gprn) +static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) { TCGv val = tcg_temp_new(); tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); @@ -4690,7 +4685,7 @@ static void spr_write_mas73(void *opaque, int sprn, int gprn) tcg_temp_free(val); } -static void spr_read_mas73(void *opaque, int gprn, int sprn) +static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) { TCGv mas7 = tcg_temp_new(); TCGv mas3 = tcg_temp_new(); @@ -7322,14 +7317,14 @@ enum BOOK3S_CPU_TYPE { BOOK3S_CPU_POWER8 }; -static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit, - int sprn, int cause) +static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, + int bit, int sprn, int cause) { TCGv_i32 t1 = tcg_const_i32(bit); TCGv_i32 t2 = tcg_const_i32(sprn); TCGv_i32 t3 = tcg_const_i32(cause); - gen_update_current_nip(opaque); + gen_update_current_nip(ctx); gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); tcg_temp_free_i32(t3); @@ -7337,14 +7332,14 @@ static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit, tcg_temp_free_i32(t1); } -static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit, - int sprn, int cause) +static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, + int bit, int sprn, int cause) { TCGv_i32 t1 = tcg_const_i32(bit); TCGv_i32 t2 = tcg_const_i32(sprn); TCGv_i32 t3 = tcg_const_i32(cause); - gen_update_current_nip(opaque); + gen_update_current_nip(ctx); gen_helper_msr_facility_check(cpu_env, t1, t2, t3); tcg_temp_free_i32(t3); @@ -7352,7 +7347,7 @@ static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit, tcg_temp_free_i32(t1); } -static void spr_read_prev_upper32(void *opaque, int gprn, int sprn) +static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) { TCGv spr_up = tcg_temp_new(); TCGv spr = tcg_temp_new(); @@ -7365,7 +7360,7 @@ static void spr_read_prev_upper32(void *opaque, int gprn, int sprn) tcg_temp_free(spr_up); } -static void spr_write_prev_upper32(void *opaque, int sprn, int gprn) +static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) { TCGv spr = tcg_temp_new(); @@ -7704,16 +7699,16 @@ static void gen_spr_power6_common(CPUPPCState *env) 0x00000000); } -static void spr_read_tar(void *opaque, int gprn, int sprn) +static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); - spr_read_generic(opaque, gprn, sprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_read_generic(ctx, gprn, sprn); } -static void spr_write_tar(void *opaque, int sprn, int gprn) +static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); - spr_write_generic(opaque, sprn, gprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_write_generic(ctx, sprn, gprn); } static void gen_spr_power8_tce_address_control(CPUPPCState *env) @@ -7724,28 +7719,28 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env) 0x00000000); } -static void spr_read_tm(void *opaque, int gprn, int sprn) +static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_read_generic(opaque, gprn, sprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_read_generic(ctx, gprn, sprn); } -static void spr_write_tm(void *opaque, int sprn, int gprn) +static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_write_generic(opaque, sprn, gprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_write_generic(ctx, sprn, gprn); } -static void spr_read_tm_upper32(void *opaque, int gprn, int sprn) +static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_read_prev_upper32(opaque, gprn, sprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_read_prev_upper32(ctx, gprn, sprn); } -static void spr_write_tm_upper32(void *opaque, int sprn, int gprn) +static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_write_prev_upper32(opaque, sprn, gprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_write_prev_upper32(ctx, sprn, gprn); } static void gen_spr_power8_tm(CPUPPCState *env) @@ -7768,28 +7763,28 @@ static void gen_spr_power8_tm(CPUPPCState *env) 0x00000000); } -static void spr_read_ebb(void *opaque, int gprn, int sprn) +static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_read_generic(opaque, gprn, sprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_generic(ctx, gprn, sprn); } -static void spr_write_ebb(void *opaque, int sprn, int gprn) +static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_write_generic(opaque, sprn, gprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_generic(ctx, sprn, gprn); } -static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn) +static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_read_prev_upper32(opaque, gprn, sprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_prev_upper32(ctx, gprn, sprn); } -static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn) +static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_write_prev_upper32(opaque, sprn, gprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_prev_upper32(ctx, sprn, gprn); } static void gen_spr_power8_ebb(CPUPPCState *env) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index dbf1993..ab01bc0 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -4779,7 +4779,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { if (search_pc) { diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 3088edc..7010740 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1890,7 +1890,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 78c4e21..25d1bd6 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5271,7 +5271,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-tricore/translate.c b/target-tricore/translate.c index dbcf87e..3b83782 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -5077,7 +5077,7 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb, ctx.mem_idx = cpu_mmu_index(env); tcg_clear_temp_count(); - gen_tb_start(); + gen_tb_start(tb); while (ctx.bstate == BS_NONE) { ctx.opcode = cpu_ldl_code(env, ctx.pc); decode_opc(env, &ctx, 0); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 653c225..ab7e96f 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1917,7 +1917,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, } #endif - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 6500554..9e137fe 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -3054,7 +3054,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu, dc.next_icount = tcg_temp_local_new_i32(); } - gen_tb_start(); + gen_tb_start(tb); if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { tcg_gen_movi_i32(cpu_pc, dc.pc); diff --git a/translate-all.c b/translate-all.c index c24cfe8..8fa4378 100644 --- a/translate-all.c +++ b/translate-all.c @@ -218,7 +218,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, gen_intermediate_code_pc(env, tb); - if (use_icount) { + if (tb->cflags & CF_USE_ICOUNT) { /* Reset the cycle counter to the start of the block. */ cpu->icount_decr.u16.low += tb->icount; /* Clear the IO flag. */ @@ -1045,6 +1045,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, int code_gen_size; phys_pc = get_page_addr_code(env, pc); + if (use_icount) { + cflags |= CF_USE_ICOUNT; + } tb = tb_alloc(pc); if (!tb) { /* flush must be done */ |
