diff options
| author | Andrew Jeffery <andrew@aj.id.au> | 2016-03-16 17:06:00 +0000 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2019-11-29 19:49:38 -0600 |
| commit | 30a6033be92c49bafae08e05b62a6b6fc0ec6bd7 (patch) | |
| tree | ff95fe02626da1dc5a10d0eba07bc3a05ceb72a8 /trace-events | |
| parent | 68baf6379cd022ff7b5f1df85de146d42d871358 (diff) | |
| download | hqemu-30a6033be92c49bafae08e05b62a6b6fc0ec6bd7.zip hqemu-30a6033be92c49bafae08e05b62a6b6fc0ec6bd7.tar.gz | |
hw/intc: Add (new) ASPEED VIC device model
Implement a basic ASPEED VIC device model for the AST2400 SoC[1], with
enough functionality to boot an aspeed_defconfig Linux kernel. The model
implements the 'new' (revised) register set: While the hardware exposes
both the new and legacy register sets, accesses to the model's legacy
register set will not be serviced (however the access will be logged).
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1458096317-25223-3-git-send-email-andrew@aj.id.au
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'trace-events')
| -rw-r--r-- | trace-events | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/trace-events b/trace-events index e589230..d494de1 100644 --- a/trace-events +++ b/trace-events @@ -1901,3 +1901,10 @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32 aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32 aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64 + +# hw/intc/aspeed_vic.c +aspeed_vic_set_irq(int irq, int level) "Enabling IRQ %d: %d" +aspeed_vic_update_fiq(int flags) "Raising FIQ: %d" +aspeed_vic_update_irq(int flags) "Raising IRQ: %d" +aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
