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authorJohn Snow <jsnow@redhat.com>2015-11-20 17:53:55 -0500
committerJohn Snow <jsnow@redhat.com>2015-11-24 14:51:43 -0500
commita421f3c38509ee4ce47230ec68c5c3a184efb538 (patch)
treea7841f8b6d1e2df49dde230d996d23dc5a3726fa /tests
parent4b6eda626fdb8bf90472c6868d502a2ac09abeeb (diff)
downloadhqemu-a421f3c38509ee4ce47230ec68c5c3a184efb538.zip
hqemu-a421f3c38509ee4ce47230ec68c5c3a184efb538.tar.gz
ide-test: cdrom_pio_impl fixup
Final tidying: move the interrupt wait into the loop, document that the status read clears the IRQ, and move the final interrupt check outside of the loop. This should be functionally equivalent to how it works currently, but a little less ambiguous and slightly more explicit about the state transitions. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 1448060035-31973-3-git-send-email-jsnow@redhat.com
Diffstat (limited to 'tests')
-rw-r--r--tests/ide-test.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/tests/ide-test.c b/tests/ide-test.c
index fc1ce52..46763db 100644
--- a/tests/ide-test.c
+++ b/tests/ide-test.c
@@ -709,9 +709,6 @@ static void cdrom_pio_impl(int nblocks)
/* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */
send_scsi_cdb_read10(0, nblocks);
- /* HP3: INTRQ_Wait */
- ide_wait_intr(IDE_PRIMARY_IRQ);
-
/* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
* If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.
* We allow an odd limit only when the remaining transfer size is
@@ -723,16 +720,25 @@ static void cdrom_pio_impl(int nblocks)
for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) {
size_t offset = i * (limit / 2);
size_t rem = (rxsize / 2) - offset;
- /* HP2: Check_Status_B */
+
+ /* HP3: INTRQ_Wait */
+ ide_wait_intr(IDE_PRIMARY_IRQ);
+
+ /* HP2: Check_Status_B (and clear IRQ) */
data = ide_wait_clear(BSY);
assert_bit_set(data, DRQ | DRDY);
assert_bit_clear(data, ERR | DF | BSY);
+
/* HP4: Transfer_Data */
for (j = 0; j < MIN((limit / 2), rem); j++) {
rx[offset + j] = le16_to_cpu(inw(IDE_BASE + reg_data));
}
- ide_wait_intr(IDE_PRIMARY_IRQ);
}
+
+ /* Check for final completion IRQ */
+ ide_wait_intr(IDE_PRIMARY_IRQ);
+
+ /* Sanity check final state */
data = ide_wait_clear(DRQ);
assert_bit_set(data, DRDY);
assert_bit_clear(data, DRQ | ERR | DF | BSY);
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