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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-11 11:03:34 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-11 11:03:34 +0000 |
commit | 8df1ca4ba51fc3bfccc3d901584b316ae2e60bb9 (patch) | |
tree | 58a0b1b3ac966f93be740eb812db1ad6587563bc /tcg/tcg.c | |
parent | 9843a0d2c62d683c1940cfd2d7c6533837b56bb2 (diff) | |
download | hqemu-8df1ca4ba51fc3bfccc3d901584b316ae2e60bb9.zip hqemu-8df1ca4ba51fc3bfccc3d901584b316ae2e60bb9.tar.gz |
Allocate register pair for 64-bit registers on 32-bit host.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4730 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tcg/tcg.c')
-rw-r--r-- | tcg/tcg.c | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -423,7 +423,7 @@ TCGv tcg_temp_new_internal(TCGType type, int temp_local) idx = s->nb_temps; #if TCG_TARGET_REG_BITS == 32 if (type == TCG_TYPE_I64) { - tcg_temp_alloc(s, s->nb_temps + 1); + tcg_temp_alloc(s, s->nb_temps + 2); ts = &s->temps[s->nb_temps]; ts->base_type = type; ts->type = TCG_TYPE_I32; @@ -1961,7 +1961,7 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf, break; } args += def->nb_args; - next: ; + next: if (search_pc >= 0 && search_pc < s->code_ptr - gen_code_buf) { return op_index; } |