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author | Andreas Färber <afaerber@suse.de> | 2013-08-27 00:28:06 +0200 |
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committer | Andreas Färber <afaerber@suse.de> | 2014-03-13 19:20:47 +0100 |
commit | d5a11fefef1eeed86a8f06021067ba9990729a5a (patch) | |
tree | 7a99e0676de042609104c21d98ff2a94be017c9a /target-xtensa | |
parent | f0c3c505a8ec1a948006b3a16a35864a2270a84b (diff) | |
download | hqemu-d5a11fefef1eeed86a8f06021067ba9990729a5a.zip hqemu-d5a11fefef1eeed86a8f06021067ba9990729a5a.tar.gz |
exec: Change tlb_fill() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-xtensa')
-rw-r--r-- | target-xtensa/op_helper.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index a314ed0..1c80e31 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -60,9 +60,11 @@ static void do_unaligned_access(CPUXtensaState *env, } } -void tlb_fill(CPUXtensaState *env, - target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, + target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) { + XtensaCPU *cpu = XTENSA_CPU(cs); + CPUXtensaState *env = &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; |