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| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-06-29 10:50:03 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2015-07-06 13:25:11 +0300 |
| commit | ddd44279fdbc545a9182cb642645af8a4672c267 (patch) | |
| tree | 2419cab26d887b77965daef5fdf552356523c589 /target-xtensa/translate.c | |
| parent | f50a1640fb82708a5d528dee1ace42a224b95b15 (diff) | |
| download | hqemu-ddd44279fdbc545a9182cb642645af8a4672c267.zip hqemu-ddd44279fdbc545a9182cb642645af8a4672c267.tar.gz | |
target-xtensa: add 64-bit floating point registers
Xtensa ISA got specification for 64-bit floating point registers and
opcodes, see ISA, 4.3.11 "Floating point coprocessor option".
Add 64-bit FP registers.
Although 64-bit floating point is currently not supported by xtensa
translator, these registers need to be reported to gdb with proper size,
otherwise it wouldn't find other registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 86e4849..f2118c2 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -228,7 +228,7 @@ void xtensa_translate_init(void) for (i = 0; i < 16; i++) { cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUXtensaState, fregs[i]), + offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), fregnames[i]); } @@ -3206,8 +3206,9 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, for (i = 0; i < 16; ++i) { cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, - float32_val(env->fregs[i]), - *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' '); + float32_val(env->fregs[i].f32[FP_F32_LOW]), + *(float *)(env->fregs[i].f32 + FP_F32_LOW), + (i % 2) == 1 ? '\n' : ' '); } } } |
