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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-02-25 11:46:55 +0000 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-03-16 15:44:48 +0000 |
| commit | 62e47b2e6d17020b78a676e086bf98cfeba595b7 (patch) | |
| tree | e4a20e86f21a8bf3c71dfc884e4b85109ad1cec4 /target-tricore/tricore-opcodes.h | |
| parent | f4aef476afc4cab9bb594975401f6902a57aa9b9 (diff) | |
| download | hqemu-62e47b2e6d17020b78a676e086bf98cfeba595b7.zip hqemu-62e47b2e6d17020b78a676e086bf98cfeba595b7.tar.gz | |
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode
Add helpers:
* msub64_q_ssov: multiply two 32 bit q-format number, sub the result from a
64 bit q-format number and saturate.
* msub32_q_sub_ssov: sub two 64 bit q-format numbers and return a 32 bit
result.
* msubr_q_ssov: multiply two 32 bit q-format numbers, sub the result from a 32 bit
q-format number and saturate.
* msubr_q: multiply two 32 bit q-format numbers and sub the result from a 32 bit
q-format number.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index e65696d..80e1753 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1328,8 +1328,8 @@ enum { OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d, OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24, OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c, - OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e, - OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e, + OPC2_32_RRR1_MSUBR_H_64_UL = 0x1e, + OPC2_32_RRR1_MSUBRS_H_64_UL = 0x3e, OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07, OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06, OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27, |
