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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2014-09-01 12:59:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-09-01 14:49:21 +0100 |
| commit | 5de93515f995066f709f6e1af5531a36ce6766bd (patch) | |
| tree | 73aa0ddf73a2ac68d3239a395ef1dcc19365b548 /target-tricore/translate.c | |
| parent | a47b50db609f95edf5b2f964a7a8087f094cfcfa (diff) | |
| download | hqemu-5de93515f995066f709f6e1af5531a36ce6766bd.zip hqemu-5de93515f995066f709f6e1af5531a36ce6766bd.tar.gz | |
target-tricore: Add instructions of SC opcode format
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-14-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-tricore/translate.c')
| -rw-r--r-- | target-tricore/translate.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 74db70d..5298712 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -680,6 +680,42 @@ static void decode_ssr_opc(DisasContext *ctx, int op1) } } +static void decode_sc_opc(DisasContext *ctx, int op1) +{ + int32_t const16; + + const16 = MASK_OP_SC_CONST8(ctx->opcode); + + switch (op1) { + case OPC1_16_SC_AND: + tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); + break; + case OPC1_16_SC_BISR: + gen_helper_1arg(bisr, const16 & 0xff); + break; + case OPC1_16_SC_LD_A: + gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); + break; + case OPC1_16_SC_LD_W: + gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); + break; + case OPC1_16_SC_MOV: + tcg_gen_movi_tl(cpu_gpr_d[15], const16); + break; + case OPC1_16_SC_OR: + tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); + break; + case OPC1_16_SC_ST_A: + gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); + break; + case OPC1_16_SC_ST_W: + gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); + break; + case OPC1_16_SC_SUB_A: + tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); + break; + } +} static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) { int op1; @@ -816,6 +852,18 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) address = MASK_OP_SBR_DISP4(ctx->opcode); gen_compute_branch(ctx, op1, r1, 0, 0, address); break; +/* SC-format */ + case OPC1_16_SC_AND: + case OPC1_16_SC_BISR: + case OPC1_16_SC_LD_A: + case OPC1_16_SC_LD_W: + case OPC1_16_SC_MOV: + case OPC1_16_SC_OR: + case OPC1_16_SC_ST_A: + case OPC1_16_SC_ST_W: + case OPC1_16_SC_SUB_A: + decode_sc_opc(ctx, op1); + break; } } |
